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37
DM35425HR User’s Manual
6.3.2
FB_DMA_CHANNELS
(R
EAD
-O
NLY
)
This register contains the number of DMA Channels in this Function Block. Each Channel contains a control register, and a set of Buffer
Descriptor Registers.
6.3.3
FB_DMA_BUFFERS
(R
EAD
-O
NLY
)
This register contains the number of Buffer Descriptors in each DMA Channel.
6.3.4
M
ODE
_S
TATUS
(R
EAD
/W
RITE
,
R
EAD
-O
NLY
)
Selects the current mode of operation and indicates its triggering status.
B[3:0]: Mode
o
0x04: Uninitialized. This is the power-on state. No converter initialization has taken place. Sampling is stopped, and all
counters are reset and the triggering state machine is reset. Transition to any of the other Modes will start converter
initialization (sampling will not start until initialization is complete).
o
0x00: Reset. Sampling is stopped. All counters are reset and the triggering state machine is reset.
o
0x01: Paused. Sampling is stopped, but the counters and triggering state machine maintain their state.
o
0x02: Go, Single-Shot. After filling the buffer with the Post-Stop samples, capturing stops. The Mode must be set back
to RESET in order to capture more samples.
o
0x03: Go, Re-arm. After filling the buffer with the Post-Stop samples and the FIFO is empty, the triggering state machine
is restarted, i.e. FIFO is filled with Pre-Start samples and waits for a start trigger.
B[7:4]: Status
o
0x08: Uninitialized
–
The status when in the “Uninitialized” mode and the converter requires initialization.
o
0x09: Initializing
o
0x00: Stopped
–
The status when in the “Reset” mode, or in the “Uninitialized” mode and the converter does not require
initialization.
o
0x01: Filling Pre-Trigger buffer
o
0x02: Waiting for start trigger
o
0x03: Sampling/Waiting for stop trigger
o
0x04: Filling Post-Stop buffer
o
0x05: Wait to re-arm
–
Waiting until local FIFO is empty so the pre-trigger buffer can be filled.
o
0x07: Done capturing
6.3.5
CLK_SRC
(R
EAD
/W
RITE
)
Selects the source for CLK_DIV from the clock bus.
Refer to
on page 30 for list of valid values.
6.3.6
START_TRIG
(R
EAD
/W
RITE
)
Selects the start trigger from the clock bus. CLK_DIV will start counting after the start trigger, unless PRE_TRIGGER_CAPTURE is non-zero
in which case CLK_DIV will start counting immediately.
Refer to
on page 30 for list of valid values.
6.3.7
STOP_TRIG
(R
EAD
/W
RITE
)
Selects the stop trigger from the clock bus.
Refer to
on page 30 for list of valid values.
6.3.8
CLK_DIV
(R
EAD
/W
RITE
)
Divider for the pacer clock. Pacer Clock Frequency = (Clk_Src_Frequency) / (1 + CLK_DIV). If synchronizing with the pacer clock from
another Function Block (by using one of the CLK_BUS signals), this is typically set to 0.
