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35
DM35425HR User’s Manual
6.2.12
FB_DMA
M
_WR_FIFO_CNT
(R
EAD
-O
NLY
)
B[9:0] This is the amount of space available in the write FIFO in bytes. Software can use this to determine when the FIFO is full. A
value of 0x3FC indicated that there are 1020 or more bytes of space available.
B15: WR_FULL-
‘1’ indicates that the write FIFO is full
6.2.13
FB_DMA
M
_ADDRESS
N
(R
EAD
/W
RITE
)
This is the 64-bit PCI address for DMA Channel m, buffer n. It must be double-word aligned (i.e. b[1:0] are reserved).
6.2.14
FB_DMA
M
_SIZE
N
(R
EAD
/W
RITE
)
This is the size in bytes of the buffer for DMA Channel m, buffer n. It must be an integer number of double-words (i.e. b[1:0] are reserved).
The actual size is FB_DMAm 4 Bytes. The maximum buffer size is 16MB.
6.2.15
FB_DMA
M
_CTRL
N
(R
EAD
/W
RITE
)
B0: Valid: S
et to ‘1’ to indicate that this contains valid information. The DMA engine will set the error bit and halt if it is ready to
use
this descriptor and it is not valid.
B1: Halt: Set
to ‘1’ to halt the DMA engine after this buffer is full.
B2: Loop: Set
to ‘1’ to start back at descriptor 0 after this buffer is full. This has a higher priority than the HALT bit.
B3: Interrupt: Set
to ‘1’ to generate an
interrupt after this buffer is full.
If the last buffer is reached, and the HALT and LOOP bits are both ‘0’, the DMA engine will loop.
If the last buffer is reached, and the HALT and LOOP bits are both ‘1’, the DMA engine will halt and the Current_Buffer w
ill be set to 0.
6.2.16
FB_DMA
M
_STAT
N
(R
EAD
/C
LEAR
)
B0: Used (R/C): DMA engine sets to ‘1’ to indicate that it has completely used this descriptor. The
user must clear this bit when it is
ready to be used again. The DMA engine will set the error bit and PAUSE if it is ready to use this descriptor and the
Used bit is set, unless the
bit is set. The bits are cleared by writing 0x00 to the byte.
