RTD Embedded Technologies, Inc.
|
www.rtd.com
43
DM35425HR User’s Manual
B[3:0]: Mode
o
0x04: Uninitialized. This is the power-on state. No converter initialization has taken place. Sampling is stopped, and all
counters are reset and the triggering state machine is reset. Transition to any of the other Modes will start converter
initialization (sampling will not start until initialization is complete).
o
0x00: Reset. Sampling is stopped. All counters are reset and the triggering state machine is reset.
o
0x01: Paused. Sampling is stopped, but the counters and triggering state machine maintain their state.
o
0x02: Go, Single-Shot. After converting the Post-Stop number of values, converting stops. The Mode must be set back
to RESET in order to convert more values.
o
0x03: Go, Re-arm. After converting the Post-Stop number of values, the triggering state machine is restarted. DAC data
is resumed from that last value sent.
B[7:4]: Status
o
0x08: Uninitialized
–
The status when in the “Uninitialized” mode and the converter requires initialization.
o
0x09: Initializing
o
0x00: Stopped
–
The status when in the “Reset” mode, or in the “Uninitialized” mode and the converter does not require
initialization.
o
0x01:
Reserved
o
0x02: Waiting for start trigger
o
0x03: Converting/Waiting for stop trigger
o
0x04: Output Post-Stop buffer
o
0x05: Wait to re-arm
o
0x07: Done capturing
6.4.5
CLK_SRC
(R
EAD
/W
RITE
)
Selects the source for CLK_DIV from the clock bus.
Refer to
on page 30 for list of valid values.
6.4.6
START_TRIG
(R
EAD
/W
RITE
)
Selects the start trigger from the clock bus. CLK_DIV will start counting after the start trigger.
Refer to
on page 30 for list of valid values.
6.4.7
STOP_TRIG
(R
EAD
/W
RITE
)
Selects the stop trigger from the clock bus.
Refer to
on page 30 for list of valid values.
6.4.8
CLK_DIV
(R
EAD
/W
RITE
)
Divider for the pacer clock. Pacer Clock Frequency = (Clk_Src_Frequency) / (1 + CLK_DIV). If synchronizing with the pacer clock from
another Function Block (by using one of the CLK_BUS signals), this is typically set to 0.
6.4.9
CLK_DIV_CNTR
(R
EAD
O
NLY
)
The current value of the Clock Divide Counter. This counter starts at a value of CLK_DIV, and counts down. When it reaches zero, a sample
is taken. This is useful when using a slow sample clock.
6.4.10
POST_STOP_CONVERSIONS
(R
EAD
/W
RITE
)
Number of conversions to send after the Stop Trigger.
6.4.11
CONVERSION_CNT
(R
EAD
O
NLY
)
Total number of conversions. This only increment in while in “Converting/Waiting for stop trigger” and “Output Post
-
Stop buffer” sta
te. It also
continues counting after a Re-Arm.
