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34
DM35425HR User’s Manual
The user may also write a value to this register and then poll the register to see when the value changes. This method can be used to
detect when the DMA engine services the channel without an Action change.
6.2.3
FB_DMA
M
_S
ETUP
(R
EAD
/W
RITE
)
B0: IntEna: Set to ‘1’ to enable the DMA engine to generate interrupts on completion of a buffer.
B1: ErrIntEna: Set to ‘1’ to enable the DMA engine to generate interrupts on error.
B2: Directi
on: Set to ‘1’ to transfer from the
board
to the PCI bus. Clear to ‘0’ to transfer from the PCI bus to the
board. Note that
although the DMA channel always supports both directions, the Function Block that the channel is associated with may
only support one direction.
B3: IgnoreUsed: Set to ‘1’ to prevent an error condition when accessing a buffer with the
bit set. Examples are continuous
output from a DAC, or very large Pre-trigger buffering using system memory.
6.2.4
FB_DMA
M
_S
TAT
_U
SED
(R
EAD
/W
RITE
)
This register is used to determine the source of a DMA interrupt. The bits are cleared by writing 0x00 to the byte. Stat_Used will be set
regardless of having ErrIntEna set to ‘1’.
B0: Used_Desc.
Set to ‘1’ by
the DMA engine if it attempting to use a descriptor with the
6.2.5
FB_DMA
M
_S
TAT
_I
NVALID
(R
EAD
/W
RITE
)
This register is used to determine the source of a DMA interrupt. The bits are cleared by writing 0x00 to the byte. Stat_Invalid will be set
regardless of having ErrIntEna set to ‘1’.
B0: Invalid_Desc
. Set to ‘1’ by the DMA engine if it attempting to use a descriptor with the
bit cleared.
6.2.6
FB_DMA
M
_S
TAT
_O
VERFLOW
(R
EAD
/W
RITE
)
This register is used to determine the source of a DMA interrupt. The bits are cleared by writing 0x00 to the byte. Stat_Overflow will be set
regardless of having ErrIntEna set to ‘1’. If an overflow occurs the DMA engine will PA
USE.
B0: Overflow (R/C). Set to ‘1’ by the DMA engine if an overflow occurred on the FIFO.
6.2.7
FB_DMA
M
_S
TAT
_U
NDERFLOW
(R
EAD
/W
RITE
)
This register is used to determine the source of a DMA interrupt. The bits are cleared by writing 0x00 to the byte. Stat_Underflow will be set
regardless of having ErrIntEna set to ‘1’. If an underflow occurs the DMA engine will PAUSE.
B0: Underflow (R/C). Set to ‘1’ by the DMA engine if an underflow occurred on the FIFO.
6.2.8
FB_DMA
M
_S
TAT
_C
OMPLETE
(R
EAD
/W
RITE
)
This register is used to determine the source of a DMA interrupt. The bits are cleared by writing 0x00 to the byte.
B0: Buffer_Complete (R/C). Set to ‘1’ by the DMA engine when a buffer is filled that has the
6.2.9
FB_DMA
M
_C
URRENT
_B
UFFER
(R
EAD
-O
NLY
)
This is the ID for the buffer that will be used for the next access. The user may use this to track the progress of the DMA activity.
6.2.10
FB_DMA
M
_COUNT
(R
EAD
-O
NLY
)
This is the offset in the DMA buffer for the next access. The user may use this to track the progress of the DMA activity. This value is given in
bytes.
6.2.11
FB_DMA
M
_RD_FIFO_CNT
(R
EAD
-O
NLY
)
B[9:0]
This is the amount of data available in the read FIFO in bytes. Software can use this to determine when the FIFO is
empty. A value of 0x3FC indicates that there are 1020 or more bytes of data available.
B15: RD_EMPTY-
‘1’ indicates that the read FIFO is empty
