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38
DM35425HR User’s Manual
NOTE: Pacer Clock Frequency should equal desired sampling rate of
enabled channels. The max sampling rate can be calculated by using
on page 27.
6.3.9
CLK_DIV_CNTR
(R
EAD
O
NLY
)
The current value of the Clock Divide Counter. This counter starts at a value of CLK_DIV, and counts down. When it reaches zero, a sample
is taken. This is useful when using a slow sample clock.
6.3.10
PRE_TRIGGER_CAPTURE
(R
EAD
/W
RITE
)
Number of samples to collect before the Start Trigger. The length is limited by the FIFO size
–
writing a value larger than the FIFO size will
have indeterminate results.
6.3.11
POST_STOP_CAPTURE
(R
EAD
/W
RITE
)
Number of samples to collect after the Stop Trigger.
6.3.12
SAMPLE_CNT
(R
EAD
O
NLY
)
Total number of samples collected. This only increment while in the
“Filling Pre
-
Trigger buffer”, “
Sampling/Waiting for stop trigger
”
and “Filling
Post-
Stop buffer”
state. It also continues counting after a Re-Arm.
6.3.13
INT_ENA
(M
ASKABLE
R
EAD
/W
RITE
)
Each bit corresponds to an interrupt source. A value of ‘1’ enables the source, and a value of ‘0’ disables it. See below f
or a description of the
sources.
6.3.14
INT_STAT
(R
EAD
/C
LEAR
)
Each bit corresponds to an interrupt sour
ce. Reading a value of ‘1’ indicates that an event has occurred. Reading a value of ‘0’ indicates that
the event has not occurred. Writing a ‘1’ will clear that bit.
B0: Sample
–
A sample has been taken.
B1: Channel Threshold
–
One of the channels has exceeded the High or Low threshold. Check the CH_THRESH_STAT registers.
B2: Pre-Start Buffer Filled
B3: Start Trigger
B4: Stop Trigger
B5:Post-Stop Buffer Filled
B6: Sampling has completed and the FIFO is empty (all data transferred to host)
B7: Pacer
–
The pacer clock has ticked.
6.3.15
CLK_BUS
N
NOTE: If a CLK_BUS is unassigned in all function blocks, it defaults to
System Clock/Immediate.
Select the source to drive onto Clock Bus N. That clock bus can then be used by a different function block as a clock source or trigger.
A function block can drive multiple different Clock Buses. However, a Clock Bus N should not be driven by more than one function block at the
same time or the clock signal will be undefined.
B[7:0]:
0x00:
Disables Clock Source
0x80:
Sample
–
A sample has been taken.
