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27
DM35425HR User’s Manual
the multiplexed input the sampling rate is limited to the number of channels enabled and summation of channel delay. Refer to the equation
below to calculate the max sample rate per channel.
Equation 1: Max Sampling Rate
𝑀𝑎𝑥 𝑆𝑎𝑚𝑝𝑙𝑒 𝑅𝑎𝑡𝑒 =
1.25𝑀𝐻𝑧
𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝐶ℎ𝑎𝑛𝑛𝑒𝑙𝑠 𝐸𝑛𝑎𝑏𝑙𝑒𝑑 + ∑ 𝐶ℎ𝑎𝑛𝑛𝑒𝑙 𝐷𝑒𝑙𝑎𝑦
5.4
Analog output
The DM35425 feature 4 independent 12-bit analog output channels with individually programmable output ranges of ±5V, and ±10V. Each
channel supports a maximum update rate 200 kHz and a maximum operating load of 5mA.
5.4.1
I
NITIALIZING THE
DAC
C
ONVERTER
The following is a list of the typical steps needed to initialize the DAC converter and begin sampling
1.
Set the DAC to the Uninitialized state (MODE = Uninitialized)
2.
Setup the DMA for the channel
3.
Set the input mode (CH_FRONT_END_CONFIG)
4.
Set the start and stop triggers (START_TRIG, STOP_TRIG)
5.
Set the clock source (CLK_SOURCE)
6.
Set the sample rate (CLK_DIV_CNTR)
7.
Set the Post Capture counter ( POST_STOP_CAPTURE)
8.
Set the DAC to the Reset state (MODE = Reset)
9.
Start the DMA
10.
Start the DAC (MODE = Go)
5.4.2
S
IMPLIFIED BLOCK DIAGRAM OF ANALOG OUTPUT
The following figure shows the front end circuit for the DM35425. It also shows the names of the FPGA registers in bold and the different ways
the front-end can be configured for different modes of operation. Refer to section
for more information about FPGA registers.
From FPGA
Din
CHn_Front_End_Config
[DABIP_UNI]
Vout
Offset
DAC: 12 Bit @
200 KHz
Refout
CHn_Front_End_Config
[GAIN]
AOUTn
CHn_Front_End_Config
[DAC_Enable]
