2-11
VC
C3
VC
C3
RA
1
RA
2
RA
3
RA
4
RA
5
RA
6
RA
7
RA
8
RA
9
NA
1
NA
2
NA
3
NA
4
NA
5
NA
6
NA
7
NA
8
NA
9
R
A
[0
..
25
]
N
A
[0..25]
NA
0
RA
0
N
A
[0..25]
R
A
[0
..
25
]
VC
C3
VC
C3
D
D
[0
..63]
/W
R
N
D
[0
..31]
DD
0
DD
1
DD
2
DD
3
DD
4
DD
5
DD
6
DD
7
DD
8
DD
9
DD
1
0
DD
1
1
DD
1
2
DD
1
3
DD
1
4
DD
1
5
VC
C3
VC
C3
DD
1
6
DD
1
7
DD
1
8
DD
1
9
DD
2
0
DD
2
1
DD
2
2
DD
2
3
DD
2
4
DD
2
5
DD
2
6
DD
2
7
DD
2
8
DD
2
9
DD
3
0
DD
3
1
VC
C3
D
D[
0..63]
N
D[
0..31]
ND
0
ND
1
ND
2
ND
3
ND
4
ND
5
ND
6
ND
7
ND
8
ND
9
ND
1
0
ND
1
1
ND
1
2
ND
1
3
ND
1
4
ND
1
5
ND
1
6
ND
1
7
ND
1
8
ND
1
9
ND
2
0
ND
2
1
ND
2
2
ND
2
3
ND
2
4
ND
2
5
ND
2
6
ND
2
7
ND
2
8
ND
2
9
ND
3
0
ND
3
1
/C
C
S
4
/C
C
S
4
/B
S
RB
_N
BS
RB
_C
KI
OB
CL
K1
2
0
_
3
LA
B/
BA
1
LB
0
2
LB
1
3
GN
D
4
LB
2
5
LB
3
6
VC
C
7
LB
4
8
LB
5
9
GN
D
10
LB
6
11
LB
7
12
HB
0
13
HB
1
14
GN
D
15
HB
2
16
HB
3
17
VC
C
18
HB
4
19
HB
5
20
GN
D
21
HB
6
22
HB
7
23
HA
B/
BA
24
/H
OE
25
HA
7
26
HA
6
27
GN
D
28
HA
5
29
HA
4
30
VC
C
31
HA
3
32
HA
2
33
GN
D
34
HA
1
35
HA
0
36
LA
7
37
LA
6
38
GN
D
39
LA
5
40
LA
4
41
VC
C
42
LA
3
43
LA
2
44
GN
D
45
LA
1
46
LA
0
47
/L
O
E
48
IC
30
SN
74L
V
CH
162
4
5A
DG
G
LA
B/
BA
1
LB
0
2
LB
1
3
GN
D
4
LB
2
5
LB
3
6
VC
C
7
LB
4
8
LB
5
9
GN
D
10
LB
6
11
LB
7
12
HB
0
13
HB
1
14
GN
D
15
HB
2
16
HB
3
17
VC
C
18
HB
4
19
HB
5
20
GN
D
21
HB
6
22
HB
7
23
HA
B/
BA
24
/H
OE
25
HA
7
26
HA
6
27
GN
D
28
HA
5
29
HA
4
30
VC
C
31
HA
3
32
HA
2
33
GN
D
34
HA
1
35
HA
0
36
LA
7
37
LA
6
38
GN
D
39
LA
5
40
LA
4
41
VC
C
42
LA
3
43
LA
2
44
GN
D
45
LA
1
46
LA
0
47
/L
O
E
48
IC
37
SN
74L
V
CH
162
4
5A
DG
G
LA
B/
BA
1
LB
0
2
LB
1
3
GN
D
4
LB
2
5
LB
3
6
VC
C
7
LB
4
8
LB
5
9
GN
D
10
LB
6
11
LB
7
12
HB
0
13
HB
1
14
GN
D
15
HB
2
16
HB
3
17
VC
C
18
HB
4
19
HB
5
20
GN
D
21
HB
6
22
HB
7
23
HA
B/
BA
24
/H
OE
25
HA
7
26
HA
6
27
GN
D
28
HA
5
29
HA
4
30
VC
C
31
HA
3
32
HA
2
33
GN
D
34
HA
1
35
HA
0
36
LA
7
37
LA
6
38
GN
D
39
LA
5
40
LA
4
41
VC
C
42
LA
3
43
LA
2
44
GN
D
45
LA
1
46
LA
0
47
/L
O
E
48
IC
31
SN
74L
V
CH
162
4
5A
DG
G
PC
2
CE
0.
1u
PC
78
CE
0.
1u
PC
19
CE
0.
1u
PC
35
CE
0
.1u
PC
10
CE
0.
1u
PC
26
CE
0.
1u
1
2
3
4
8
7
6
5
RA
62
EX
BV
8V
6
80
JV
1
2
3
4
8
7
6
5
RA
66
EX
BV
8V
6
80
JV
1
2
3
4
8
7
6
5
R
A
6
0
E
X
B
V
8
V
33
0JV
1
2
3
4
8
7
6
5
R
A
6
4
E
X
B
V
8
V
33
0JV
1
2
3
4
8
7
6
5
R
A
7
3
E
X
B
V
8
V
33
0JV
1
2
3
4
8
7
6
5
R
A
6
1
E
X
B
V
8
V
33
0JV
1
2
3
4
8
7
6
5
R
A
6
3
E
X
B
V
8
V
33
0JV
1
2
3
4
8
7
6
5
R
A
6
5
E
X
B
V
8
V
33
0JV
1
2
3
4
8
7
6
5
R
A
6
7
E
X
B
V
8
V
33
0JV
1
2
3
4
8
7
6
5
R
A
8
4
E
X
B
V
8
V
33
0JV
R
180
10
K
/C
C
S
4
/C
S
4
R9
3
6
8
R1
2
9
6
8
R1
3
2
3
3
R1
5
1
3
3
R1
6
2
3
3
Cm
d
_
St
o
M
VC
C3
RR
X
D
R
213
10
K
/C
S
6
R1
7
9
3
3
/C
C
S
6
V
C
C
C
1.2
Place two capacitors
at FPGA s
ide
o
riented to SDRAM
Place one on each side of
FPGA
as close as
p
o
ssib
le
Place one capacito
r
on
each other side of
FPGA
Place one capacitor close to each V
CCA pin
Place one on each side of
FPGA
as close as
p
o
ssib
le
Place
at FPGA sid
e op
posi
te to 1.2V reg
u
lator
V
C
C
C
1.2
V
CC
D
_PL
L
1
N4
VC
CI
NT
F7
GN
D
J1
1
Po
we
r Sup
p
ly
V
CC
A
_PL
L
2
F1
2
GN
DA
_
P
L
L
2
E1
2
VC
CI
NT
F1
1
VC
CI
NT
G6
VC
CI
NT
G7
VC
CI
NT
G8
VC
CI
NT
G9
VC
CI
O2
M3
VC
CI
O7
A1
6
VC
CI
O5
K1
4
VC
CI
O3
P4
VC
CI
O7
C1
0
VC
CI
O5
M1
4
VC
CI
O3
P7
VC
CI
O1
E3
VC
CI
O7
C1
3
VC
CI
O6
E1
4
VC
CI
O3
T1
VC
CI
O1
G3
VC
CI
O8
A1
VC
CI
O6
G1
4
VC
CI
O4
P1
0
GN
D
K8
GN
D
K6
GN
D
L9
GN
D
L1
0
GN
D
L1
1
GN
D
K1
2
GN
D
G1
1
GN
D
B2
GN
D
B1
5
GN
D
C5
GN
D
C1
2
GN
D
D7
GN
D
D1
0
GN
D
E4
GN
D
E1
3
GN
D
G4
GN
D
G1
3
GN
D
K4
GN
D
K1
3
GN
D
M4
GN
D
M1
3
GN
D
N7
GN
D
N1
0
GN
D
P5
GN
D
P1
2
VC
CI
O4
P1
3
VC
CI
O8
C4
VC
CI
O8
C7
V
CC
D
_PL
L
2
D1
3
GN
DA
_
P
L
L
1
M5
V
CC
A
_PL
L
1
L5
V
CC
A
_PL
L
3
F5
GN
DA
_
P
L
L
3
E5
V
CC
D
_PL
L
3
D4
V
CC
A
_PL
L
4
L1
2
GN
DA
_
P
L
L
4
M1
2
V
CC
D
_PL
L
4
N1
3
VC
CI
NT
G1
0
VC
CI
NT
H6
VC
CI
NT
H1
1
VC
CI
NT
J6
VC
CI
NT
K7
VC
CI
NT
K1
1
GN
D
H7
GN
D
H8
GN
D
H9
GN
D
H1
0
GN
D
J7
GN
D
J8
VC
CI
NT
L6
VC
CI
NT
K9
VC
CI
NT
K1
0
VC
CI
NT
M9
GN
D
J9
GN
D
J1
0
GN
D
F6
GN
D
F1
0
VC
CI
O4
T1
6
VC
CI
NT
M1
1
VC
CI
NT
J1
2
VC
CI
O2
K3
GN
D
R2
GN
D
R1
5
IO
3C
10
3C
16
VC
CI
NT
VC
CI
NT
VC
CI
NT
VC
CI
NT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GN
D
GN
D
GN
D
GN
D
3C
16
3C
10
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
3C
5/
3C
10
al
l pi
n funct
io
n
s a
re com
m
o
n b
etw
ee
n
3C
5/
3C
5/
3C
5,
3C
10, 3C
16
, 3
C
2
5 unl
ess
othe
rw
ise
not
ed
IC
44F
E
P
3C
10F256
N
Place on botto
m side under FPGA
Place
on
botto
m sid
e un
der FPGA
VC
C3
Place on botto
m side under FPGA
VC
C
3
V
C
C
C
1.2
VC
C
3
T8
1
A
K
D1
0
1S
S35
5
P
M
+
C1
4
22
0u_6
.3
V
1.2V
Ma
x50
0
m
A
VC
C2
.5
VC
C
3
T8
2
2.5V
Ma
x50
0
m
A
PC
87
CE
0.
1u
PC
88
CE
0.
1u
CB
50
CE
0.
1u
CB
55
CE
0.
1u
CB
58
CE
0.
1u
CB
59
CE
0.
1u
CB
56
CE
22
u
CB
30
CE
0.
1u
CB
35
CE
0.
1u
CB
42
CE
0.
1u
CB
46
CE
0.
1u
CB47
CE
0.
1u
CB
51
CE
0.
1u
CB52
CE
0.
1u
CB
60
CE
0.
1u
CB
28
CE
0.
1u
CB31
CE
0.
1u
CB
32
CE
0
.1u
CB
33
CE
0.
1u
CB34
CE
0.
1u
CB36
CE
0.
1u
CB
37
CE
0
.1u
CB
38
CE
0.
1u
CB39
CE
0.
1u
CB43
CE
0.
1u
CB
44
CE
0
.1u
CB
45
CE
0.
1u
CB
48
CE
0
.1u
CB
49
CE
0.
1u
CB
53
CE
0
.1u
CB
54
CE
0.
1u
CB61
CE
0.
1u
CB
62
CE
0
.1u
CB
63
CE
0.
1u
CB
29
CE
22
u
CB
40
CE
2
2
u
CB
41
CE
22
u
CB
57
CE
22
u
P
M
+
C1
5
2
20
u
_
6.
3V
A
K
D1
1
1S
S35
5
VC
C
1
N.
C.
2
OU
T
3
GN
D
FI
N
IC
52
B
D
1
2
KA
5FP
VC
C
1
N.
C.
2
OU
T
3
GN
D
FI
N
IC
53
B
D
2
5
KA
5FP
L4
M
M
Z
1
60
8S80
0A
L5
M
M
Z
1
60
8S80
0A
R3
8
1
10
K
R3
8
2
10
K
TP
2
8
TP
2
9
VC
C2
.5
VC
C2
.5
VC
C2
.5
VC
C2
.5
MAIN BOARD_Circuit Diagram 7/9
Summary of Contents for VS-300
Page 49: ...2 4 MAIN BOARD_Arrangement Diagram Soldering Side ...
Page 60: ...2 15 SERVO BOARD_Arrangement Diagram Soldering Side ...
Page 65: ...2 20 2 4 CARRIAGE BOARD CARRIAGE BOARD_Arrangement Diagram Component Side ...
Page 68: ...2 23 2 5 SUB BOARD SUB BOARD_Arrangement Diagram Component Side ...