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FEDL22620-01

ML22620

POP

Description

0

Without pop noise suppression

1

With pop noise suppression

In case that this bit is set to "1", when the AEN1 bit is set to "0" and the AEN0 bit is set to "1", the line amplifier output
rises from the DGND level to the SG level at the specified time (tPUPA2) and the line amplifier output enters the
power-up state. When the AEN0 bit is set to "0", the line amplifier output falls from the SG level to the DGND level
at the specified time (tPDA2) and the line amplifier output enters the power-down state.
In case that this bit is set to "0", when the AEN1 bit is set to "0" and the AEN0 bit is set to "1", the line amplifier output
rises from the DGND level to the SG level at the specified time (tPUPA3) and the line amplifier output enters the
power-up state. When the AEN0 bit is set to "0", the line amplifier output falls from the SG level to the DGND level
at the specified time (tPDA3) and the line amplifier output enters the power-down state.

The settings of the AEN1/AEN0/POP bits for power-down and power-up of the analog section when the speaker amplifier
output and line amplifier output are as follows. When using a Class D amplifier with speaker amplifier outputs, set it to the
power-up state (AEN1/AEN0= "01") or the power-down state (AEN1/AEN0= "00"). If DAMP = "1" is selected, do not set
AEN1= "1".

Mode

AEN1

AEN0

POP

Description

Speaker amplifier

output

0

0

*1

In the power-down state or
changeover to the power-down state.

0

1

*1

In the power-up state or
changeover to the power-up state

SPP pin

Line amplifier output

0

0

0

In the power-down state or
changeover to the power-down state without Pop Noise Suppression

1

0

0

In the power-up state or
changeover to the power-up state without Pop Noise Suppression

0

0

1

In the power-down state or
changeover to the power-down state with pop noise suppression

1

0

1

In the power-up state or
changeover to the power-up state with pop noise suppression

*1 Settings can be enabled for both 0 and 1.

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Summary of Contents for LAPIS Semiconductor ML22620

Page 1: ...ilure The functions necessary for sound output are integrated into a single chip so that sound functions can be realized simply by adding this LSI Memory capacity and maximum sound production time HQ...

Page 2: ...mplifier Class AB D 1 0W 8 SPVDD 5V Ta 25 O C Line amplifier output 10k driving Exclusive operation from speaker amplifier output External analog sound input at the time Class AB speaker amplifier cho...

Page 3: ...8 17 18 19 20 21 22 23 24 16 15 14 13 12 11 10 25 26 27 28 29 30 31 N C SPP SPM RESETB TEST0 STATUS1 STATUS2 CBUSYB SPGND SPV DD AIN SG V DDL DV DD DGND XT TOP VIEW TQFP32 9 XTB N C IOVDD EROFF ERSO E...

Page 4: ...ing non access and the L level during access Setting the EROFF pin to L enables output H 10 ERSCK O Serial flash memory interface serial clock output pin Setting the EROFF pin to L enables output L 11...

Page 5: ...connect it as close as possible Leave it open when not in use L 19 DVDD P Digital power supply pin Connect a bypass capacitor between this pin and the DGND pin 20 VDDL O 2 5V regulator output pin Used...

Page 6: ...tput data is H level H 31 STATUS2 O Status error output pin 2 Execute OUTSTAT command to select BUSYB 3 and NCR 3 in each channel or errors The initial value is BUSYB 3 of channel 0 and output data is...

Page 7: ...ction CMOS inputs with pull down Applicable pin TEST0 B Attribute Input Power IOVDD Function CMOS inputs with pull down Applicable pin EROFF C Attribute Input Power DVDD Function CMOS inputs with pull...

Page 8: ...TATUS2 CBUSYB SO G Attribute Input output Power IOVDD Function CMOS inputs Function CMOS outputs Applicable pin ERCSB ERSCK ERSO H Attribute Input output Power IOVDD Function CMOS inputs with pull dow...

Page 9: ...22620 01 ML22620 Classifi cation Circuit Overview J Attribute Analog Power SPVDD Function Sound output Applicable pins SPP SPM L Attribute Analog Power SPVDD Function Sound input Applicable pins AIN 9...

Page 10: ...C 4 layer board SPVDD 5V 1000 mW Output short circuit current IOS Applies to pins other than SPM SPP and VDDL pins 10 mA Applies to SPM and SPP pins 500 mA Applies to the VDDL pin 50 mA Storage temper...

Page 11: ...high impedance state SO 10 A IOOL1 VOL DGND in high impedance state 10 A Output leakage current 2 IOOH2 VOH IOVDD in high impedance state ERCSB ERSCK ERSO 10 A IOOL2 VOL DGND in high impedance state...

Page 12: ...300 Line amplifier output load resistance 1 RLA For SPGND 10 k Line amplifier Out put Voltage Range 1 VAO No output load SPVDD 6 SPVDD 5 6 V SG pin output voltage VSG 0 95x SPVDD 2 SPVDD 2 1 05x SPVD...

Page 13: ...external clock input DAMP L POP H AEN1 L H 72 74 76 ms At AMODE command input CBUSYB L level output time tPUPA3 4 096MHz external clock input DAMP L POP L AEN1 L H 32 34 36 ms At PDWN command input CB...

Page 14: ...K H level pulse width tSCKH 100 ns SCK L level pulse width tSCKL 100 ns CBUSYB output delay time from SCK tDBSY 90 ns When rewriting the flash memory using the clock synchronous serial interface SPVDD...

Page 15: ...ERSCK hold time from ERCSB rising edge tECSH 50 ns Data setup time from ERSCK rising edge tEDIS 10 ns Data hold time from ERSCK rising edge tEDIH 10 ns Data delay time from ERSCK falling edge tEDOD 5...

Page 16: ...ller PLL OSC4 096MHz or 4 000MHz PCM Synthesizer XT XTB Digital Mixing LPF DVDD DGND VDDL RESETB TEST0 RC4 096MHz Command Analyzer ERCSB ERSCK ERSI ERSO EROFF IOVDD CBUSYB STATUS1 STATUS2 MCU Interfac...

Page 17: ...oaded into the LSI on the falling edge of the SCK pin clock and the status signal is output from the SO pin on the rising edge of the SCK pin clock When the CSB pin is fixed to L level the SI pin data...

Page 18: ...ng and the AMODE can set the input gain to the amplifier By using the fade function with FADE command the volume can be adjusted stepwise when the volume is changed with CVOL 3 0 0 1 2 3 AIN SPP SPM C...

Page 19: ...ADPCM 1 5 4bit ADPCM algorithm is improved Adopting variable bit length enables high sound quality and high data compression Suitable for sound effects with sharp changes in waveforms or for pulsed w...

Page 20: ...pacity sampling frequency and playback algorithm The relationship is shown below However this is the playback time when the edit ROM function is not used When the number of phrases is 1024 the samplin...

Page 21: ...n the memory capacity only Silence insertion 20 to 1024 ms Using the edit ROM function enables an effective use of the memory capacity of sound ROM Below is an example of the ROM configuration in the...

Page 22: ...calculation of the synthesis If the clamp is known to be generated in advance adjust the volume of each channel by CVOL command SPVDD SPGND Channel 0 Channel 1 For channels 0 and 1 Mixing waveform If...

Page 23: ...22 05kHz 44 1kHz Group 3 12 0kHz 24 0kHz 48 0kHz Group 4 10 7kHz 21 3kHz Group 5 The figure below shows the operation image when a sampling frequency group with different sampling frequency group is...

Page 24: ...command can be used to send whether an error is detected or not to the STATUS1 pin or STATUS2 pin For SAFE RDERR ERRCL and OUTSTAT commands refer to the Command section Misoperation detection and fail...

Page 25: ...e two times input mode This LSI has a function to input various commands and data two times to prevent malfunction due to noise at the serial interface pin The setting of the two times input mode is m...

Page 26: ...it of the SAFE command When the TSDEN bit is set to 1 by the SAFE command LSI temperature error detection starts When the TSDEN bit is set to 0 LSI temperature error detection ends When the LSI become...

Page 27: ...power down with the AMODE command Then use ERRCL command to clear the error bit SPDERR To restart playback use the AMODE command to analog power up the speaker amplifier output mode and enter the PLA...

Page 28: ...the PUP command and before the PLAY command or START command starts playback this LSI may have error at the time of start In such cases initialize this LSI by moving the LSI to the power down mode by...

Page 29: ...the WDTCL command The count time of the WDT counter is 2s the initial value The counting time can be set to 125ms 500ms 2s or 4s In addition it is possible to shift to the command wait state after po...

Page 30: ...ction outputs are selected by OUTSTAT command WDTEN Set WDTEN 1 Count up WDT counter WDT overflow WDTERR 2 RSTERR 2 0h Command SAFE WDTCL Count up 0h Count up 0h STATUSn pin 1 n 1 or 2 Change to RSTER...

Page 31: ...nter is 2s the initial value The counting time can be set to 125ms 500ms 2s or 4s In addition the RST counter overflow can cause a transition to the command standby state after power up Set the counti...

Page 32: ...mand and the state configured by OUTSTAT command remain When Transition to command standby state after power up is not selected by the overflow of the RST counter 1 Misoperation detection and failure...

Page 33: ...ayback If the clock input from the crystal resonator or the ceramic resonator is stopped while the OSCEN bit is 0 the error bit OSCERR does not change to 1 but the clock backup function is activated a...

Page 34: ...ion Rewrite using serial flash memory interface without this LSI The serial flash memory can be rewritten using the ERCSB ERSCK ERSI and ERSO pins that is the serial flash memory interface When the ER...

Page 35: ...the SPVDD and DVDD shut down at the same time or the SPVDD shuts down and then the IOVDD and DVDD shut down at the same time The DVDD SPVDD and IOVDD can also shut down at the same time SPVDD IOVDD 9...

Page 36: ...t input timing The same timing is applied when a reset is input during command standby tRST RESETB XT XTB Oscillating Oscillation stopped GND GND Hi Z VDDL SPM SPP Status Power down During playback Re...

Page 37: ...FEDL22620 01 ML22620 Serial flash memory interface timing ERCSB ERSCK ERSI VIH VIL VIL VIH VIL VIH tECSH ERSO VOL VOH tEFLH tEFHL VIH VIL EROFF tECSS tEDIS tEDIH tESCKL tESCKH tEDOD tESCKF 37 115...

Page 38: ...VIL VIH tESCK tDIS tDIH tSCKH tSCKL tCSH CBUSYB tDBSY VOL VOH SO VIL VIH tDOZ tDOD tSCKS EROFF VIH VIL tEEROFF tEROFFH Clock Synchronous Serial Interface Timing SCK Initial Value L Level CSB SCK SI V...

Page 39: ...TB 1 Oscillating Oscillation stopped Awaiting command internal internal VOH VOL CBUSYB tPUP RC oscillation internal Oscillating Oscillation stopped VDDL Power up DGND CSB Status Command is being proce...

Page 40: ...ng command AMODE command 1 st byte AMODE command 2 nd byte LINE output GND SPM GND 1 2SPVDD SPP Hi Z 1 2SPVDD VOH VOL CBUSYB tCB1 tPUPA1 internal internal 1 2SPVDD internal Command is being processed...

Page 41: ...d Awaiting command Awaiting command AMODE command 1 st byte AMODE command 2 nd byte SPP VOH VOL CBUSYB GND 1 2SPVDD Command is being processed POP noise suppressed internal internal tCB1 tPUPA2 CSB St...

Page 42: ...aiting command Awaiting command AMODE command 1 st byte AMODE command 2 nd byte LINE output internal SPM SPP VOH VOL CBUSYB tCB1 tPDA1 GND 1 2SPVDD GND 1 2SPVDD Hi Z 1 2SPVDD Command is being processe...

Page 43: ...mand Awaiting command Awaiting command AMODE command 1 st byte AMODE command 2 nd byte SPP VOH VOL CBUSYB GND 1 2SPVDD Command is being processed POP noise suppressed internal internal tCB1 tPDA2 CSB...

Page 44: ...T command 1 st byte CBUSYB Command is being processed tCB1 FDIRECT command 2 nd byte Command is being processed tCB1 Flash memory access Normal mode Awaiting command VOH VOL CSB Status SCK SI Normal m...

Page 45: ...nd timing CSB Status Awaiting command SCK SI NCRn BUSYBn Command is being processed Awaiting command AVOL command 1 st byte VOH VOL CBUSYB internal internal Command is being processed Awaiting command...

Page 46: ...ing FADR command CSB Status Command is being processed SCK SI NCRn BUSYBn Awaiting command FADR command 1 st byte internal internal VOH VOL CBUSYB Awaiting command FADR command 2 nd byte Awaiting comm...

Page 47: ...gnal of the playback channel becomes H level The NCR signal goes to the L level during playback preparation and goes to the H level when playback preparation is completed and playback starts When the...

Page 48: ...hrases without silence sounds after the current phrase playback ends When the playback is not continuous input the PLAY command for the next phrases after confirming the playback is completed by RDSTA...

Page 49: ...becomes H level The NCR signal goes to the L level during playback preparation and goes to the H level when playback preparation is completed and playback starts When the NCR signal of the playback c...

Page 50: ...phrases without silence sounds after the current phrase playback ends When the playback is not continuous input the START command for the next phrases after confirming the playback is completed by RD...

Page 51: ...Approx 4ms At 11 025 22 05 44 1kHz Approx 2 9ms At 12 0 24 0 48 0kHz Approx 2 7ms CSB Status Awaiting command SCK SI NCRn BUSYBn SPM 1 2SPVDD SPP 1 2SPVDD Playing STOP command Command is being process...

Page 52: ...of the playback channels become H level The NCR signal becomes L level during playback preparation and becomes H level when playback preparation is completed and playback starts When the NCR signal o...

Page 53: ...tate waiting for the end of the playback of silence sound After ending the playback of silence sound and starting the playback of phrase 1 the NCR signal changes to H level and LSI is in state that ac...

Page 54: ...nnel becomes H level This enables the SLOOP command and repeats playback While the repeat playback mode is set the NCR signal is L level CSB Status 1st Repeat playing SCK SI NCRn BUSYBn SPM 1 2SPVDD S...

Page 55: ...cessed Awaiting command CBUSYB internal internal RDSTAT command 1st byte 2nd byte Under reading Awaiting command Hi Z Hi Z SO tCB1 VOH VOL CSB Status SCK SI NCRn BUSYBn Command is being processed Awai...

Page 56: ...iting command CBUSYB internal internal RDVER command 1st byte 2nd byte Under reading Awaiting command Hi Z Hi Z SO tCB1 VOH VOL CSB Status SCK SI NCR BUSYB Command is being processed Awaiting command...

Page 57: ...output status ch0 NCR output ch1 BUSYB output ERR internal STATUS2 tCB1 tCB1 VOH VOL CSB Status SCK SI NCR BUSYB Command is being processed Awaiting command CBUSYB internal internal SAFE command 1st b...

Page 58: ...the H level when playback preparation is completed and playback starts When the NCR signal of the playback channel becomes H level the PLAY command of the next phrase to be played can be accepted 1 Th...

Page 59: ...0 0 0 1 0 1 0 0 PDWN 0 0 1 0 0 0 0 0 FADR 0 0 1 1 F9 F8 C1 C0 F7 F6 F5 F4 F3 F2 F1 F0 PLAY 0 1 0 0 F9 F8 C1 C0 F7 F6 F5 F4 F3 F2 F1 F0 START 0 1 0 1 CH3 CH2 CH1 CH0 STOP 0 1 1 0 CH3 CH2 CH1 CH0 MUON...

Page 60: ...bit is used to set the mode for inputting command and data two times When this bit is set to 1 the subsequent command and data inputs are set to the two times input mode and the command is accepted on...

Page 61: ...using analog mixing from the AIN pin set DAMP 0 Class AB amplifier is used HPF Description 0 No high pass filter is used 1 Use a high pass filter with a cut off frequency of 200Hz FAD Description 0 Fa...

Page 62: ...the specified time tPDA3 and the line amplifier output enters the power down state The settings of the AEN1 AEN0 POP bits for power down and power up of the analog section when the speaker amplifier...

Page 63: ...g DAMP bit 1 AEN1 bit 0 AEN0 bit 0 1 Line amplifier power up timing DAMP bit 0 POP bit 1 AEN1 bit 0 1 AEN0 bit 0 Line amplifier power up timing DAMP bit 0 POP bit 0 AEN1 bit 0 1 AEN0 bit 0 Speaker amp...

Page 64: ...is set to 4 0dB Also the setting values of the AVOL command are retained when the STOP command is inputted but they are initialized when the power is down AV5 AV2 Description AV5 AV2 Description F 12...

Page 65: ...in 0 dB 32 32768 steps 0 1 1 Volume change in 0 dB 16 32768 steps 1 0 0 Volume change in 0 dB 8 32768 steps 1 0 1 Volume change in 0 dB 4 32768 steps 1 1 0 Volume change in 0 dB 2 32768 steps 1 1 1 V...

Page 66: ...creating sound ROM data the serial flash memory access mode is entered After that the flash memory can be accessed using the clock synchronous serial interface If the protection code set when creating...

Page 67: ...nd can be input regardless of the NCR signal status For information about the operation of the watchdog timer refer to the Misoperation detection and failure detection functions Watchdog timer overflo...

Page 68: ...ed after power up It is invalid when the BUSYB signals of any channels are L After inputting the PDWN command oscillation stops following the elapse of the command processing time tPD The states of th...

Page 69: ...the playback phrases of each channel are specified The phrases F9 F0 to be played back are specified when creating sound ROM data Set the phrase specified when creating This command can only set up to...

Page 70: ...ting sound ROM data Set the phrase specified when creating This command can only set up to 0 to 1023 phrases To specify 1024 phrases or more use PLAY2 command The channel settings are as follows C1 C0...

Page 71: ...this bit is set to 1 channel 0 is played back CH1 When this bit is set to 1 channel 1 is played back CH2 When this bit is set to 1 channel 2 is played back CH3 When this bit is set to 1 channel 3 is...

Page 72: ...omes H If the BUSYB signal does not become H enter the STOP command again Refer to the Playback stop flow in the command flowchart for more information The channel settings are as follows Channeled De...

Page 73: ...tmu 20ms tmu 27 M7 26 M6 25 M5 24 M4 23 M3 22 M2 21 M1 20 M0 1 4ms The channel settings are as follows Channeled Description CH0 Setting this bit to 1 inserts silence into channel 0 CH1 Setting this...

Page 74: ...lso if the phrase has been edited the edited phrase is played repeatedly The channel settings are as follows Channeled Description CH0 Setting this bit to 1 repeats playback on channel 0 CH1 Setting t...

Page 75: ...eled Description CH0 Setting this bit to 1 cancels repeat playback on channel 0 CH1 Setting this bit to 1 cancels repeat playback on channel 1 CH2 Setting this bit to 1 cancels repeat playback on chan...

Page 76: ...1 7 06dB 39 14 63dB 41 0 43dB 49 3 18dB 51 7 22dB 59 15 02dB 61 0 50dB 69 3 28dB 71 7 38dB 79 15 42dB 02 0 58dB 0A 3 38dB 12 7 55dB 1A 15 85dB 22 0 65dB 2A 3 49dB 32 7 72dB 3A 16 29dB 42 0 73dB 4A 3 5...

Page 77: ...dB 1F 44 37dB The channel settings are as follows Channeled Description CH0 Setting this bit to 1 set the volume of channel 0 CH1 Setting this bit to 1 set the volume of channel 1 CH2 Setting this bit...

Page 78: ...BUSYB0 NCR3 NCR2 NCR1 NCR0 The NCR signal outputs L during command processing and playback standby and outputs H in other states The BUSYB signal outputs L during command processing and playback soun...

Page 79: ...n in the second byte after command input set the SI pin to L The identification information read in the second byte is as follows 2nd byte D7 D6 D5 D4 D3 D2 D1 D0 Output data VER7 VER6 VER5 VER4 VER3...

Page 80: ...R This bit is set to 1 when the disconnection of the speaker connected to the SPP and SPM pins is detected TSDERR This bit is set to 1 when the LSI temperature becomes 130 C or higher SPDERR This bit...

Page 81: ...TUS2 pin STA1 STA0 Description 0 0 BUSYB 0 1 NCR 1 0 Misoperation detection and Failure Detection 1 1 Channeled Description CH0 Setting this bit to 1 selects channel 0 CH1 Setting this bit to 1 select...

Page 82: ...er the playback phrases of the channels are specified The phrases F11 F0 to be played back are specified when creating sound ROM data Set the phrase specified when creating The channel settings are as...

Page 83: ...evel The phrases F11 F0 to be played back are specified when creating sound ROM data Set the phrase specified when creating The channel settings are as follows C1 C0 Description 0 0 Channel 0 0 1 Chan...

Page 84: ...n SPDEN Set the detection of short circuit between the SPP pin and the SPM pin ROMEN Set error detection of flash memory WDTEN 1 Operate the watchdog timer and set overflow detection RSTEN 1 Operate t...

Page 85: ...ts that can be read by the RDERR command This command can be input regardless of the NCR signal status However if the error continues the error bit remains in the error status even if the ERRCL comman...

Page 86: ...FEDL22620 01 ML22620 Command Flowchart 1 byte command input flow Applies to PUP WDTCL PDWN START STOP SLOOP CLOOP and ERRCL commands Command input End Yes No Start No Yes CBUSYB H CBUSYB H 86 115...

Page 87: ...620 2 byte command input flow Applies to AMODE AVOL FADE FDIRECT FADR PLAY MUON CVOL OUTSTAT SAFE commands 1st byte command input 2nd byte command input End Yes No Yes No Start Yes No CBUSYB H CBUSYB...

Page 88: ...L22620 3 byte command input flow Applies to FADR2 PLAY2 command 1st byte command input 3rd byte command input End Yes No Yes No Start Yes No CBUSYB H CBUSYB H CBUSYB H 2nd byte command input Yes No CB...

Page 89: ...FEDL22620 01 ML22620 Read flow Applies to RDSTAT RDVER RDERR commands 1st byte command input Read status SI L Yes No CBUSYB H Start End 89 115...

Page 90: ...emory access migration MCU command interface serial flash memory access cancel Power on RESETB L RESETB H Yes No Wait 10us Power down state Power down state Serial flash memory access PUP command FDIR...

Page 91: ...nection and short circuit Analog power up state PUP command SAFE Command Within 10 ms Analog power up state Single channel playback Multi channel playback No Yes Playback end Playback start Playback s...

Page 92: ...ontinuous playback flow PLAY START MUON Command Within 10 ms Start continuous playback During playback PLAY START MUON Commands During playback STOP Command End RDSTAT Command No Yes No Read status SI...

Page 93: ...top flow Power down flow During loop playback Stop after phrase ends Forced stop Loop stop Loop stop CLOOP command STOP Command Power up state Power down state PDWN Command PLAY START Command Within 1...

Page 94: ...No Yes No 1st byte of PLAY command Yes No A A RDSTAT Command 1st byte of AMODE command No Yes No 2nd byte of AMODE Command Yes No PDWN Command Yes No Power down state No Yes No Yes CBUSYB H CBUSYB H...

Page 95: ...DE command 2nd byte of AMODE Command Yes No Command wait state Yes No Check STATUS1 2 pins H Confirm that the SPDERR bit is H ERRCL Command Yes No Clearing the ERR bit STATUS1 2 pins STOP Command Read...

Page 96: ...and input Yes No CBUSYB H CBUSYB H STATUS1 2 pins L First command input inputting again No Yes No CBUSYB H Yes First ERRCL command input Yes No STATUS1 2 pins L Second command input inputting again ST...

Page 97: ...in No Yes No CBUSYB H Yes First ERRCL command input Yes No STATUS1 2 pins L Second command input inputting again STATUS1 2 pins L First command input 2Byte Second command input 2Byte Yes No Yes No CBU...

Page 98: ...nput Yes No STATUS1 2 pins L Second command input inputting again STATUS1 2 pins L First command input 2Byte Second command input 2Byte Yes No Yes No CBUSYB H STATUS1 2 pins L Second ERRCL command inp...

Page 99: ...s No CBUSYB H CBUSYB H STATUS1 2 pins L First command input inputting again No Yes No CBUSYB H Yes First ERRCL command input Yes No STATUS1 2 pins L Second command input inputting again STATUS1 2 pins...

Page 100: ...is used to select the misoperation detection and failure detection outputs and the STATUS1 or STATUS2 pin is H if all the read data is L the data cannot be read normally Read the data again First comm...

Page 101: ...LSI is divided into the following three power supplies Digital power supply DV DD digital GND DGND Spea ker amplifier power supply SPVDD Speaker amplifier GND SPGND Power supply for flash memory inter...

Page 102: ...FEDL22620 01 ML22620 Application Circuit synchronous serial interfaces Please add necessary bypass capacitor to a power supply pin of the serial flash memory separately 102 115...

Page 103: ...d Ohm Power supply voltage V Temperatures ranges C 4M CSTCR4M00G55B R0 39 2 7 to 5 5 40 to 125 4 096M CSTCR4M09G55B R0 Built in RC4MHz characteristic RC4MHz characteristic is as follows This graph is...

Page 104: ...e is the package heat resistance value ja reference value This value changes the condition of the board size layer number and so on Board ja jc jb Condition JEDEC 4layers 1 W L t 76 2 114 5 1 6 mm 31...

Page 105: ...ackage This LSI adopts a heat sink type package to raise a radiation of heat characteristic Be sure to design the land pattern corresponding to the heat sink area of the LSI on a board and solder each...

Page 106: ...FEDL22620 01 ML22620 106 115...

Page 107: ...ases 1024 1BANK 4096 BANK 4 Edit ROM function Yes Silence insertion function 20ms to 1024ms 4ms step Repeat function Yes Low pass filter FIR type interpolation filter D A converter Voltage type 16 bit...

Page 108: ...FEDL22620 01 ML22620 It becomes command compatible with ML22420 by using the following command setting Command name Bit name Bit value PUP WCM 0 AMODE HPF 0 108 115...

Page 109: ...et the master clock frequency to FOSC 4 096 4 096MHz setting 4 000 4 000MHz setting Number of phrases used Select the number of phrases from the following 4096 3072 2048 1024 Sound ROM information Set...

Page 110: ...ternal clock input from this pin Delete the capacitor when a crystal or ceramic resonator is connected XT pin When using a resonator connect it as close as possible XT pin Leave it open when not in us...

Page 111: ...r power on Be sure to enter L at the RESETB pin when the DVDD is below the recommended operating voltage range Power off timing Shut down in the order of IOVDD SPVDD and DVDD or SPVDD IOVDD and DVDD S...

Page 112: ...and after confirming that the BUSYB signal becomes H If the BUSYB signal does not become H enter the STOP command again Be sure to specify one of the channels for the channel setting CH0 CH3 Do not in...

Page 113: ...e RSTEN bit is set to 1 Peripheral circuit Handling of SG Pin Handling of VDDL Pins Power wiring Bypass capacitor Coupling capacitor Confirm the recommended values and precautions in this chapter Pack...

Page 114: ...FEDL22620 01 ML22620 Revision history Document No Date Page Description Previous edition Current edition FEDL22620 01 2020 4 24 Formal 1st edition 114 115...

Page 115: ...ation tolerant 7 For use of our Products in applications requiring a high degree of reliability as exemplified below please contact and consult with a LAPIS Semiconductor representative transportation...

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