Rohm LAPIS Semiconductor ML22620, Manual

Page: 14 / 115

FEDL22620-01
ML22620
●
AC Characteristics (Clock Synchronous Serial Interface)
SPV
DD
≥DV
DD
=IOV
DD
=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +105°C, Load capacitance of output pin =15pF(max.)
Parameter Symbol Condition Min. Typ. Max. Unit
CSB input enable time from EROFF falling edge t
EEROFF
— 1000 — — ns
CSB hold time from EROFF rising edge t
EROFFH
— 1000 — — ns
SCK setup time from CSB falling edge t
SCKS
— 100 — — ns
SCK input enable time from CSB falling edge t
ESCK
— 100 — — ns
SCK hold time from CSB rising edge t
CSH
— 100 — — ns
Data floating time from CSB rising edge t
DOZ
RL=3KΩ
— — 100 ns
Data setup time from SCK t
DIS
— 50 — — ns
Data hold time from SCK t
DIH
— 50 — — ns
Data output delay time from SCK t
DOD
— — — 90 ns
SCK "H" level pulse width t
SCKH
— 100 — — ns
SCK "L" level pulse width t
SCKL
— 100 — — ns
CBUSYB output delay time from SCK t
DBSY
— — — 90 ns
<When rewriting the flash memory using the clock synchronous serial interface>
SPV
DD
≥DV
DD
=IOV
DD
=2.7 to 5.5V, DGND=SPGND=0V, Ta=-40 to +105°C, Load capacitance of output pin =15pF(max.)
Parameter Symbol Condition Min. Typ. Max. Unit
CSB input enable time from EROFF falling edge t
EEROFF
— 1000 — — ns
CSB hold time from EROFF rising edge t
EROFFH
— 1000 — — ns
SCK setup time from CSB falling edge t
SCKS
— 125 — — ns
SCK input enable time from CSB falling edge t
ESCK
— 125 — — ns
SCK hold time from CSB rising edge t
CSH
— 125 — — ns
Data floating time from CSB rising edge t
DOZ
RL=3KΩ
— — 125 ns
Data setup time from SCK t
DIS
— 50 — — ns
Data hold time from SCK t
DIH
— 50 — — ns
Data output delay time from SCK t
DOD
— — — 110 ns
SCK "H" level pulse width t
SCKH
— 125 — — ns
SCK "L" level pulse width t
SCKL
— 125 — — ns
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