RK3288 Hardware Design Guide
7 CPU&PMU
7.1 Schematic
RK3288 only need an external 24MHz crystal as shown in Fig 7-1. This crystal Y1100
requires frequency offset =<±20ppm, temperature offset =<±30ppm. The value of load
capacitors C1101, C1102 should be selected according to actual load capacitance of crystal.
8pF is the corresponding value of crystal selected by us, it is not the common value.
To decrease the circuit area of crystal, reduce its internal PLL clock jitter and avoid large
clock jitter caused by unreasonable signal return path design, RK3288 clock signal is
referenced to ground OSC_XVSS pin. This design has a certain demand for PCB layout, if user
don't need to reserve adjustment space, R1102 can be removed and connect OSC_SVSS to
GND network.
When RK3288 accesses to deep sleep mode, internal clock source will be switched to
external 32.768 KHz signal, system power consumption will be reduced by lower operating
frequency, and this signal will be obtained from PMIC or external RTC clock source.
Fig 7-1
Summary of Contents for RK32 Series
Page 1: ...RK3288 Hardware Design Guide RK3288 Hardware Design Guide Revision 1 2 Jun 18 2014...
Page 2: ...RK3288 Hardware Design Guide Revision History Date Revision Description 2014 12 15 1 2...
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