Rockchip RK32 Series, Hardware Design Manual

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RK3288 Hardware Design Guide
Fig 8-8
8.2 PCB Layout
（
DDR0 channel, DDR1 channel
）
Please follow below recommendations strictly to get the better performance:

Trace width and safe clearance

The trace width of all signals related to DDR should be set to 4mils.

Because the distance between CPU solder balls is 25.59 mils, the distance
between two adjacent traces in the same signal group is 12.795 mils, in other
words the distance between two adjacent traces is half of the distance of pads,
and routing in parallel from CPU must follow the 3W principle.

The distance between two adjacent traces in the different signal groups must
follow the 3W principle.

Both trace width and clearance for differential pair signals should be set to 4mils.

Trace length

The length tolerance of DQSnP and DQSnM should be less than 5mils. Less than
50mils length tolerance of DATAn and DQSnP/DQSnM in each GROUP (A, B, C, D)
is better. The length tolerance between GROUP data and GROUP data should be
limited within 120mils

The length tolerance between GROUP E and GROUP G should be limited within
100mils.

The length tolerance of CLK and CLKN in GROUP F should be less than 5mils.

The length tolerance between DQSnp/DQSnM in GROUP A~D and CLK, CLKn in
GROUP F should meet the tDQSS timing parameters, suggest to refer to below
design principles:

DDR1600
：
Length
（
CLK
）
-Length
（
DQSn
）＜
900mils

DDR1333
：
Length
（
CLK
）
-Length
（
DQSn
）＜
1200mils

DDR1066
：
Length
（
CLK
）
-Length
（
DQSn
）＜
1700mils

DDR800
：
Length
（
CLK
）
-Length
（
DQSn
）＜
2600mils

Recommendations for other else signals

DQS should be routed through DQ in the same GROUP.

DQS should be not routed close to CLK

Make sure that 3W principle must be applied to the center distance between
Snake-shaped lines. The amplitude of Snake-shaped line should be limited within
180mils, or it will reduce the quality of signals and make the transmission delay
below expectations