Renesas RZ/G1M, User Manual

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RZ/G1M 5. Pin Function Controller (PFC)
R01UH0626EJ0100 Rev.1.00 5-29
Sep 30,2016
5.3.16 Peripheral Function Select Register 6 (IPSR6)
Function: IPSR6 selects the functions of the multiplexed LSI pins.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— —
IP6
[29]
IP6
[28]
IP6
[27]
IP6
[26]
IP6
[25]
IP6
[24]
IP6
[23]
IP6
[22]
IP6
[21]
IP6
[20]
IP6
[19]
IP6
[18]
IP6
[17]
IP6
[16]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP6
[15]
IP6
[14]
IP6
[13]
IP6
[12]
IP6
[11]
IP6
[10]
IP6
[9]
IP6
[8]
IP6
[7]
IP6
[6]
IP6
[5]
IP6
[4]
IP6
[3]
IP6
[2]
IP6
[1]
IP6
[0]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Initial Value R/W Description
31 to 0 H'0000 0000 R/W The functions of the LSI pins are selected according to the table below.
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.
Bit Name
Function 1
(Set Value
= H'0)
Function 2
(Set Value
= H'1)
Function 3
(Set Value
= H'2)
Function 4
(Set Value
= H'3)
Function 5
(Set Value
= H'4)
Function 6
(Set Value
= H'5)
Function 7
(Set Value
= H'6)
Others
(Set Value =
H'7 to H'F)
IP6[2:0] AUDIO_CLKB — MSIOF1_SCK_B SCIF_CLK DVC_MUTE — — —
IP6[5:3] AUDIO_CLKC SCIFB0_SCK_C MSIOF1_SYNC_B RX2 SCIFA2_RXD — — —
IP6[7:6] AUDIO_CLKOUT MSIOF1_SS1_B TX2 SCIFA2_TXD — — — —
IP6[9:8] IRQ0 SCIFB1_RXD_D — — — — — —
IP6[11:10] IRQ1 SCIFB1_SCK_C — — — — — —
IP6[13:12] IRQ2 SCIFB1_TXD_D — — — — — —
IP6[15:14] IRQ3 I2C4_SCL_C MSIOF2_TXD_E — — — — —
IP6[18:16] IRQ4 HRX1_C/HRX1_E I2C4_SDA_C MSIOF2_RXD_E — — — —
IP6[20:19] IRQ5 HTX1_C/HTX1_E I2C1_SCL_E MSIOF2_SCK_E — — — —
IP6[23:21] IRQ6 HSCK1_C MSIOF1_SS2_B I2C1_SDA_E MSIOF2_SYNC_E — — —
IP6[26:24] IRQ7 HCTS1#_C MSIOF1_TXD_B — — — — —
IP6[29:27] IRQ8 HRTS1#_C MSIOF1_RXD_B — — — — —
Legend:
—
Setting prohibited