Renesas RZ/G1M, User Manual

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RZ/G1M 5. Pin Function Controller (PFC)
R01UH0626EJ0100 Rev.1.00 5-87
Sep 30,2016
5.4 Operation
5.4.1 Function Setting for Multiplexed Pins
Setting the LSI multiplexed pin setting mask register (PMMR) is necessary before setting each of the GPIO/peripheral
function select registers 0 to 7 (GPSR0 to GPSR7) and peripheral function select registers 0 to 16 (IPSR0 to IPSR16).
Specifically, the inverse of the value to be set in the select register must be written to the LSI multiplexed pin setting
mask register. Otherwise, the GPIO/peripheral function select registers 0 to 7 (GPSR0 to GPSR7) and peripheral function
select registers 0 to 16 (IPSR0 to IPSR16) cannot be set. IPSR0 to IPSR16, MOD_SEL and MOD_SEL2 to MOD_SEL4
registers shall be set before setting GPSR0 to GPSR7 registers in case that they need to be configured. MOD_SEL and
MOD_SEL2 to MOD_SEL4 registers can be set either earlier or later than setting IPSR0 to IPSR16 registers.
Note: When GPIO is selected by GPSRn for an LSI pin and one of the below pin functions is selected by IPSRn, make
sure to disable data reception of SCIFA3/4/5.
LSI Pin Pin Function
DU1_DB6 SCIFA3_RXD
ETH_REFCLK SCIFA3_RXD_B
GPS_MAG SCIFA4_RXD_C
GPS_SIGN SCIFA3_RXD_C
SD0_WP SCIFA5_RXD_B
SD3_WP SCIFA5_RXD_C
VI0_FIELD SCIFA4_RXD
VI0_VSYNC# SCIFA5_RXD
VI1_VSYNC# SCIFA4_RXD_B
(1) Procedure for changing pin function from GPIO to peripheral function
Set the LSI multiplexed pin setting mask register
Set the LSI multiplexed pin setting mask register
Set the GPIO/peripheral function select register
(GP) to peripheral function
Set the peripheral function select register (IP)
Clock (CP
φ
)
[Legend]
GP: GPIO/peripheral function select register bit
IP: Peripheral function select register bit
Pin
GP 0
GPIO
Peripheral function
Peripheral function select value
1
IP
Figure 5.1 Procedure for Changing Pin Function from GPIO to Peripheral Function