Renesas RZ/G1M, User Manual

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RZ/G1M 5. Pin Function Controller (PFC)
R01UH0626EJ0100 Rev.1.00 5-33
Sep 30,2016
5.3.20 Peripheral Function Select Register 10 (IPSR10)
Function: IPSR10 selects the functions of the multiplexed LSI pins.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IP10
[31]
IP10
[30]
IP10
[29]
IP10
[28]
IP10
[27]
IP10
[26]
IP10
[25]
IP10
[24]
IP10
[23]
IP10
[22]
IP10
[21]
IP10
[20]
IP10
[19]
IP10
[18]
IP10
[17]
IP10
[16]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP10
[15]
IP10
[14]
IP10
[13]
IP10
[12]
IP10
[11]
IP10
[10]
IP10
[9]
IP10
[8]
IP10
[7]
IP10
[6]
IP10
[5]
IP10
[4]
IP10
[3]
IP10
[2]
IP10
[1]
IP10
[0]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Initial Value R/W Description
31 to 0 H'0000 0000 R/W The functions of the LSI pins are selected according to the table below.
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.
Bit Name
Function 1
(Set Value
= H'0)
Function 2
(Set Value
= H'1)
Function 3
(Set Value
= H'2)
Function 4
(Set Value
= H'3)
Function 5
(Set Value
= H'4)
Function 6
(Set Value
= H'5)
Function 7
(Set Value
= H'6)
Others
(Set Value =
H'7 to H'F)
IP10[2:0] VI0_G1 IIC1_SDA — I2C4_SDA HRTS2# SCIFB2_RTS# ATADIR1# —
IP10[5:3] VI0_G2 VI2_HSYNC# — I2C3_SCL_B HSCK2 SCIFB2_SCK ATARD1# —
IP10[8:6] VI0_G3 VI2_VSYNC# — I2C3_SDA_B HRX2 SCIFB2_RXD ATACS01# —
IP10[11:9] VI0_G4 VI2_CLKENB — HTX2 SCIFB2_TXD SCIFB0_SCK_D — —
IP10[14:12] VI0_G5 VI2_FIELD — — CAN0_TX_E HTX1_D SCIFB0_TXD_D —
IP10[16:15] VI0_G6 VI2_CLK — — — — — —
IP10[18:17] VI0_G7 VI2_DATA0 — — — — — —
IP10[21:19] VI0_R0 VI2_DATA1 — TS_SDATA0_C ATACS11# — — —
IP10[24:22] VI0_R1 VI2_DATA2 — TS_SCK0_C ATAG1# — — —
IP10[26:25] VI0_R2 VI2_DATA3 — TS_SDEN0_C — — — —
IP10[28:27] VI0_R3 VI2_DATA4 — TS_SPSYNC0_C — — — —
IP10[31:29] VI0_R4 VI2_DATA5 — TX0_C I2C1_SCL_D — — —
Legend:
—
Setting prohibited