Renesas RZ/G1M, User Manual

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RZ/G1M 5. Pin Function Controller (PFC)
R01UH0626EJ0100 Rev.1.00 5-79
Sep 30,2016
5.3.44 IIC3 (DVFS) and TDBG IO Cell Control Register (IOCTRL7)
Function: IOCTRL controls the driving abilities of pins in use for the IIC and IIC3 (DVFS) interfaces. This register is
internal use and reserved; the value of this register should not be changed.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
— — — — — — — — — — — — — — — —
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — —
gpreg_m
sel03_p
— — — —
conta_II
C3(DVF
S)
contb_II
C3(DVF
S)
— — — — — —
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W Description
31 to 13 — All 0 R/W —
12 gpreg_msel03
_p
0 R/W Debug monitor function:
0: Use DU pins for debug monitor function.
1: Use SDHI pins for debug monitor function.
11 to 8 — All 0 R/W —
7 conta_IIC3(DV
FS)
0 R/W The setting value of these bits must be 00.
6 contb_IIC3(DV
FS)
0 R/W
5 to 0 — All 0 R/W —
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.