Renesas RZ/G1M, User Manual

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RZ/G1M 5. Pin Function Controller (PFC)
R01UH0626EJ0100 Rev.1.00 5-23
Sep 30,2016
5.3.10 Peripheral Function Select Register 0 (IPSR0)
Function: IPSR0 selects the functions of the multiplexed LSI pins.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
IP0
[30]
IP0
[29]
IP0
[28]
IP0
[27]
IP0
[26]
IP0
[25]
IP0
[24]
IP0
[23]
IP0
[22]
IP0
[21]
IP0
[20]
IP0
[19]
IP0
[18]
IP0
[17]
IP0
[16]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IP0
[15]
IP0
[14]
IP0
[13]
IP0
[12]
IP0
[11]
IP0
[10]
IP0
[9]
IP0
[8]
IP0
[7]
IP0
[6]
IP0
[5]
IP0
[4]
IP0
[3]
IP0
[2]
IP0
[1]
IP0
[0]
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit Initial Value R/W Description
31 to 0 H'0000 0000 R/W The functions of the LSI pins are selected according to the table below.
Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately
before setting this register.
Bit
Name
Function 1
(Set Value
= H'0)
Function 2
(Set Value
= H'1)
Function 3
(Set Value
= H'2)
Function 4
(Set Value
= H'3)
Function 5
(Set Value
= H'4)
Function 6
(Set Value
= H'5)
Others
(Set Value =
H'6 to H'F)
IP0[0] D0 — — — — — —
IP0[1] D1 — — — — — —
IP0[2] D2 — — — — — —
IP0[3] D3 — — — — — —
IP0[4] D4 — — — — — —
IP0[5] D5 — — — — — —
IP0[6] D6 — — — — — —
IP0[7] D7 — — — — — —
IP0[8] D8 — — — — — —
IP0[9] D9 — — — — — —
IP0[10] D10 — — — — — —
IP0[11] D11 — — — — — —
IP0[12] D12 — — — — — —
IP0[13] D13 — — — — — —
IP0[14] D14 — — — — — —
IP0[15] D15 — — — — — —
IP0[18:16] A0 ATAWR0#_C MSIOF0_SCK_B I2C0_SCL_C PWM2_B — —
IP0[20:19] A1 MSIOF0_SYNC_B — — — — —
IP0[22:21] A2 MSIOF0_SS1_B — — — — —
IP0[24:23] A3 MSIOF0_SS2_B — — — — —
IP0[26:25] A4 MSIOF0_TXD_B — — — — —
IP0[28:27] A5 MSIOF0_RXD_B — — — — —
IP0[30:29] A6 MSIOF1_SCK — — — — —
Legend:
—
Setting prohibited