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RZ/G1M

5. Pin Function Controller (PFC)

R01UH0626EJ0100 Rev.1.00

5-4

Sep 30,2016

Name Abbr.

R/W

Initial

Value

Address

Access
Size

Condition

DDR3 general port output
data register

DDR3GPOD R/W H'0000_0000

H'E606

0248 32

—



DDR3 general port input
data register

DDR3GPID R

H'XXXX_XXX0 H'E606

024C 32

—



Summary of Contents for RZ/G1M

Page 1: ...he product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp RZ G1M User s Manual Hardware Rev 1 00 Sep 2016 for Rich Graphics Applications RZ G Series Specifications of Individual RZ G Series Product ...

Page 2: ...e range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as t...

Page 3: ... supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provid...

Page 4: ...sions of these documents Document Type Description Document Title Document No User s manual for specifications of individual RZ G series product Overview of hardware pin assignments pin multiplexing and pin function controller RZ G1M User s Manual Hardware R01UH0626EJ0 100 Rev 1 00 This user s manual User s manual for specifications common to RZ G series products Hardware specifications address ma...

Page 5: ...register description includes a bit chart illustrating the arrangement of bits and a table of bits describing the meanings of the bit settings All trademarks and registered trademarks are the property of their respective owners ...

Page 6: ...ontroller PFC 5 1 5 1 Overview 5 1 5 1 1 Features 5 1 5 2 Register Configuration 5 2 5 3 Register Description 5 5 5 3 1 LSI Multiplexed Pin Setting Mask Register PMMR 5 6 5 3 2 GPIO Peripheral Function Select Register 0 GPSR0 5 7 5 3 3 GPIO Peripheral Function Select Register 1 GPSR1 5 9 5 3 4 GPIO Peripheral Function Select Register 2 GPSR2 5 11 5 3 5 GPIO Peripheral Function Select Register 3 GP...

Page 7: ...ull Up Control Register 0 PUPR0 5 56 5 3 32 LSI Pin Pull Up Control Register 1 PUPR1 5 58 5 3 33 LSI Pin Pull Up Control Register 2 PUPR2 5 60 5 3 34 LSI Pin Pull Up Control Register 3 PUPR3 5 62 5 3 35 LSI Pin Pull Up Control Register 4 PUPR4 5 64 5 3 36 LSI Pin Pull Up Control Register 5 PUPR5 5 66 5 3 37 LSI Pin Pull Up Control Register 6 PUPR6 5 68 5 3 38 LSI Pin Pull Up Control Register 7 PUP...

Page 8: ...g unit SD card host interface USB3 0 and USB2 0 interfaces PCI Express interface Serial ATA interface and CAN interface Also a full implementation of the extremely expandable and Internal AXI bus has been adopted for the RZ G1M This bus structure is optimized for maximum system performance leading to the realization of high performance and cost effective premium in vehicle infotainment systems Not...

Page 9: ... bit 10 ch CAN 2 ch IE BUS RWDT JTAG SecureWDT TPU Secure timer Secure up time clock 4 ch CMT0 2 ch CMT1 8 ch 3 ch 30 ch MLP USB2 0 Host Func USB2 0 Host USB3 0 Host SATA0 SATA1 PCI Express VSP1 VCP3 SSP1 Ethernet AVB Ethernet MAC DBSC3 DDR3 SDRAM FDP1 2D DMAC JPU RT DMAC 3 ch 2 ch 1 ch IPMMU INTC VIN 3 ch IMR LX2 1 ch Audio DSP DCU 3DGE R GP2D DU Audio DMAC 26 ch Audio DMAC peripheral peripheral ...

Page 10: ...tex A15 ARM Cortex A15 Dual MPCore 1 5 GHz L1 I D cache 32 32 Kbytes L2 cache 1 Mbyte NEONTM VFPv4 supported Security extension supported ARM debugger CoreSight CoreSight system compliant JTAG SWD I F supported CoreSight PTM A15 supported each CPU CoreSight ETR 16 Kbytes for program flow trace CoreSight ETR 4 Kbytes for system trace ...

Page 11: ...is different from H1 s 3DGE Please refer to 3DGE s specification Reset RST Includes one reset signal external output port for external modules Includes Boot Address Register etc Pin function controller PFC Setting multiplexed pin functions for LSI pins Function of the RZ G1M pin selectable by setting the registers in the PFC module Module selection Enable and disable the functions of RZ G1M LSI pi...

Page 12: ...t in cycle unit and the maximum value is 15 EX_WAIT pin can be used for wait state insertion Connectable bus widths 16 bits or 8 bits Burst ROM interface Wait states can be inserted through register settings Number of bursts can be set through register settings Connectable bus widths 16 bits or 8 bits Byte control SRAM interface available with areas 1 and 6 only Byte control SRAM interface Wait st...

Page 13: ...sfers 64M 67 108 864 transfers 64 M transfers supported only for LBSC DMAC00 Minimum number of transfers One Address mode Dual address mode Transfer modes Single transfer mode continuous transfer mode Transfer end interrupt Occurs at the end of the number of transfers specified in the register External bus controller for DDR3 SDRAM DBSC3 Two channels 32 bit bus mode DDR3L SDRAM can be connected di...

Page 14: ...dule Item Description AXI bus On chip main bus Bus protocol AXI3 with QoS control Frequency 260 MHz Bus width 256 bits 128 bits On chip CPU GPU main bus CorelinkTM CCI 400 Cache Coherent Interconnect r0p3 Bus protocol AMBA 4 ACETM and ACE LiteTM Frequency 520 MHz Bus width 128 bits ...

Page 15: ...ytes 32 bytes and 64 bytes Maximum number of transfer times 16 777 216 times Transfer request Selectable from on chip peripheral module request and auto request Bus mode Selectable from normal mode and slow mode Priority Selectable from fixed channel priority mode and round robin mode Interrupt request Supports interrupt request to CPU at the end of data transfer Repeat function Automatically rese...

Page 16: ...riority selectable Trust Zone supported 1 3 5 Local Memory Item Description INTRAM RAM0 of 72 Kbytes RAM1 of 4 Kbytes RAM2 of 256 Kbytes 1 3 6 Graphics Units Item Description 3D graphics engine 3DGE Imagination Technologies PowerVR SGX544MP2 Max Freq 520 MHz Most comprehensive IP core family and roadmap in the industry USSE2 delivers twice the peak floating point and instruction throughput of Seri...

Page 17: ...o settings Number of color palette planes with blending ratio 4 Dot clock Switchable between external input and internal clock Color management γ correction gain correction Applies correction of color skin color adjustment and color correction set in memory in terms of color phase brightness and chromaticity for a specified range of colors or for the full range of colors Interface LVDS output Four...

Page 18: ...t Y 12 bit CbCr format 18 bit RGB666 24 bit RGB888 Clipping function Up to 2048 2048 Horizontal scaling Uses a 9 tap multi phase filter Up to two times but only scaling down is possible for HD1080i or HD720P data Vertical scaling Scaling by linear interpolation Up to three times but only scaling down is possible for HD1080i or HD720P data Output format RGB 565 ARGB 1555 YCbCr422 RGB888 for channel...

Page 19: ...ersion and changes to the number of colors by dithering Color keying 2 Full HD video processing Up and down scaling with arbitrary scaling ratio Super resolution processing Blending of four picture layers and raster operations ROPs 3 Full HD picture quality color correction with 1D 3D look up table LUT Dynamic γ correction and gain correction Correction of color to adjust skin tones or colors in m...

Page 20: ...icture basis Encodes decodes data one picture frame or field at a time High picture quality Supports the H 264 high efficiency coding tools CABAC 8 8 frequency conversion and quantization matrix High efficiency motion vector detection by a combination of discrete search and trace search Highly efficient real time intra prediction by Prediction from Original Image POI Optimal mode selection by Rate...

Page 21: ...it CTU mixer MIX and digital mute and volume function DVC can be used on two fixed output channels Sampling rate conversion SRC Capable of asynchronous sampling rate conversion Supports resolutions up to 24 bits Two kinds of filter type for SRC Supports the quality suitable for audio sound THD N 132dB Realized the filter by passband 1dB 0 4575FS cutoff 18dB 0 5FS Supports the quality suitable for ...

Page 22: ... and long formats Supports TDM format six modules of ten modules can be used for this function Up to four independent stereo sound sources in a TDM format can be distributed to each course Up to four independent stereo sound sources can be combined output in TDM format Serial sound interface SSI Operating mode non compressed mode Not support compressed mode Supports versatile serial audio formats ...

Page 23: ...B3 0 Single channel SS HS FS Serial ATA Serial ATA Standard Rev 3 1 supported 3 0 Gbps Gen2 transfer rate supported Single channel PHY for USB3 0 and SATA channel 0 Single channel PHY for PCIEC and SATA channel 1 SD host interface SDHI Three channels Interface 0 Support SDR104 class transfer rate at max 97 5 Mbytes s 195 MHz and SDXC Does not support CPRM Interfaces 1 and 2 Support SDR50 class tra...

Page 24: ...oth IDs Selectable ID priority mode or mailbox number priority mode Sleep mode for reducing power consumption PCI Express Controller PCIEC PCI Express Base Specification Revision 2 0 Single channel PHY integrated Ethernet AVB Supports IEEE802 1BA IEEE802 1AS IEEE802 1Qav and IEEE1722 functions Supports transfer at 1000 Mbps and 100 Mbps Magic packet detection Supports Reception Filtering to separa...

Page 25: ...an be selected Source clock RCLK clock Compare match function provided Interrupt requests Compare match timer 1 CMT1 48 bit timer eight channels 16 bits 32 bits 48 bits can be selected Source clock RCLK system clock Compare match function provided Interrupt requests Timer unit TMU 4 sets of 3 channel 32 bit timer Auto reload type 32 bit down counter Internal prescaler Interrupt request Two channel...

Page 26: ...le clock generation from the system clock Serial communication interface with FIFO SCIFA Six channels Internal 64 byte transmit receive FIFOs High speed UART Internal prescaler Clock synchronous serial communications possible Support edge selection function Interrupt request DMAC request and DMA multi Byte transfer supported Asynchronous mode modem control is enabled Clock synchronous mode Serial ...

Page 27: ...ronous communication There is a single serial data communication format for clock synchronous serial communication Data length 8 bits Receive error detection Overrun errors Full duplex communication capability The SCIF has an independent transmitter and receiver that enable simultaneous transmission and reception The transmitter and receiver both have a 16 stage FIFO buffer structure enabling cont...

Page 28: ...m control functions HRTS and HCTS are stored The amount of data in the transmit receive FIFO registers and the number of receive errors in receive data in the receive FIFO register are available A receive data ready DR or a timeout error TO can be detected during reception PWM timer PWM Seven channels High level width 10 bits of PWM output can be set High level periods 10 bits of PWM can be set Pe...

Page 29: ...or CoreSight Process 28 nm Si CMOS Package FC BGA2727 831 1 4 Power Supply Voltages and Temperature Range Power supply voltage typ 1 8 V ETM SD MMC SATA PCI Express USB3 0 LVCMOS I F Xtal JTAG Trace and RST 1 03 V core 1 35V DDR3 I O SSTL mode DDR3L 3 3 V Others Temperature range Tc 40 C to 105 C Ta 40 C to 85 C ...

Page 30: ...RZ G1M 2 Area Map R01UH0626EJ0100 Rev 1 00 2 1 Sep 30 2016 2 Area Map See section 2 Area Map in the RZ G Series User s Manual Hardware ...

Page 31: ...WAIT0 DREQ0 PRESET OUT AVS1 AVS2 VCCQ VDD_ DVFS VDD_ DVFS VDD_ DVFS V EX_CS0 RD MD12 EX_CS3 MD9 EX_CS4 EX_CS5 MD8 A10 MD22 A7 MD27 VSS VSS VSS VSS W D15 D14 A5 A4 MD24 A3 MD13 A2 MD23 A1 MD28 VSS VDD VDD VSS VSS VDD_ DVFS VSS Y D13 D12 D11 D10 D9 D8 D7 VSS VSS VSS VDD VSS VDD_ DVFS VSS AA D6 D5 D4 D3 D2 D1 D0 VSS VDD VSS VDD VSS VDD_ DVFS VSS AB VI0_ CLKENB VI0_ HSYNC VI0_ VSYNC VI0_ DATA0 VI0_B0 ...

Page 32: ... HRTS1 HCTS1 VSS HSCK1 U VSS VSS VSS VSS HRX1 HTX1 SSI_ SDATA1 SSI_WS1 SSI_ SDATA0 SSI_ WS0129 SSI_ SCK0129 V VDD_ DVFS VSS VSS VDD VDD VCCQ SSI_ SDATA3 SSI_WS34 SSI_ SCK34 SSI_ SDATA2 SSI_WS2 SSI_SCK2 SSI_SCK1 W VDD_ DVFS VSS VDD VSS VSS VSS SSI_ SDATA7 SSI_ SDATA5 SSI_WS5 SSI_SCK5 SSI_ SDATA4 SSI_WS4 SSI_SCK4 Y VDD_ DVFS VSS VDD VSS VDD VCCQ SSI_ SDATA8 SSI_ WS78 SSI_ SCK78 VCCQ18 SSI_ SDATA6 SS...

Page 33: ...r 0 or 1 but its level must be fixed MPMD1 MPMD0 MP Mode Switching 0 0 Normal operation 0 1 Setting prohibited 1 0 Setting prohibited 1 1 Setting prohibited BSMODE JTAG Pin Operating Mode Switching 0 Normal operation 1 Operates in boundary scan mode When PRESET is at low level pin IO control is disabled MD0 Free Running Mode or Step Up Mode 0 Free running mode 1 Step up mode MD3 MD2 MD1 Boot Devic...

Page 34: ...ed Reserved Reserved 10 0 CoreSight debug port Normal Normal 1 00 Reserved Normal 01 Reserved Normal 10 Normal Reserved 11 Normal Reserved 11 0 Reserved Normal Normal 1 00 CoreSight debug port Normal 01 1 Reserved Reserved Reserved 1 00 Reserved Reserved Reserved 01 0 CoreSight debug port Normal Normal 1 00 Reserved Normal 01 Reserved Normal 1 Reserved Reserved Reserved 10 0 Reserved Normal Normal...

Page 35: ...nput the clock frequency of less than 24 MHz when the input division ratio is 1 2 3 VCO 3120 MHz MD19 DDR3 SDRAM Bus Clock 0 DDR3L 1600 mode 1 DDR3L 1333 mode MD28 MD27 MD22 DDR 64 Bits or 32 Bits Remarks 0 0 0 DDR 64 bits single channel Reserved setting prohibited 1 DDR 64 bits single channel Reserved setting prohibited 1 0 Reserved setting prohibited 1 DDR 64 bits single channel Reserved setting...

Page 36: ...s available for internal pull down function Off Pull up control function is available and default state is not pulled up Pull up control function is not available For details of pull up control function refer to PUPR0 through PUPR7 registers in section 5 Pin Function Controller PFC I Input I S Schmitt input IO Input and output IO OD Input and open drain output O Output P Power supply pin H L X Z i...

Page 37: ...0 1 35V O O L IO Z 9 DBSC3 channel 0 X 29 DBSC3 channel 0 L 49 DBSC3 channel 0 Z G18 M0CK1 1 35V A18 M0A11 1 35V A28 M0DM0 1 35V O O L O Z 10 DBSC3 channel 0 H 30 DBSC3 channel 0 L 50 DBSC3 channel 0 P B20 M0CS0 1 35V E16 M0A12 1 35V G22 VDDQ_M0DPLL0 O H O L P 11 DBSC3 channel 0 H 31 DBSC3 channel 0 L 51 DBSC3 channel 0 P A19 M0CS1 1 35V A17 M0A13 1 35V G23 VSSQ_M0DPLL0 O H O L P 12 DBSC3 channel ...

Page 38: ... F22 VDDQ_M0DPLL1 G27 M0DQS2 1 35V H29 M0DQ30 1 35V P IO Z IO Z 65 DBSC3 channel 0 P 76 DBSC3 channel 0 Z 87 DBSC3 channel 0 Z F23 VSSQ_M0DPLL1 D31 M0DM2 1 35V H31 M0DQ31 1 35V P O Z IO Z 66 DBSC3 channel 0 Z 77 DBSC3 channel 0 P 88 DBSC3 channel 0 Z E31 M0DQ16 1 35V K25 VDDQ_M0DPLL2 J27 M0DQS3 1 35V IO Z P IO Z 67 DBSC3 channel 0 Z 78 DBSC3 channel 0 P 89 DBSC3 channel 0 Z C30 M0DQ17 1 35V J25 VS...

Page 39: ... L5 M1CK1 1 35V O 102 DBSC3 channel 1 Reserved Reserved X K5 M1CK1 1 35V O 103 DBSC3 channel 1 GPIO GPIO H I GPIO F2 M1CS0 GP_DDR5 GP_DDR5 1 35V 1 8V GPIO O H I I 104 DBSC3 channel 1 GPIO GPIO H I GPIO G1 M1CS1 GP_DDR8 GP_DDR8 1 35V 1 8V GPIO O H I I 105 DBSC3 channel 1 GPIO GPIO L I GPIO F4 M1ODT0 GP_DDR6 GP_DDR6 1 35V 1 8V GPIO O L I I 106 DBSC3 channel 1 GPIO GPIO L I GPIO H4 M1ODT1 GP_DDR10 GP...

Page 40: ... L O Z O Z 121 DBSC3 channel 1 GPIO GPIO L I GPIO L3 M1A10 GP_DDR22 GP_DDR22 1 35V 1 8V GPIO O L I I 122 DBSC3 channel 1 GPIO GPIO L Z GPIO K1 M1A11 GP_DDR21 GP_DDR21 1 35V 1 8V GPIO O L O Z O Z 123 DBSC3 channel 1 GPIO GPIO L Z GPIO C2 M1A12 GP_DDR16 GP_DDR16 1 35V 1 8V GPIO O L O Z O Z 124 DBSC3 channel 1 GPIO GPIO L I GPIO L1 M1A13 GP_DDR27 GP_DDR27 1 35V 1 8V GPIO O L I I 125 DBSC3 channel 1 G...

Page 41: ...l 1 DBSC3 channel 0 64 bit Reserved Z D11 M1DQ7 M0DQ39 1 35V IO Z IO Z Z 142 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z E12 M1DQS0 M0DQS4 1 35V IO Z IO Z Z 143 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z E11 M1DQS0 M0DQS4 1 35V IO Z IO Z Z 144 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z A11 M1DM0 M0DM4 1 35V O Z O Z Z 145 DBSC3 channel 1 DBSC3 channel 0 64 bit DBSC3 channel 0 P ...

Page 42: ..._M0DPLL5 P P P 161 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z B6 M1DQ16 M0DQ48 1 35V IO Z IO Z Z 162 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z A7 M1DQ17 M0DQ49 1 35V IO Z IO Z Z 163 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z C8 M1DQ18 M0DQ50 1 35V IO Z IO Z Z 164 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z B8 M1DQ19 M0DQ51 1 35V IO Z IO Z Z 165 DBSC3 channel 1 DBSC3 cha...

Page 43: ...Z C5 M1DQ27 M0DQ59 1 35V IO Z IO Z Z 179 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z A5 M1DQ28 M0DQ60 1 35V IO Z IO Z Z 180 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z A3 M1DQ29 M0DQ61 1 35V IO Z IO Z Z 181 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z B5 M1DQ30 M0DQ62 1 35V IO Z IO Z Z 182 DBSC3 channel 1 DBSC3 channel 0 64 bit Reserved Z A2 M1DQ31 M0DQ63 1 35V IO Z IO Z Z 183 DBS...

Page 44: ...CPGPLL1 U6 AVS1 3 3V 4mA P O H L 1 Off 193 CPG P 205 AVS L H15 VDD_CPGPLL2 U7 AVS2 3 3V 4mA P O H L 1 Off 194 CPG P 206 POWER ISO P G15 VSS_CPGPLL2 AD19 VCCQ_ISO P P 195 CPG P 207 Debug I L25 VDD_CPGPLL0 AF19 TRST 1 8V P I On 196 CPG P 208 Debug I M25 VSS_CPGPLL0 AE18 TCK 1 8V P I On 197 CPG P 209 Debug I L26 VDD_CPGPLL3 AF18 TMS 1 8V P I I On 198 CPG P 210 Debug I M26 VSS_CPGPLL3 AH17 TDI 1 8V P ...

Page 45: ...S_SATA0 VSS_USB3 P P P P 220 SATA1 PCIEC P 239 SATA0 USB 3 0 P AF24 VDDA_SATA1 VDDA _PCIe AG26 VDDA_SATA0 VDDA_USB3 P P P P 221 SATA1 PCIEC P 240 SATA0 USB 3 0 P AG24 VDDA_SATA1 VDDA _PCIe AH27 VDDA_SATA0 VDDA_USB3 P P P P 222 SATA1 PCIEC P 241 SATA0 USB 3 0 P AF23 VDDD_SATA1 VDDD _PCIe AH25 VDDD_SATA0 VDDD_USB3 P P P P 223 SATA1 PCIEC P 242 SATA0 USB 3 0 P AG23 VDDD_SATA1 VDDD _PCIe AH26 VDDD_SAT...

Page 46: ...22 DU0_LVDS_CH0_N 1 8V P O Z 262 USB 2 0 channel 0 P 281 DU0 Z AB24 AVDD AL21 DU0_LVDS_CH1_P 1 8V P O Z 263 USB 2 0 channel 0 P 282 DU0 Z AC24 AVSS AL22 DU0_LVDS_CH1_N 1 8V P O Z 264 USB 2 0 channel 0 L 283 DU0 Z AF31 USB0_PWEN GP7_23 3 3V 4mA AJ20 DU0_LVDS_CH2_P 1 8V O L IO Off O Z 265 USB 2 0 channel 0 I 284 DU0 Z AF30 USB0_OVC VBUS GP7_24 3 3V 4mA AJ21 DU0_LVDS_CH2_N 1 8V I IO On O Z 266 USB 2 ...

Page 47: ...3 3 3V 8mA IO I IO I On 297 LBSC Reserved I GPIO AA3 D4 GP0_4 3 3V 8mA IO I IO I On 298 LBSC Reserved I GPIO AA2 D5 GP0_5 3 3V 8mA IO I IO I On 299 LBSC Reserved I GPIO AA1 D6 GP0_6 3 3V 8mA IO I IO I On 300 LBSC Reserved I GPIO Y7 D7 GP0_7 3 3V 8mA IO I IO I On 301 LBSC Reserved I GPIO Y6 D8 GP0_8 3 3V 8mA IO I IO I On 302 LBSC Reserved I GPIO Y5 D9 GP0_9 3 3V 8mA IO I IO I On 303 LBSC Reserved I...

Page 48: ...SIOF0 Reserved I GPIO W3 A5 MSIOF0_RXD_B GP0_21 3 3V 8mA O L I IO I On 315 LBSC MSIOF1 Reserved I GPIO T6 A6 MSIOF1_SCK GP0_22 3 3V 8mA O L IO IO I On 316 LBSC MSIOF1 Reserved I Mode Pin V7 A7 MSIOF1_SYNC GP0_23 3 3V 8mA MD27 O L IO IO I Off 317 LBSC MSIOF1 I2C0 Reserved I GPIO T5 A8 MSIOF1_SS1 I2C0_SCL GP0_24 3 3V 8mA O L O IO IO I On 318 LBSC MSIOF1 I2C0 Reserved I GPIO T4 A9 MSIOF1_SS2 I2C0_SDA...

Page 49: ..._TXD GP1_6 3 3V 8mA O L IO O O IO I On 332 LBSC QSPI Reserved SCIF0 SCIFA0 Reserved I GPIO P3 A23 IO2 RX0 SCIFA0_RXD GP1_7 3 3V 8mA O L IO I I IO I On 333 LBSC LBSC QSPI SCIF1 SCIFA1 Reserved I GPIO P2 A24 DREQ2 IO3 TX1 SCIFA1_TXD GP1_8 3 3V 8mA O L I IO O O IO I On 334 LBSC LBSC QSPI LBSC SCIF1 SCIFA1 I GPIO P1 A25 DACK2 SSL DREQ1_C RX1 SCIFA1_RXD GP1_9 3 3V 8mA O L O IO I I I IO I On 335 LBSC O ...

Page 50: ...C Reserved I Mode Pin N7 DACK0 DRACK0 GP1_25 3 3V 4mA MD7 O O IO I Off 352 Reserved Reserved HSCIF0 HSCIF2 SCIFB0 SCIFB2 LBSC HSCIF2 I GPIO T25 HSCK0_C HSCK2_C SCIFB0_SCK_B SCIFB2_SCK_B DREQ2_C HTX2_D GP5_31 3 3V 4mA IO IO O O I O IO I On 353 SSI HSCIF0 HSCIF2 SCIFB0 SCIFB2 I GPIO V31 SSI_SCK0129 HRX0_C HRX2_C SCIFB0_RXD_C SCIFB2_RXD_C GP2_0 3 3V 8mA IO I I I I IO I On 354 SSI HSCIF0 HSCIF2 SCIFB0...

Page 51: ...eserved I GPIO Y27 SSI_WS5 MSIOF1_SYNC_C TS_SCK0 MSIOF2_TXD_D VI1_R3_B GP2_16 3 3V 8mA IO IO I O I IO I On 370 SSI MSIOF1 TSIF0 Reserved MSIOF2 VIN1 Reserved I GPIO Y26 SSI_SDATA5 MSIOF1_TXD_C TS_SDEN0 MSIOF2_SS1_D VI1_R4_B GP2_17 3 3V 8mA IO O I O I IO I On 371 SSI MSIOF1 TSIF0 Reserved MSIOF2 VIN1 Reserved I GPIO AA31 SSI_SCK6 MSIOF1_RXD_C TS_SPSYNC0 MSIOF2_RXD_D VI1_R5_B GP2_18 3 3V 8mA IO I I ...

Page 52: ...385 INTC I S AL16 NMI 1 8V I S 386 INTC SCIFB1 Reserved I GPIO AE30 IRQ0 SCIFB1_RXD_D GP7_10 3 3V 4mA I I IO I On 387 INTC SCIFB1 Reserved I GPIO AE29 IRQ1 SCIFB1_SCK_C GP7_11 3 3V 4mA I O IO I On 388 INTC SCIFB1 Reserved I GPIO AD29 IRQ2 SCIFB1_TXD_D GP7_12 3 3V 4mA I O IO I On 389 INTC I2C4 MSIOF2 Reserved I GPIO AD28 IRQ3 I2C4_SCL_C MSIOF2_TXD_E GP7_13 3 3V 4mA I IO O IO I On 390 INTC HSCIF1 I2...

Page 53: ...8mA O I O O O IO I On 405 DU1 Reserved VIN1 SCIF1 SCIFA1 MSIOF2 I GPIO AK11 DU1_DG1 VI1_DATA3_B RX1_B SCIFA1_RXD_B MSIOF2_SS2_B GP3_9 3 3V 8mA O I I I O IO I On 406 DU1 Reserved VIN1 SCIF1 SCIFA1 SSI I GPIO AJ11 DU1_DG2 VI1_DATA4_B SCIF1_SCK_B SCIFA1_SCK SSI_SCK78_B GP3_10 3 3V 8mA O I IO O IO IO I On 407 DU1 Reserved VIN1 Reserved SSI I GPIO AH11 DU1_DG3 VI1_DATA5_B SSI_WS78_B GP3_11 3 3V 8mA O I...

Page 54: ...AN0 SCIF3 I2C2 PWM4 Reserved I GPIO AK10 DU1_DOTCLKOUT1 CAN0_TX TX3_B I2C2_SCL_B PWM4 GP3_26 3 3V 8mA O O O IO O IO I On 423 DU1 Reserved I Mode Pin AE8 DU1_EXHSYNC DU 1_HSYNC GP3_27 3 3V 8mA MD3 IO IO I Off 424 DU1 Reserved I Mode Pin AF8 DU1_EXVSYNC DU 1_VSYNC GP3_28 3 3V 8mA MD2 IO IO I Off 425 DU1 Reserved RCAN0 SCIF3 I2C2 Reserved I GPIO AG8 DU1_EXODDF DU1 _ODDF DISP CDE CAN0_RX RX3_B I2C2_SD...

Page 55: ...O IO O O IO I On 444 VIN0 VIN2 Reserved I2C3 HSCIF2 SCIFB2 LBSC I GPIO AD4 VI0_G3 VI2_VSYNC I2C3_SDA_B HRX2 SCIFB2_RXD ATACS01 GP4_16 3 3V 4mA I I IO I I O IO I On 445 VIN0 VIN2 Reserved HSCIF2 SCIFB2 SCIFB0 I GPIO AD5 VI0_G4 VI2_CLKENB HTX2 SCIFB2_TXD SCIFB0_SCK_D GP4_17 3 3V 4mA I I O O O IO I On 446 VIN0 VIN2 Reserved Reserved RCAN0 HSCIF1 SCIFB0 I GPIO AD6 VI0_G5 VI2_FIELD CAN0_TX_E HTX1_D SCI...

Page 56: ...AVB_RXD5 GP5_5 3 3V 4mA I I IO I On 463 VIN1 EtherAVB I GPIO AH1 VI1_DATA1 AVB_RXD6 GP5_6 3 3V 4mA I I IO I On 464 VIN1 EtherAVB I GPIO AJ1 VI1_DATA2 AVB_RXD7 GP5_7 3 3V 4mA I I IO I On 465 VIN1 EtherAVB I GPIO AJ2 VI1_DATA3 AVB_RX_ER GP5_8 3 3V 4mA I I IO I On 466 VIN1 EtherAVB I GPIO AK1 VI1_DATA4 AVB_MDIO GP5_9 3 3V 8mA I IO IO I On 467 VIN1 EtherAVB I GPIO AL2 VI1_DATA5 AVB_RX_DV GP5_10 3 3V 4...

Page 57: ...IFB2 Reserved MSIOF0 I GPIO AL8 AVB_TX_EN SCIFB2_RXD_D MSIOF0_SCK_C GP5_26 3 3V 8mA O I IO IO I On 484 Reserved EtherAVB SCIFB2 Reserved MSIOF0 I GPIO AH7 AVB_TX_ER SCIFB2_SCK_C MSIOF0_SS1_C GP5_27 3 3V 8mA O O O IO I On 485 Reserved EtherAVB Reserved MSIOF0 I GPIO AJ7 AVB_TX_CLK MSIOF0_SS2_C GP5_28 3 3V 8mA I O IO I On 486 Reserved EtherAVB Reserved MSIOF0 I GPIO AK7 AVB_COL MSIOF0_RXD_C GP5_29 3...

Page 58: ...I GPIO Z DBG 1 AL13 SD3_CLK MMC_CLK GP6_16 1 8 3 3V 2 16mA O O IO I Off 1 507 SDHI3 MMC I GPIO I DBG 1 AH13 SD3_CMD MMC_CMD GP6_17 1 8 3 3V 2 16mA IO IO IO I Off 1 508 SDHI3 MMC I GPIO I DBG 1 AG13 SD3_DATA0 MMC_D0 GP6_18 1 8 3 3V 2 16mA IO IO IO I Off 1 509 SDHI3 MMC I GPIO I DBG 1 AF13 SD3_DATA1 MMC_D1 GP6_19 1 8 3 3V 2 16mA IO IO IO I Off 1 510 SDHI3 MMC I GPIO I DBG 1 AE14 SD3_DATA2 MMC_D2 GP6...

Page 59: ...MSIOF0 MMC Reserved SCIF0 VIN1 I2C7 IIC0 VIN1 I GPIO T26 MSIOF0_SS2 MMC_D7 RX0_E VI1_VSYNC _C IIC0_SDA_C VI1_G5_B GP6_29 3 3V 8mA O IO I I IO I IO I On 521 Reserved Reserved RCAN1 I Mode Pin R26 CAN1_TX_D GP4_29 3 3V 4mA MDT1 O IO I Off 522 Reserved Reserved RCAN I Mode Pin R28 CAN_CLK_C GP4_30 3 3V 4mA MDT0 I IO I Off 523 Reserved Reserved RCAN1 I GPIO R27 CAN1_RX_D GP4_31 3 3V 4mA I IO I On 524 ...

Page 60: ...I I I IO I On 535 HSCIF0 SCIFB0 Reserved Reserved RCAN0 VIN1 I GPIO P30 HTX0 SCIFB0_TXD CAN0_TX_B VI1_DATA5_C GP7_4 3 3V 8mA O O O I IO I Off 536 HSCIF1 SCIFB1 VIN1 Reserved VIN1 I GPIO V25 HRX1 SCIFB1_RXD VI1_R0_B VI1_DATA6_C GP7_5 3 3V 8mA I I I I IO I Off 537 HSCIF1 SCIFB1 VIN1 Reserved VIN1 I GPIO V26 HTX1 SCIFB1_TXD VI1_R1_B VI1_DATA7_C GP7_6 3 3V 8mA O O I I IO I Off 538 HSCIF1 SCIFB1 Reserv...

Page 61: ...DD_MLBPPLL0 P 543 P 554 P U26 VDD_MLBPLL P25 VSS_MLBPPLL0 P P 544 P 555 P U25 VSS_MLBPLL N26 VDD_MLBPPLL1 P P 545 Reserved Z 556 P L31 1 8 3 3V P26 VSS_MLBPPLL1 P 546 Reserved Z 557 P K31 1 8 3 3V K28 VCCQ18_MLBP P 547 Reserved Z 558 P N31 1 8 3 3V N28 VCCQ18_MLBP P 548 Reserved Z 559 P M31 1 8 3 3V K29 VCCQ33_MLBP P 549 Reserved Z 560 P L29 1 8 3 3V N29 VCCQ33_MLBP P 550 Reserved Z 561 Thermal Se...

Page 62: ... pull down function Off Pull up control function is available and default state is not pulled up Pull up control function is not available For details of pull up control function refer to PUPR0 through PUPR7 registers in section 5 Pin Function Controller PFC I Input IO Input and output O Output H High level output L Low level output X Undefined value output Z High impedance P Power supply pin Note...

Page 63: ...16 M0ZQ IO IO M0ZQ IO 15 E21 M0WE O H M0WE H 16 D22 M0RAS O H M0RAS H 17 C22 M0CAS O H M0CAS H 18 E17 M0A0 O L M0A0 L 19 B22 M0A1 O L M0A1 L 20 A22 M0A2 O L M0A2 L 21 D17 M0A3 O L M0A3 L 22 A21 M0A4 O L M0A4 L 23 D16 M0A5 O L M0A5 L 24 B17 M0A6 O L M0A6 L 25 B21 M0A7 O L M0A7 L 26 A16 M0A8 O L M0A8 L 27 B18 M0A9 O L M0A9 L 28 C18 M0A10 O L M0A10 L 29 A18 M0A11 O L M0A11 L 30 E16 M0A12 O L M0A12 L ...

Page 64: ...3 IO Z M0DQ13 Z 59 B24 M0DQ14 IO Z M0DQ14 Z 60 A25 M0DQ15 IO Z M0DQ15 Z 61 E23 M0DQS1 IO Z M0DQS1 Z 62 E24 M0DQS1 IO Z M0DQS1 Z 63 C25 M0DM1 O Z M0DM1 Z 64 F22 VDDQ_M0DPLL1 P VDDQ_M0DPLL1 P 65 F23 VSSQ_M0DPLL1 P VSSQ_M0DPLL1 P 66 E31 M0DQ16 IO Z M0DQ16 Z 67 C30 M0DQ17 IO Z M0DQ17 Z 68 E29 M0DQ18 IO Z M0DQ18 Z 69 B31 M0DQ19 IO Z M0DQ19 Z 70 E30 M0DQ20 IO Z M0DQ20 Z 71 C31 M0DQ21 IO Z M0DQ21 Z 72 E2...

Page 65: ... H I 104 G1 M1CS1 IO H I M1CS1 GP_DDR8 1 H I 105 F4 M1ODT0 IO L I M1ODT0 GP_DDR6 1 L I 106 H4 M1ODT1 IO L I M1ODT1 GP_DDR10 1 L I 107 L8 M1ZQ IO IO M1ZQ IO 108 E3 M1WE O H Z M1WE GP_DDR9 1 H Z 109 D3 M1RAS O H Z M1RAS GP_DDR12 1 H Z 110 E4 M1CAS IO H I M1CAS GP_DDR4 1 H I 111 B1 M1A0 O L Z M1A0 GP_DDR7 1 L Z 112 H2 M1A1 IO L I M1A1 GP_DDR13 1 L I 113 E2 M1A2 O L Z M1A2 GP_DDR15 1 L Z 114 M3 M1A3 I...

Page 66: ...VREFDQ2 M0VREFDQ2 2 P 148 A13 M1DQ8 IO Z M1DQ8 M0DQ40 Reserved 2 Z Z Z 149 A14 M1DQ9 IO Z M1DQ9 M0DQ41 Reserved 2 Z Z Z 150 D14 M1DQ10 IO Z M1DQ10 M0DQ42 Reserved 2 Z Z Z 151 B14 M1DQ11 IO Z M1DQ11 M0DQ43 Reserved 2 Z Z Z 152 C14 M1DQ12 IO Z M1DQ12 M0DQ44 Reserved 2 Z Z Z 153 B15 M1DQ13 IO Z M1DQ13 M0DQ45 Reserved 2 Z Z Z 154 D15 M1DQ14 IO Z M1DQ14 M0DQ46 Reserved 2 Z Z Z 155 A15 M1DQ15 IO Z M1DQ1...

Page 67: ...d 2 Z Z Z 185 A4 M1DM3 O Z M1DM3 M0DM7 Reserved 2 Z Z Z 186 G10 VDDQ_M1DPLL3 P VDDQ_M1DPLL3 VDDQ_M0DPLL7 VDDQ_M0DPLL7 2 P 187 G9 VSSQ_M1DPLL3 P VSSQ_M1DPLL3 VSSQ_M0DPLL7 VSSQ_M0DPLL7 2 P 188 G6 VDDQ_M1BKUP P VDDQ_M1BKUP P 189 AL18 EXTAL I I EXTAL I 190 AL17 XTAL O O XTAL O 191 F16 VDD_CPGPLL1 P VDD_CPGPLL1 P 192 F15 VSS_CPGPLL1 P VSS_CPGPLL1 P 193 H15 VDD_CPGPLL2 P VDD_CPGPLL2 P 194 G15 VSS_CPGPLL...

Page 68: ...VSS_SATA1 P VSS_SATA1 VSS_PCIe 4 P 232 AL27 RIDP0_SATA I I RIDP0_SATA RIDP0_USB3 4 I I 233 AL28 RIDN0_SATA I I RIDN0_SATA RIDN0_USB3 4 I I 234 AL29 TODP0_SATA O O TODP0_SATA TODP0_USB3 4 O O 235 AL30 TODN0_SATA O O TODN0_SATA TODN0_USB3 4 O O 236 AJ28 CICREFP0_SATA I I CICREFP0_SATA CICREFP0_USB3 4 I I 237 AJ27 CICREFN0_SATA I I CICREFN0_SATA CICREFN0_USB3 4 I I 238 AF25 VSS_SATA0 P VSS_SATA0 VSS_...

Page 69: ...I USB1_OVC I On 277 AE20 DU0_LVDS_CLK_P O Z DU0_LVDS_CLK_P Z 278 AF20 DU0_LVDS_CLK_N O Z DU0_LVDS_CLK_N Z 279 AJ23 DU0_LVDS_CH0_P O Z DU0_LVDS_CH0_P Z 280 AJ22 DU0_LVDS_CH0_N O Z DU0_LVDS_CH0_N Z 281 AL21 DU0_LVDS_CH1_P O Z DU0_LVDS_CH1_P Z 282 AL22 DU0_LVDS_CH1_N O Z DU0_LVDS_CH1_N Z 283 AJ20 DU0_LVDS_CH2_P O Z DU0_LVDS_CH2_P Z 284 AJ21 DU0_LVDS_CH2_N O Z DU0_LVDS_CH2_N Z 285 AG22 DU0_LVDS_CH3_P ...

Page 70: ...6 V7 A7 IO I MD27 A7 GP0_23 5 L I Off 317 T5 A8 IO I A8 GP0_24 5 L I On 318 T4 A9 IO I A9 GP0_25 5 L I On 319 V6 A10 IO I MD22 A10 GP0_26 5 L I Off 320 T3 A11 IO I A11 GP0_27 5 L I On 321 T2 A12 IO I A12 GP0_28 5 L I On 322 R7 A13 IO I MD21 A13 GP0_29 5 L I Off 323 R6 A14 IO I MD19 A14 GP0_30 5 L I Off 324 R5 A15 IO I MD20 A15 GP0_31 5 L I Off 325 R4 A16 IO I A16 GP1_0 5 L I On 326 R3 A17 IO I A17...

Page 71: ...SDATA1 IO I GP2_5 I On 359 W30 SSI_SCK2 IO I GP2_6 I On 360 W29 SSI_WS2 IO I GP2_7 I On 361 W28 SSI_SDATA2 IO I GP2_8 I On 362 W27 SSI_SCK34 IO I GP2_9 I On 363 W26 SSI_WS34 IO I GP2_10 I On 364 W25 SSI_SDATA3 IO I GP2_11 I On 365 Y31 SSI_SCK4 IO I GP2_12 I Off 366 Y30 SSI_WS4 IO I GP2_13 I Off 367 Y29 SSI_SDATA4 IO I GP2_14 I On 368 Y28 SSI_SCK5 IO I GP2_15 I On 369 Y27 SSI_WS5 IO I GP2_16 I On 3...

Page 72: ... On 402 AE12 DU1_DR6 IO I GP3_6 I On 403 AE11 DU1_DR7 IO I GP3_7 I On 404 AL11 DU1_DG0 IO I GP3_8 I On 405 AK11 DU1_DG1 IO I GP3_9 I On 406 AJ11 DU1_DG2 IO I GP3_10 I On 407 AH11 DU1_DG3 IO I GP3_11 I On 408 AG11 DU1_DG4 IO I GP3_12 I On 409 AF11 DU1_DG5 IO I GP3_13 I On 410 AF10 DU1_DG6 IO I GP3_14 I On 411 AE10 DU1_DG7 IO I GP3_15 I On 412 AJ9 DU1_DB0 IO I GP3_16 I On 413 AH9 DU1_DB1 IO I GP3_17...

Page 73: ..._12 I On 441 AD1 VI0_G0 IO I GP4_13 I On 442 AD2 VI0_G1 IO I GP4_14 I On 443 AD3 VI0_G2 IO I GP4_15 I On 444 AD4 VI0_G3 IO I GP4_16 I On 445 AD5 VI0_G4 IO I GP4_17 I On 446 AD6 VI0_G5 IO I GP4_18 I On 447 AE6 VI0_G6 IO I GP4_19 I On 448 AD7 VI0_G7 IO I GP4_20 I On 449 AE1 VI0_R0 IO I GP4_21 I On 450 AE3 VI0_R1 IO I GP4_22 I On 451 AE4 VI0_R2 IO I GP4_23 I On 452 AE5 VI0_R3 IO I GP4_24 I On 453 AF3...

Page 74: ...L7 STP_OPWM_0 IO I GP5_30 I On 488 AL15 SD0_CLK IO I GP6_0 I Off 489 AH16 SD0_CMD IO I GP6_1 I Off 490 AG16 SD0_DATA0 IO I GP6_2 I Off 491 AF16 SD0_DATA1 IO I GP6_3 I Off 492 AE16 SD0_DATA2 IO I GP6_4 I Off 493 AH15 SD0_DATA3 IO I GP6_5 I Off 494 AJ15 SD0_CD IO I GP6_6 I Off 495 AJ16 SD0_WP IO I GP6_7 I Off 496 AD16 VCCQ_SD0 VCCQ_SD0 497 AL14 SD2_CLK IO I Z 7 GP6_8 TDO2 8 I Z 7 Off 9 498 AH14 SD2_...

Page 75: ...7_21 I On 526 R29 GPS_MAG IO I GP7_22 I On 527 AJ18 I2C5_SCL IO Z I2C5_SCL Z 528 AH18 I2C5_SDA IO Z I2C5_SDA Z 529 AJ19 IIC3_SCL IO Z IIC3_SCL Z 530 AH19 IIC3_SDA IO Z IIC3_SDA Z 531 P28 HCTS0 IO I GP7_0 I On 532 R25 HRTS0 IO I GP7_1 I On 533 P31 HSCK0 IO I GP7_2 I On 534 P29 HRX0 IO I GP7_3 I On 535 P30 HTX0 IO I GP7_4 I Off 536 V25 HRX1 IO I GP7_5 I Off 537 V26 HTX1 IO I GP7_6 I Off 538 U31 HSCK...

Page 76: ...SC channel 0 64 bit M0DQ 63 32 enable operation MD 28 27 22 110 Reserved except for power supply pins 3 No 204 and 205 AVS Default State The output is high or low depending on product 4 No 213 to 254 Default Pin Function MD 24 23 00 SATA1 and SATA0 MD 24 23 01 SATA1 and USB3 0 MD 24 23 10 PCIe and SATA0 MD 24 23 11 PCIe and USB3 0 5 No 293 to 334 336 337 344 345 and 347 to 349 Default Pin Function...

Page 77: ...ea 0 or QSPI Default pull up Internal pull up control function is available or not from a power on reset and its pull up state On Pull up control function is available and default state is pulled up No 212 ACK pin is available internal pull down function Off Pull up control function is available and default state is not pulled up Pull up control function is not available For details of pull up con...

Page 78: ...19 M0CS1 H Open 12 D20 M0ODT0 L Open 13 E18 M0ODT1 L Open 14 H16 M0ZQ IO Must be used 15 E21 M0WE H Open 16 D22 M0RAS H Open 17 C22 M0CAS H Open 18 E17 M0A0 L Open 19 B22 M0A1 L Open 20 A22 M0A2 L Open 21 D17 M0A3 L Open 22 A21 M0A4 L Open 23 D16 M0A5 L Open 24 B17 M0A6 L Open 25 B21 M0A7 L Open 26 A16 M0A8 L Open 27 B18 M0A9 L Open 28 C18 M0A10 L Open 29 A18 M0A11 L Open 30 E16 M0A12 L Open 31 A1...

Page 79: ...0DQ11 Z Open 57 B26 M0DQ12 Z Open 58 D26 M0DQ13 Z Open 59 B24 M0DQ14 Z Open 60 A25 M0DQ15 Z Open 61 E23 M0DQS1 Z Open 62 E24 M0DQS1 Z Open 63 C25 M0DM1 Z Open 64 F22 VDDQ_M0DPLL1 P Must be used 65 F23 VSSQ_M0DPLL1 P Must be used 66 E31 M0DQ16 Z Open 67 C30 M0DQ17 Z Open 68 E29 M0DQ18 Z Open 69 B31 M0DQ19 Z Open 70 E30 M0DQ20 Z Open 71 C31 M0DQ21 Z Open 72 E28 M0DQ22 Z Open 73 D29 M0DQ23 Z Open 74 ...

Page 80: ... or pulled down to VSS 98 G5 M1RESET O Open 99 J5 M1CK0 O Open 100 H5 M1CK0 O Open 101 L5 M1CK1 O Open 102 K5 M1CK1 O Open 103 F2 M1CS0 H I Open 104 G1 M1CS1 H I Open 105 F4 M1ODT0 L I Open 106 H4 M1ODT1 L I Open 107 L8 M1ZQ IO Must be used 108 E3 M1WE H Z Open 109 D3 M1RAS H Z Open 110 E4 M1CAS H I Open 111 B1 M1A0 L Z Open 112 H2 M1A1 L I Open 113 E2 M1A2 L Z Open 114 M3 M1A3 L I Open 115 E1 M1A...

Page 81: ...2 M1DQS0 Z Open 143 E11 M1DQS0 Z Open 144 A11 M1DM0 Z Open 145 G13 VDDQ_M1DPLL0 P Must be used 146 G12 VSSQ_M1DPLL0 P Must be used 147 G14 M1VREFDQ0 P Must be used 148 A13 M1DQ8 Z Open 149 A14 M1DQ9 Z Open 150 D14 M1DQ10 Z Open 151 B14 M1DQ11 Z Open 152 C14 M1DQ12 Z Open 153 B15 M1DQ13 Z Open 154 D15 M1DQ14 Z Open 155 A15 M1DQ15 Z Open 156 E14 M1DQS1 Z Open 157 E13 M1DQS1 Z Open 158 C13 M1DM1 Z Op...

Page 82: ...Must be used 189 AL18 EXTAL I Must be used 190 AL17 XTAL O Open 191 F16 VDD_CPGPLL1 P Must be used 192 F15 VSS_CPGPLL1 P Must be used 193 H15 VDD_CPGPLL2 P Must be used 194 G15 VSS_CPGPLL2 P Must be used 195 L25 VDD_CPGPLL0 P Must be used 196 M25 VSS_CPGPLL0 P Must be used 197 L26 VDD_CPGPLL3 P Must be used 198 M26 VSS_CPGPLL3 P Must be used 199 AE19 PRESET I Must be used 200 U5 PRESETOUT L to H O...

Page 83: ...used 230 AK26 VSS_SATA1 P Must be used 231 AK23 VSS_SATA1 P Must be used 232 AL27 RIDP0_SATA I Open 233 AL28 RIDN0_SATA I Open 234 AL29 TODP0_SATA O Open 235 AL30 TODN0_SATA O Open 236 AJ28 CICREFP0_SATA I Fixed to VSS_SATA0 237 AJ27 CICREFN0_SATA I Fixed to VSS_SATA0 238 AF25 VSS_SATA0 P Must be used 239 AG26 VDDA_SATA0 P Must be used 240 AH27 VDDA_SATA0 P Must be used 241 AH25 VDDD_SATA0 P Must ...

Page 84: ...AVSS P Must be used 274 AG28 AVSS P Must be used 275 AE28 USB1_PWEN L Off Open 276 AD27 USB1_OVC I On Open 277 AE20 DU0_LVDS_CLK_P Z Open 278 AF20 DU0_LVDS_CLK_N Z Open 279 AJ23 DU0_LVDS_CH0_P Z Open 280 AJ22 DU0_LVDS_CH0_N Z Open 281 AL21 DU0_LVDS_CH1_P Z Open 282 AL22 DU0_LVDS_CH1_N Z Open 283 AJ20 DU0_LVDS_CH2_P Z Open 284 AJ21 DU0_LVDS_CH2_N Z Open 285 AG22 DU0_LVDS_CH3_P Z Open 286 AG21 DU0_L...

Page 85: ...to VCCQ or pulled down to VSS 317 T5 A8 L I Area 0 1 On Open 318 T4 A9 L I Area 0 1 On Open 319 V6 A10 L I MD22 Area 0 1 Off Pulled up to VCCQ or pulled down to VSS 320 T3 A11 L I Area 0 1 On Open 321 T2 A12 L I Area 0 1 On Open 322 R7 A13 L I MD21 Area 0 1 Off Pulled up to VCCQ or pulled down to VSS 323 R6 A14 L I MD19 Area 0 1 Off Pulled up to VCCQ or pulled down to VSS 324 R5 A15 L I MD20 Area ...

Page 86: ...K2 I On Open 360 W29 SSI_WS2 I On Open 361 W28 SSI_SDATA2 I On Open 362 W27 SSI_SCK34 I On Open 363 W26 SSI_WS34 I On Open 364 W25 SSI_SDATA3 I On Open 365 Y31 SSI_SCK4 I Off Pulled up to VCCQ or pulled down to VSS 366 Y30 SSI_WS4 I Off Pulled up to VCCQ or pulled down to VSS 367 Y29 SSI_SDATA4 I On Open 368 Y28 SSI_SCK5 I On Open 369 Y27 SSI_WS5 I On Open 370 Y26 SSI_SDATA5 I On Open 371 AA31 SSI...

Page 87: ...1 DU1_DG0 I On Open 405 AK11 DU1_DG1 I On Open 406 AJ11 DU1_DG2 I On Open 407 AH11 DU1_DG3 I On Open 408 AG11 DU1_DG4 I On Open 409 AF11 DU1_DG5 I On Open 410 AF10 DU1_DG6 I On Open 411 AE10 DU1_DG7 I On Open 412 AJ9 DU1_DB0 I On Open 413 AH9 DU1_DB1 I On Open 414 AG9 DU1_DB2 I On Open 415 AF9 DU1_DB3 I On Open 416 AE9 DU1_DB4 I On Open 417 AJ10 DU1_DB5 I MD11 Off Pulled up to VCCQ or pulled down ...

Page 88: ... 442 AD2 VI0_G1 I On Open 443 AD3 VI0_G2 I On Open 444 AD4 VI0_G3 I On Open 445 AD5 VI0_G4 I On Open 446 AD6 VI0_G5 I On Open 447 AE6 VI0_G6 I On Open 448 AD7 VI0_G7 I On Open 449 AE1 VI0_R0 I On Open 450 AE3 VI0_R1 I On Open 451 AE4 VI0_R2 I On Open 452 AE5 VI0_R3 I On Open 453 AF3 VI0_R4 I Off Pulled up to VCCQ or pulled down to VSS 454 AF4 VI0_R5 I Off Pulled up to VCCQ or pulled down to VSS 45...

Page 89: ...d up to VCCQ_SD0 or pulled down to VSS 494 AJ15 SD0_CD I Off Pulled up to VCCQ_SD0 or pulled down to VSS 495 AJ16 SD0_WP I Off Pulled up to VCCQ_SD0 or pulled down to VSS 496 AD16 VCCQ_SD0 Must be used 497 AL14 SD2_CLK I Off Pulled up to VCCQ_SD2 or pulled down to VSS 498 AH14 SD2_CMD I Off Pulled up to VCCQ_SD2 or pulled down to VSS 499 AG15 SD2_DATA0 I Off Pulled up to VCCQ_SD2 or pulled down to...

Page 90: ...528 AH18 I2C5_SDA Z Pulled up to VCCQ18 529 AJ19 IIC3_SCL Z Pulled up to VCCQ18 530 AH19 IIC3_SDA Z Pulled up to VCCQ18 531 P28 HCTS0 I On Open 532 R25 HRTS0 I On Open 533 P31 HSCK0 I On Open 534 P29 HRX0 I On Open 535 P30 HTX0 I Off Pulled up to VCCQ or pulled down to VSS 536 V25 HRX1 I Off Pulled up to VCCQ or pulled down to VSS 537 V26 HTX1 I Off Pulled up to VCCQ or pulled down to VSS 538 U31 ...

Page 91: ... be used 560 N29 VCCQ33_MLBP P Must be used 561 P27 VTHSENSE0 O Open or fixed to VSS 3 562 N27 VTHREF0 O Open or fixed to VSS 3 Notes 1 No 293 to 325 335 to 337 344 345 and 347 to 349 Boot Minimum number of pins that is necessary for area 0 boot operation must be used 2 No 329 to 334 Boot These pins must be used for QSPI boot 3 No 561 and 562 Pin handling when not in use Thermal sensor should be i...

Page 92: ...ule select register MOD_SEL module select register 2 MOD_SEL2 module select register 3 MOD_SEL3 and module register4 MOD_SEL4 For details see sections 5 3 27 Module Select Register MOD_SEL through 5 3 30 Module Select Register 4 MOD_SEL4 Pull up control for each LSI pin On off of the pull up or pull down resistors on each LSI pin can be controlled by setting the registers in the PFC module The pul...

Page 93: ... W H 0000 0000 H E606 000C 32 GPIO peripheral function select register 3 GPSR3 R W H 0000 0000 H E606 0010 32 GPIO peripheral function select register 4 GPSR4 R W H 0000 0000 H E606 0014 32 GPIO peripheral function select register 5 GPSR5 R W H 0000 0000 H E606 0018 32 GPIO peripheral function select register 6 GPSR6 R W H 4000 0000 H E606 001C 32 GPIO peripheral function select register 7 GPSR7 R...

Page 94: ... E606 0098 32 Module select register 4 MOD_SEL4 R W H 0000 0000 H E606 009C 32 LSI pin pull up control register 0 PUPR0 R W H D87F FFFF H E606 0100 32 LSI pin pull up control register 1 PUPR1 R W H EC8B7DC6 H E606 0104 32 LSI pin pull up control register 2 PUPR2 R W H DE61 F3FF H E606 0108 32 LSI pin pull up control register 3 PUPR3 R W H DFFF FFFF H E606 010C 32 LSI pin pull up control register 4...

Page 95: ...26EJ0100 Rev 1 00 5 4 Sep 30 2016 Name Abbr R W Initial Value Address Access Size Condition DDR3 general port output data register DDR3GPOD R W H 0000_0000 H E606 0248 32 DDR3 general port input data register DDR3GPID R H XXXX_XXX0 H E606 024C 32 ...

Page 96: ...0 Readable writable Writing 0 initializes the bit Writing 1 is ignored R WC1 Readable writable Writing 1 initializes the bit Writing 0 is ignored W Write only Reading this bit is prohibited When the bit is reserved the write value should always be 0 W Write only The read value is undefined All the bits are active high unless otherwise specified and deactivated on reset All access to registers is m...

Page 97: ... Bit Name Initial Value R W Description 31 to 0 PMPM 31 0 H 0000 0000 R W Multiplexed Pin Setting Mask Writing a value to any register from among the GPIO peripheral function select registers GPSR0 to GPSR7 peripheral function select registers IPSR0 to IPSR16 module select registers MOD_SEL MOD_SEL2 MOD_SEL3 and MOD_SEL4 IO cell control registers IOCTRL0 IOCTRL1 and IOCTRL4 to IOCTRL7 is enabled b...

Page 98: ... the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name GPIO Set Value 0 Peripheral Function Set Value 1 GP0 0 GP 0 0 Peripheral function selected by IP0 0 GP0 1 GP 0 1 Peripheral function selected by IP0 1 GP0 2 GP 0 2 Peripheral function selected by IP0 2 GP0 3 GP 0 3 Peripheral function selected by IP0 3 GP0 4 GP 0 4 Peripheral function selected by IP0 ...

Page 99: ...function selected by IP1 1 0 GP0 24 GP 0 24 Peripheral function selected by IP1 3 2 GP0 25 GP 0 25 Peripheral function selected by IP1 5 4 GP0 26 GP 0 26 Peripheral function selected by IP1 7 6 GP0 27 GP 0 27 Peripheral function selected by IP1 10 8 GP0 28 GP 0 28 Peripheral function selected by IP1 13 11 GP0 29 GP 0 29 Peripheral function selected by IP1 16 14 GP0 30 GP 0 30 Peripheral function s...

Page 100: ...tely set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name GPIO Set Value 0 Peripheral Function Set Value 1 GP1 0 GP 1 0 Peripheral function selected by IP1 25 23 GP1 1 GP 1 1 Peripheral function selected by IP1 28 26 GP1 2 GP 1 2 Peripheral function selected by IP1 31 29 GP1 3 GP 1 3 Peripheral function selected by IP2 2 0 GP1 4 GP 1 4 Peripheral fun...

Page 101: ...lue 1 GP1 21 GP 1 21 Peripheral function selected by IP3 13 12 GP1 22 GP 1 22 Peripheral function selected by IP3 15 14 GP1 23 GP 1 23 Peripheral function selected by IP3 17 16 GP1 24 GP 1 24 Peripheral function selected by IP3 19 18 GP1 25 GP 1 25 Peripheral function selected by IP3 21 20 GP1 26 GP1 27 GP1 28 GP1 29 GP1 30 GP1 31 ...

Page 102: ...P3 27 25 GP2 1 GP 2 1 Peripheral function selected by IP3 30 28 GP2 2 GP 2 2 Peripheral function selected by IP4 1 0 GP2 3 GP 2 3 Peripheral function selected by IP4 4 2 GP2 4 GP 2 4 Peripheral function selected by IP4 7 5 GP2 5 GP 2 5 Peripheral function selected by IP4 9 8 GP2 6 GP 2 6 Peripheral function selected by IP4 12 10 GP2 7 GP 2 7 Peripheral function selected by IP4 15 13 GP2 8 GP 2 8 P...

Page 103: ... 25 Peripheral function selected by IP5 25 24 GP2 26 GP 2 26 Peripheral function selected by IP5 28 26 GP2 27 GP 2 27 Peripheral function selected by IP5 31 29 GP2 28 GP 2 28 AUDIO_CLKA GP2 29 GP 2 29 Peripheral function selected by IP6 2 0 GP2 30 GP 2 30 Peripheral function selected by IP6 5 3 GP2 31 GP 2 31 Peripheral function selected by IP6 7 6 ...

Page 104: ... 5 3 GP3 1 GP 3 1 Peripheral function selected by IP7 8 6 GP3 2 GP 3 2 Peripheral function selected by IP7 10 9 GP3 3 GP 3 3 Peripheral function selected by IP7 12 11 GP3 4 GP 3 4 Peripheral function selected by IP7 14 13 GP3 5 GP 3 5 Peripheral function selected by IP7 16 15 GP3 6 GP 3 6 Peripheral function selected by IP7 18 17 GP3 7 GP 3 7 Peripheral function selected by IP7 20 19 GP3 8 GP 3 8 ...

Page 105: ...al function selected by IP9 7 GP3 26 GP 3 26 Peripheral function selected by IP9 10 8 GP3 27 GP 3 27 Peripheral function selected by IP9 11 GP3 28 GP 3 28 Peripheral function selected by IP9 12 GP3 29 GP 3 29 Peripheral function selected by IP9 15 13 GP3 30 GP 3 30 Peripheral function selected by IP9 16 GP3 31 GP 3 31 Peripheral function selected by IP9 18 17 ...

Page 106: ...Set Value 0 Peripheral Function Set Value 1 GP4 0 GP 4 0 VI0_CLK GP4 1 GP 4 1 Peripheral function selected by IP9 20 19 GP4 2 GP 4 2 Peripheral function selected by IP9 22 21 GP4 3 GP 4 3 Peripheral function selected by IP9 24 23 GP4 4 GP 4 4 Peripheral function selected by IP9 26 25 GP4 5 GP 4 5 VI0_DATA0_VI0_B0 GP4 6 GP 4 6 VI0_DATA1_VI0_B1 GP4 7 GP 4 7 VI0_DATA2_VI0_B2 GP4 8 GP 4 8 Peripheral f...

Page 107: ...unction selected by IP10 31 29 GP4 26 GP 4 26 Peripheral function selected by IP11 2 0 GP4 27 GP 4 27 Peripheral function selected by IP11 5 3 GP4 28 GP 4 28 Peripheral function selected by IP11 8 6 GP4 29 GP 4 29 Peripheral function selected by IP15 1 0 GP4 30 GP 4 30 Peripheral function selected by IP15 3 2 GP4 31 GP 4 31 Peripheral function selected by IP15 5 4 ...

Page 108: ...9 GP5 1 GP 5 1 Peripheral function selected by IP11 14 12 GP5 2 GP 5 2 Peripheral function selected by IP11 16 15 GP5 3 GP 5 3 Peripheral function selected by IP11 18 17 GP5 4 GP 5 4 Peripheral function selected by IP11 19 GP5 5 GP 5 5 Peripheral function selected by IP11 20 GP5 6 GP 5 6 Peripheral function selected by IP11 21 GP5 7 GP 5 7 Peripheral function selected by IP11 22 GP5 8 GP 5 8 Perip...

Page 109: ...ction selected by IP12 26 24 GP5 26 GP 5 26 Peripheral function selected by IP12 29 27 GP5 27 GP 5 27 Peripheral function selected by IP13 2 0 GP5 28 GP 5 28 Peripheral function selected by IP13 4 3 GP5 29 GP 5 29 Peripheral function selected by IP13 6 5 GP5 30 GP 5 30 Peripheral function selected by IP13 9 7 GP5 31 GP 5 31 Peripheral function selected by IP3 24 22 ...

Page 110: ...unction selected by IP13 10 GP6 1 GP 6 1 Peripheral function selected by IP13 11 GP6 2 GP 6 2 Peripheral function selected by IP13 12 GP6 3 GP 6 3 Peripheral function selected by IP13 13 GP6 4 GP 6 4 Peripheral function selected by IP13 14 GP6 5 GP 6 5 Peripheral function selected by IP13 15 GP6 6 GP 6 6 Peripheral function selected by IP13 18 16 GP6 7 GP 6 7 Peripheral function selected by IP13 2...

Page 111: ...P6 25 GP 6 25 Peripheral function selected by IP14 19 17 GP6 26 GP 6 26 Peripheral function selected by IP14 22 20 GP6 27 GP 6 27 Peripheral function selected by IP14 25 23 GP6 28 GP 6 28 Peripheral function selected by IP14 28 26 GP6 29 GP 6 29 Peripheral function selected by IP14 31 29 GP6 30 GP 6 30 USB1_OVC GP6 31 GP 6 31 DU0_DOTCLKIN ...

Page 112: ...unction selected by IP15 17 15 GP7 1 GP 7 1 Peripheral function selected by IP15 20 18 GP7 2 GP 7 2 Peripheral function selected by IP15 23 21 GP7 3 GP 7 3 Peripheral function selected by IP15 26 24 GP7 4 GP 7 4 Peripheral function selected by IP15 29 27 GP7 5 GP 7 5 Peripheral function selected by IP16 2 0 GP7 6 GP 7 6 Peripheral function selected by IP16 5 3 GP7 7 GP 7 7 Peripheral function sele...

Page 113: ...troller PFC R01UH0626EJ0100 Rev 1 00 5 22 Sep 30 2016 Bit Name GPIO Set Value 0 Peripheral Function Set Value 1 GP7 25 GP 7 25 USB1_PWEN GP7 26 GP 7 26 GP7 27 GP 7 27 GP7 28 GP 7 28 GP7 29 GP 7 29 GP7 30 GP 7 30 GP7 31 GP 7 31 ...

Page 114: ... R W R W R W R W R W R W R W R W R W Bit Initial Value R W Description 31 to 0 H 0000 0000 R W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Func...

Page 115: ... R W Bit Initial Value R W Description 31 to 0 H 0000 0000 R W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 ...

Page 116: ...31 to 0 H 0000 0000 R W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 ...

Page 117: ...rding to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Function 8 Set Value H 7 Others Set Value H 8 ...

Page 118: ...000 R W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set V...

Page 119: ...ue R W Description 31 to 0 H 0000 0000 R W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Functi...

Page 120: ...The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6...

Page 121: ...R W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Others Set Value H 6...

Page 122: ...functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Others Set Value H 6 to H F ...

Page 123: ...the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Others Set Value H 7 to H F IP9 2 0 DU1_DB6 I2C3_SCL_C ...

Page 124: ...W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H...

Page 125: ...o the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Others Set Value H 7 to H F IP11 2 0 VI0_R5 VI2_DATA6...

Page 126: ...00 0000 R W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Others Set Value H 5 to H F IP12 1 0 ...

Page 127: ...unctions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Func...

Page 128: ...the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Function 6 Set Value H 5 Function 7 Set Value H 6 Others Set Value...

Page 129: ...alue R W Description 31 to 0 H 0000 0000 R W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 Func...

Page 130: ... 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial Value R W Description 31 to 0 H 0000 0000 R W The functions of the LSI pins are selected according to the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set...

Page 131: ...P0 10 GP 0 11 D11 GP0 11 IP0 11 GP 0 12 D12 GP0 12 IP0 12 GP 0 13 D13 GP0 13 IP0 13 GP 0 14 D14 GP0 14 IP0 14 GP 0 15 D15 GP0 15 IP0 15 GP 0 16 A0 ATAWR0 _C MSIOF0_SCK_B I2C0_SCL_C PWM2_B GP0 16 IP0 18 16 GP 0 17 A1 MSIOF0_SYNC_ B GP0 17 IP0 20 19 GP 0 18 A2 MSIOF0_SS1_B GP0 18 IP0 22 21 GP 0 19 A3 MSIOF0_SS2_B GP0 19 IP0 24 23 GP 0 20 A4 MSIOF0_TXD_B GP0 20 IP0 26 25 GP 0 21 A5 MSIOF0_RXD_B GP0 2...

Page 132: ...PU_TO2 GP1 18 IP3 8 6 GP 1 19 RD GP1 19 GP 1 20 RD WR HRX2_B HRX2_ D SCIFB0_RXD_B DREQ1_D GP1 20 IP3 11 9 GP 1 21 WE0 HCTS2 _B SCIFB0_TXD_B GP1 21 IP3 13 12 GP 1 22 WE1 ATARD0 _B HTX2_B SCIFB0_RTS _B GP1 22 IP3 15 14 GP 1 23 EX_WAIT0 HRTS2 _B SCIFB0_CTS _ B GP1 23 IP3 17 16 GP 1 24 DREQ0 PWM3 TPU_TO3 GP1 24 IP3 19 18 GP 1 25 DACK0 DRACK0 GP1 25 IP3 21 20 GP 2 0 SSI_SCK0129 HRX0_C HRX2_C SCIFB0_RXD...

Page 133: ... SCIFA0_RXD_B MSIOF2_SYNC_ B GP3 1 IP7 8 6 GP 3 2 DU1_DR2 SSI_SCK0129_B GP3 2 IP7 10 9 GP 3 3 DU1_DR3 SSI_WS0129_B GP3 3 IP7 12 11 GP 3 4 DU1_DR4 SSI_SDATA0_B GP3 4 IP7 14 13 GP 3 5 DU1_DR5 SSI_SCK1_B GP3 5 IP7 16 15 GP 3 6 DU1_DR6 SSI_WS1_B GP3 6 IP7 18 17 GP 3 7 DU1_DR7 SSI_SDATA1_B GP3 7 IP7 20 19 GP 3 8 DU1_DG0 VI1_DATA2_B TX1_B SCIFA1_TXD_B MSIOF2_SS1_B GP3 8 IP7 23 21 GP 3 9 DU1_DG1 VI1_DATA...

Page 134: ...5 VI0_DATA0_VI0_ B0 GP4 5 GP 4 6 VI0_DATA1_VI0_ B1 GP4 6 GP 4 7 VI0_DATA2_VI0_ B2 GP4 7 GP 4 8 VI0_DATA3_VI0_ B3 SCIF3_SCK_B SCIFA3_SCK_B GP4 8 IP9 28 27 GP 4 9 VI0_DATA4_VI0_ B4 GP4 9 GP 4 10 VI0_DATA5_VI0_ B5 GP4 10 GP 4 11 VI0_DATA6_VI0_ B6 GP4 11 GP 4 12 VI0_DATA7_VI0_ B7 GP4 12 GP 4 13 VI0_G0 IIC1_SCL I2C4_SCL HCTS2 SCIFB2_CTS ATAWR1 GP4 13 IP9 31 29 GP 4 14 VI0_G1 IIC1_SDA I2C4_SDA HRTS2 SCI...

Page 135: ...1_DATA5 AVB_RX_DV GP5 10 IP11 25 GP 5 11 VI1_DATA6 AVB_MAGIC GP5 11 IP11 26 GP 5 12 VI1_DATA7 AVB_MDC GP5 12 IP11 27 GP 5 13 ETH_MDIO AVB_RX_CLK I2C2_SCL_C GP5 13 IP11 29 28 GP 5 14 ETH_CRS_DV AVB_LINK I2C2_SDA_C GP5 14 IP11 31 30 GP 5 15 ETH_RX_ER AVB_CRS I2C3_SCL IIC0_SCL GP5 15 IP12 1 0 GP 5 16 ETH_RXD0 AVB_PHY_INT I2C3_SDA IIC0_SDA GP5 16 IP12 3 2 GP 5 17 ETH_RXD1 AVB_GTXREFCL K CAN0_TX_C I2C2...

Page 136: ...8 IP14 4 GP 6 19 SD3_DATA1 MMC_D1 GP6 19 IP14 5 GP 6 20 SD3_DATA2 MMC_D2 GP6 20 IP14 6 GP 6 21 SD3_DATA3 MMC_D3 GP6 21 IP14 7 GP 6 22 SD3_CD MMC_D4 IIC1_SCL_C TX5_B SCIFA5_TXD_C GP6 22 IP14 10 8 GP 6 23 SD3_WP MMC_D5 IIC1_SDA_C RX5_B SCIFA5_RXD_ C GP6 23 IP14 13 11 GP 6 24 MSIOF0_SCK RX2_C VI1_CLK_C VI1_G0_B GP6 24 IP14 16 14 GP 6 25 MSIOF0_SYNC TX2_C VI1_CLKENB_C VI1_G1_B GP6 25 IP14 19 17 GP 6 2...

Page 137: ...D_E GP7 13 IP6 15 14 GP 7 14 IRQ4 HRX1_C HRX1_ E I2C4_SDA_C MSIOF2_RXD_E GP7 14 IP6 18 16 GP 7 15 IRQ5 HTX1_C HTX1_E I2C1_SCL_E MSIOF2_SCK_E GP7 15 IP6 20 19 GP 7 16 IRQ6 HSCK1_C MSIOF1_SS2_B I2C1_SDA_E MSIOF2_SYNC _E GP7 16 IP6 23 21 GP 7 17 IRQ7 HCTS1 _C MSIOF1_TXD_B GP7 17 IP6 26 24 GP 7 18 IRQ8 HRTS1 _C MSIOF1_RXD_B GP7 18 IP6 29 27 GP 7 19 IRQ9 DU1_DOTCLKIN _B CAN_CLK_D SCIF_CLK_B GP7 19 IP7 ...

Page 138: ... W R W R W Bit Initial Value R W Description 31 to 0 H 0000 0000 R W These bits select multiplexed pin functions as indicated in the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 F...

Page 139: ..._B of the EX_CS5 pin HTX1_B of the BS pin HCTS1 _C of the IRQ7 pin HRTS1 _C of the IRQ8 pin HRX1_C of the IRQ4 pin HSCK1_C of the IRQ6 pin HTX1_C of the IRQ5 pin HRX1_D of the VI0_R7 pin HTX1_D of the VI0_G5 pin HCTS1 _E of the SSI_WS2 pin HRTS1 _E of the SSI_SDATA2 pin HRX1_E of the IRQ4 pin HSCK1_E of the SSI_SCK2 pin HTX1_E of the IRQ5 pin sel_vi1 1 0 VI1_CLKENB of the VI1_CLKENB pin VI1_CLK of...

Page 140: ...I_SCK6 pin TS_SCK0_B of the VI1_VSYNC pin TS_SDATA0_B of the VI1_HSYNC pin TS_SDEN0_B of the VI1_CLKENB pin TS_SPSYNC0_B of the VI1_FIELD pin TS_SCK0_C of the VI0_R1 pin TS_SDATA0_C of the VI0_R0 pin TS_SDEN0_C of the VI0_R2 pin TS_SPSYNC0_C of the VI0_R3 pin TS_SCK0_D of the VI0_FIELD pin TS_SDATA0_D of the VI0_CLKENB pin TS_SDEN0_D of the VI0_HSYNC pin TS_SPSYNC0_D of the VI0_VSYNC pin sel_sof0 ...

Page 141: ... W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial Value R W Description 31 to 0 H 0000 0000 R W These bits select multiplexed pin functions as indicated in the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Functio...

Page 142: ...D of the VI0_FIELD pin SCIFA4_TXD of the VI0_CLKENB pin SCIFA4_RXD_B of the VI1_VSYNC pin SCIFA4_TXD_B of the VI1_HSYNC pin SCIFA4_RXD_C of the GPS_MAG pin SCIFA4_TXD_C of the GPS_SIGN pin sel_scifa3 1 0 SCIFA3_RXD of the DU1_DB6 pin SCIFA3_SCK of the DU1_DB7 pin SCIFA3_TXD of the DU1_DB5 pin SCIFA3_RXD_B of the ETH_REFCLK pin SCIFA3_SCK_B of the VI0_DATA3_VI0_B3 pin SCIFA3_TXD_B of the ETH_TXD1 p...

Page 143: ...tions as indicated in the table below Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register Bit Name Function 1 Set Value H 0 Function 2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 sel_hscif2 1 0 HCTS2 of the VI0_G0 pin HRTS2 of the VI0_G1 pin HRX2 of the VI0_G3 p...

Page 144: ...XODDF_ DU1_ODDF_DISP_CDE pin I2C2_SCL_C of the ETH_MDIO pin I2C2_SDA_C of the ETH_CRS_DV pin I2C2_SCL_D of the ETH_RXD1 pin I2C2_SDA_D of the ETH_LINK pin sel_i2c1 2 0 I2C1_SCL of the CS0 pin I2C1_SDA of the CS1 A26 pin I2C1_SCL_B of the SSI_WS1 pin I2C1_SDA_B of the SSI_SDATA1 pin I2C1_SCL_C of the SD2_CD pin I2C1_SDA_C of the SD2_WP pin I2C1_SCL_D of the VI0_R4 pin I2C1_SDA_D of the VI0_R5 pin I...

Page 145: ..._SCK5 pin MSIOF1_SYNC_C of the SSI_WS5 pin MSIOF1_TXD_C of the SSI_SDATA5 pin MSIOF1_RXD_D of the A11 pin MSIOF1_SCK_D of the A12 pin MSIOF1_SS1_D of the A13 pin MSIOF1_SYNC_D of the A14 pin MSIOF1_TXD_D of the A10 pin MSIOF1_RXD_E of the ETH_RXD1 pin MSIOF1_SCK_E of the ETH_LINK pin MSIOF1_SYNC_E of the ETH_REFCLK pin MSIOF1_TXD_E of the ETH_TXD1 pin sel_hscif0 1 0 HCTS0 of the HCTS0 pin HRTS0 of...

Page 146: ...2 Set Value H 1 Function 3 Set Value H 2 Function 4 Set Value H 3 Function 5 Set Value H 4 sel_ssi0 SSI_SCK0129 of the SSI_SCK0129 pin SSI_SDATA0 of the SSI_SDATA0 pin SSI_WS0129 of the SSI_WS0129 pin SSI_SCK0129_B of the DU1_DR2 pin SSI_SDATA0_B of the DU1_DR4 pin SSI_WS0129_B of the DU1_DR3 pin Legend Setting prohibited ...

Page 147: ...R W Bit Bit Name Initial Value R W Description 31 to 0 PUPR0 31 0 H D87F FFFF R W Performs individual on off control of the pull up resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR0 31 A9 pin is pulled up PUPR0 30 A8 pin is pulled up PUPR0 29 A7 pin is pulled up PUPR0 28 A6 pin is pulled up PUPR0 27 A5 pin is pul...

Page 148: ...ev 1 00 5 57 Sep 30 2016 Bit Name Set Value 1 PUPR0 6 D0 pin is pulled up PUPR0 5 DU0_DOTCLKIN pin is pulled up PUPR0 4 A24 pin is pulled up PUPR0 3 A23 pin is pulled up PUPR0 2 A22 pin is pulled up PUPR0 1 A21 pin is pulled up PUPR0 0 A20 pin is pulled up ...

Page 149: ...Description 31 to 0 PUPR1 31 0 H EC8B 7DC6 R W Performs individual on off control of the pull up resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR1 31 SSI_WS0129 pin is pulled up PUPR1 30 SSI_SCK0129 pin is pulled up PUPR1 29 SPEEDIN pin is pulled up PUPR1 28 DACK0 pin is pulled up PUPR1 27 DREQ0 pin is pulled up ...

Page 150: ...00 Rev 1 00 5 59 Sep 30 2016 Bit Name Set Value 1 PUPR1 6 A16 pin is pulled up PUPR1 5 A15 pin is pulled up PUPR1 4 A14 pin is pulled up PUPR1 3 A13 pin is pulled up PUPR1 2 A12 pin is pulled up PUPR1 1 A11 pin is pulled up PUPR1 0 A10 pin is pulled up ...

Page 151: ... W Performs individual on off control of the pull up resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR2 31 IRQ1 pin is pulled up PUPR2 30 IRQ0 pin is pulled up PUPR2 29 AUDIO_CLKOUT pin is pulled up PUPR2 28 AUDIO_CLKC pin is pulled up PUPR2 27 AUDIO_CLKB pin is pulled up PUPR2 26 AUDIO_CLKA pin is pulled up PUPR2...

Page 152: ... 30 2016 Bit Name Set Value 1 PUPR2 6 SSI_SDATA2 pin is pulled up PUPR2 5 SSI_WS2 pin is pulled up PUPR2 4 SSI_SCK2 pin is pulled up PUPR2 3 SSI_SDATA1 pin is pulled up PUPR2 2 SSI_WS1 pin is pulled up PUPR2 1 SSI_SCK1 pin is pulled up PUPR2 0 SSI_SDATA0 pin is pulled up ...

Page 153: ...W Description 31 to 0 PUPR3 31 0 H DFFF FFFF R W Performs individual on off control of the pull up resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR3 31 DU1_DB7 PUPR3 30 DU1_DB6 PUPR3 29 DU1_DB5 PUPR3 28 DU1_DB4 pin is pulled up PUPR3 27 DU1_DB3 pin is pulled up PUPR3 26 DU1_DB2 pin is pulled up PUPR3 25 DU1_DB1 p...

Page 154: ...ev 1 00 5 63 Sep 30 2016 Bit Name Set Value 1 PUPR3 6 IRQ8 pin is pulled up PUPR3 5 IRQ7 pin is pulled up PUPR3 4 IRQ6 pin is pulled up PUPR3 3 IRQ5 pin is pulled up PUPR3 2 IRQ4 pin is pulled up PUPR3 1 IRQ3 pin is pulled up PUPR3 0 IRQ2 pin is pulled up ...

Page 155: ...vidual on off control of the pull up resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR4 31 VI0_R2 pin is pulled up PUPR4 30 VI0_R1 pin is pulled up PUPR4 29 VI0_R0 pin is pulled up PUPR4 28 VI0_G7 pin is pulled up PUPR4 27 VI0_G6 pin is pulled up PUPR4 26 VI0_G5 pin is pulled up PUPR4 25 VI0_G4 pin is pulled up PU...

Page 156: ... PUPR4 6 DU1_DISP pin is pulled up PUPR4 5 DU1_EXODDF_DU1_ODDF_DISP_CDE pin is pulled up PUPR4 4 DU1_EXVSYNC_DU1_VSYNC pin is pulled up PUPR4 3 DU1_EXHSYNC_DU1_HSYNC pin is pulled up PUPR4 2 DU1_DOTCLKOUT1 pin is pulled up PUPR4 1 DU1_DOTCLKOUT0 pin is pulled up PUPR4 0 DU1_DOTCLKIN pin is pulled up ...

Page 157: ...rforms individual on off control of the pull up resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR5 31 STP_ISCLK_0 pin is pulled up PUPR5 30 STP_IVCXO27_0 pin is pulled up PUPR5 29 ETH_MDC pin is pulled up PUPR5 28 ETH_TXD0 pin is pulled up PUPR5 27 ETH_MAGIC pin is pulled up PUPR5 26 ETH_TX_EN pin is pulled up PUP...

Page 158: ...67 Sep 30 2016 Bit Name Set Value 1 PUPR5 6 VI1_VSYNC pin is pulled up PUPR5 5 VI1_HSYNC pin is pulled up PUPR5 4 VI0_R7 pin is pulled up PUPR5 3 VI0_R6 pin is pulled up PUPR5 2 VI0_R5 pin is pulled up PUPR5 1 VI0_R4 pin is pulled up PUPR5 0 VI0_R3 pin is pulled up ...

Page 159: ...00F R W Performs individual on off control of the pull up resistor provided in each signal pin of the LSI 0 Pull up function is disabled 1 Pull up function is enabled Bit Name Set Value 1 PUPR6 31 MSIOF0_RXD pin is pulled up PUPR6 30 MSIOF0_TXD pin is pulled up PUPR6 29 MSIOF0_SYNC pin is pulled up PUPR6 28 MSIOF0_SCK pin is pulled up PUPR6 27 SD3_WP pin is pulled up PUPR6 26 SD3_CD pin is pulled ...

Page 160: ...0 2016 Bit Name Set Value 1 PUPR6 6 SD0_DATA0 pin is pulled up PUPR6 5 SD0_CMD pin is pulled up PUPR6 4 SD0_CLK pin is pulled up PUPR6 3 STP_OPWM_0 pin is pulled up PUPR6 2 STP_ISSYNC_0 pin is pulled up PUPR6 1 STP_ISEN_0 pin is pulled up PUPR6 0 STP_ISD_0 pin is pulled up ...

Page 161: ...R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 0 PUPR7 31 0 H 015C 0FF3 R W Performs individual on off control of the pull up down resistor provided in each signal pin of the LSI 0 Pull up down function is disabled 1 Pull up down function is enabled Note Only PUPR7 19 ACK pin is available for pull down function Bit Name Set Value 1 PUPR7 31 PUPR7 30 PUPR7 ...

Page 162: ...me Set Value 1 PUPR7 7 GPS_MAG pin is pulled up PUPR7 6 GPS_SIGN pin is pulled up PUPR7 5 GPS_CLK pin is pulled up PUPR7 4 SIM0_D pin is pulled up PUPR7 3 SIM0_CLK pin is pulled up PUPR7 2 SIM0_RST pin is pulled up PUPR7 1 MSIOF0_SS2 pin is pulled up PUPR7 0 MSIOF0_SS1 pin is pulled up ...

Page 163: ...n 31 drv2_stpopwm 1 R W STP_OPWM_0 Setting The value of these bits must be 10 30 drv1_stpopwm 0 R W 29 to 16 All 0 R W 15 drv2_sd0wp 1 R W SD0_WP Setting The value of these bits must be 11 14 drv1_sd0wp 1 R W 13 drv2_sd0cd 1 R W SD0_CD Setting The value of these bits must be 11 12 drv1_sd0cd 1 R W 11 drv2_sd0clk 1 R W SD0_CLK Setting The value of these bits must be 11 10 drv1_sd0clk 1 R W 9 drv2_s...

Page 164: ... 1 R W SD2_CD Setting The value of these bits must be 11 28 drv1_sd2cd 1 R W 27 drv2_sd2clk 1 R W SD2_CLK Setting The value of these bits must be 11 26 drv1_sd2clk 1 R W 25 drv2_sd2cmd 1 R W SD2_CMD Setting The value of these bits must be 11 24 drv1_sd2cmd 1 R W 23 drv2_sd2d3 1 R W SD2_DATA3 Setting The value of these bits must be 11 22 drv1_sd2d3 1 R W 21 drv2_sd2d2 1 R W SD2_DATA2 Setting The va...

Page 165: ... Bit Bit Name Initial Value R W Description 1 drv2_sd3d0 1 R W SD3_DATA0 Setting The value of these bits must be 11 0 drv1_sd3d0 1 R W Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register ...

Page 166: ...clk _tdsel0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R W 13 irq5_tdsel1 0 R W IRQ5 Setting The value of these bits must be 00 12 irq5_tdsel0 0 R W 11 du1dr0_tdsel1 0 R W DU1_DR0 Setting The value of these bits must be 00 10 du1dr0_tdsel0 0 R W 9 to 4 All 0 R W 3 ethlin...

Page 167: ...ssisck5_tdsel1 0 R W SSI_SCK5 Setting The setting value of these bits must be 00 28 ssisck5_tdsel0 0 R W 27 ssisdat4_tdsel1 0 R W SSI_SDATA4 Setting The setting value of these bits must be 00 26 ssisdat4_tdsel0 0 R W 25 ssisdat0_tdsel1 0 R W SSI_SDATA0 Setting The setting value of these bits must be 00 24 ssisdat0_tdsel0 0 R W 23 excs1_tdsel1 0 R W EX_CS1 Setting The setting value of these bits mu...

Page 168: ... W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 poc_sd0clk 1 R W Selecting IO voltage for the pin SD0_CLK 0 1 8 V 1 3 3 V 30 poc_sd0cmd 1 R W Selecting IO voltage for the pin SD0_CMD 0 1 8 V 1 3 3 V 29 poc_sd0dat0 1 R W Selecting IO voltage for the pin SD0_DATA0 0 1 8 V 1 3 3 V 28 poc_sd0dat1 1 R W Selecting IO voltage for the pin SD0_DATA1 0 1 ...

Page 169: ...ltage for the pin SD3_CLK 0 1 8 V 1 3 3 V 14 poc_sd3cmd 1 R W Selecting IO voltage for the pin SD3_CMD 0 1 8 V 1 3 3 V 13 poc_sd3dat0 1 R W Selecting IO voltage for the pin SD3_DATA0 0 1 8 V 1 3 3 V 12 poc_sd3dat1 1 R W Selecting IO voltage for the pin SD3_DATA1 0 1 8 V 1 3 3 V 11 poc_sd3dat2 1 R W Selecting IO voltage for the pin SD3_DATA2 0 1 8 V 1 3 3 V 10 poc_sd3dat3 1 R W Selecting IO voltage...

Page 170: ... W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 gpreg_m sel03_p conta_II C3 DVF S contb_II C3 DVF S Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 13 All 0 R W 12 gpreg_msel03 _p 0 R W Debug monitor function 0 Use DU pins for debug monitor function 1 Use SDHI pins for debug moni...

Page 171: ... W R W R W R W R W R W R W R W R W R W R W R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DDR3EN 15 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 30 DDR3EN 31 30 00 R W 29 to 1 DDR3EN 29 1 0 R W For enabling DDR3 general port function bit 29 to 1 0 Disabled 1 Enabled 0 DDR3EN 0 0 R W ...

Page 172: ...1 DDR3OE 31 0 R W 30 DDR3OE 30 0 R W 29 DDR3OE 29 0 R W Enabling output of DDR3 general port function bit 29 0 Disabled 1 Enabled 28 DDR3OE 28 0 R W 27 DDR3OE 27 0 R W 26 DDR3OE 26 0 R W Enabling output of DDR3 general port function bit 26 0 Disabled 1 Enabled 25 DDR3OE 25 0 R W 24 DDR3OE 24 0 R W Enabling output of DDR3 general port function bit 24 0 Disabled 1 Enabled 23 DDR3OE 23 0 R W 22 DDR3O...

Page 173: ...isabled 1 Enabled 10 DDR3OE 10 0 R W 9 DDR3OE 9 0 R W Enabling output of DDR3 general port function bit 9 0 Disabled 1 Enabled 8 DDR3OE 8 0 R W 7 DDR3OE 7 0 R W Enabling output of DDR3 general port function bit 7 0 Disabled 1 Enabled 6 DDR3OE 6 0 R W 5 DDR3OE 5 0 R W 4 DDR3OE 4 0 R W 3 DDR3OE 3 0 R W Enabling output of DDR3 general port function bit 3 0 Disabled 1 Enabled 2 DDR3OE 2 0 R W Enabling...

Page 174: ...OD 24 0 R W For writing values to DDR3 general port bit 24 23 DDR3OD 23 0 R W 22 DDR3OD 22 0 R W 21 DDR3OD 21 0 R W For writing values to DDR3 general port bit 21 20 DDR3OD 20 0 R W For writing values to DDR3 general port bit 20 19 DDR3OD 19 0 R W For writing values to DDR3 general port bit 19 18 DDR3OD 18 0 R W 17 DDR3OD 17 0 R W For writing values to DDR3 general port bit 17 16 DDR3OD 16 0 R W F...

Page 175: ...0 2016 Bit Bit Name Initial Value R W Description 1 DDR3OD 1 0 R W For writing values to DDR3 general port bit 1 0 DDR3OD 0 0 R W Note To enable this register to be set appropriately set the multiplexed pin setting mask register PMMR immediately before setting this register ...

Page 176: ...rt bit 27 26 DDR3ID 26 0 R 25 DDR3ID 25 R Indicating values from DDR3 general port bit 25 24 DDR3ID 24 0 R 23 DDR3ID 23 R Indicating values from DDR3 general port bit 23 22 DDR3ID 22 R Indicating values from DDR3 general port bit 22 21 DDR3ID 21 0 R 20 DDR3ID 20 0 R 19 DDR3ID 19 0 R 18 DDR3ID 18 R Indicating values from DDR3 general port bit 18 17 DDR3ID 17 0 R 16 DDR3ID 16 0 R 15 DDR3ID 15 0 R 14...

Page 177: ...RZ G1M 5 Pin Function Controller PFC R01UH0626EJ0100 Rev 1 00 5 86 Sep 30 2016 Bit Bit Name Initial Value R W Description 0 DDR3ID 0 0 R ...

Page 178: ...OD_SEL2 to MOD_SEL4 registers can be set either earlier or later than setting IPSR0 to IPSR16 registers Note When GPIO is selected by GPSRn for an LSI pin and one of the below pin functions is selected by IPSRn make sure to disable data reception of SCIFA3 4 5 LSI Pin Pin Function DU1_DB6 SCIFA3_RXD ETH_REFCLK SCIFA3_RXD_B GPS_MAG SCIFA4_RXD_C GPS_SIGN SCIFA3_RXD_C SD0_WP SCIFA5_RXD_B SD3_WP SCIFA...

Page 179: ...H_REFCLK SCIFA3_RXD_B GPS_MAG SCIFA4_RXD_C GPS_SIGN SCIFA3_RXD_C SD0_WP SCIFA5_RXD_B SD3_WP SCIFA5_RXD_C VI0_FIELD SCIFA4_RXD_ VI0_VSYNC SCIFA5_RXD VI1_VSYNC SCIFA4_RXD_B 3 Procedure 1 for changing pin function from one peripheral function to another peripheral function Set the LSI multiplexed pin setting mask register Set the LSI multiplexed pin setting mask register Set the GPIO peripheral funct...

Page 180: ...l before performing the sequence in the Figure 5 3 LSI Pin Pin Function DU1_DB6 SCIFA3_RXD ETH_REFCLK SCIFA3_RXD_B GPS_MAG SCIFA4_RXD_C GPS_SIGN SCIFA3_RXD_C SD0_WP SCIFA5_RXD_B SD3_WP SCIFA5_RXD_C VI0_FIELD SCIFA4_RXD VI0_VSYNC SCIFA5_RXD VI1_VSYNC SCIFA4_RXD_B 5 4 2 Setting Pull Up Down Resistors The LSI pin pull up down control registers 0 to 7 PUPR0 to PUPR7 are used to switch the pull up down...

Page 181: ...16 Main Revisions and Additions in this Edition Minor revisions such as corrections of errors in spelling and modifications of wording are not included in the revision history Rev Description Page Contents Summary 1 00 First edition issued ...

Page 182: ...RZ G1M User s Manual Hardware Publication Date Rev 1 00 Sep 30 2016 Published by Renesas Electronics Corporation ...

Page 183: ...l 135 080 Korea Tel 82 2 558 3737 Fax 82 2 558 5141 SALES OFFICES http www renesas com Refer to http www renesas com for the latest and detailed information Renesas Electronics America Inc 2801 Scott Boulevard Santa Clara CA 95050 2549 U S A Tel 1 408 588 6000 Fax 1 408 588 6130 Renesas Electronics Canada Limited 9251 Yonge Street Suite 8309 Richmond Hill Ontario Canada L4C 9T3 Tel 1 905 237 2004 ...

Page 184: ...RZ G1M R01UH0626EJ0100 ...

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