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RL78/G1P

CHAPTER 12 SERIAL INTERFACE IICA

R01UH0895EJ0100 Rev.1.00

511

Nov 29, 2019

(3) Slave operation

The processing procedure of the slave operation is as follows.

Basically, the slave operation is event-driven. Therefore, processing by the INTIICAn interrupt (processing that

must substantially change the operation status such as detection of a stop condition during communication) is

necessary.

In the following explanation, it is assumed that the extension code is not supported for data communication. It is

also assumed that the INTIICAn interrupt servicing only performs status transition processing, and that actual data

communication is performed by the main processing.

IICA

Interrupt servicing

Main processing

INTIICAn

Flag

Setting

Data

Setting

Therefore, data communication processing is performed by preparing the following three flags and passing them to

the main processing instead of INTIICAn.

<1> Communication mode flag

This flag indicates the following two communication statuses.



Clear mode:

Status in which data communication is not performed



Communication mode: Status in which data communication is performed (from valid address detection to

stop condition detection, no detection of ACK from master, address mismatch)

<2> Ready flag

This flag indicates that data communication is enabled. Its function is the same as the INTIICAn interrupt for

ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing.

Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by

interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag

being cleared (an address match is interpreted as a request for the next data).

<3> Communication direction flag

This flag indicates the direction of communication. Its value is the same as the TRCn bit.

Remark

n = 0, 1

Summary of Contents for RL78/G1P

Page 1: ...e of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through various means including the Renesas Electronics Corp website http www renesas com RL78 G1P User s Manual Hardware Rev 1 00 Nov 2019 16 16 Bit Single Chip Microcontrollers www renesas com ...

Page 2: ...onics with respect to maximum ratings operating power supply voltage range heat dissipation characteristics installation etc Renesas Electronics disclaims any and all liability for any malfunctions failure or accident arising out of the use of Renesas Electronics products outside of such specified ranges 7 Although Renesas Electronics endeavors to improve the quality and reliability of Renesas Ele...

Page 3: ...put signal during power off state as described in your product documentation 4 Handling of unused pins Handle unused pins in accordance with the directions given under handling of unused pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with an unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of the ...

Page 4: ...oftware Pin functions Internal block functions Interrupts Other on chip peripheral functions Electrical specifications CPU functions Instruction set Explanation of each instruction How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering logic circuits and microcontrollers To gain a general understanding of functions Read this manual in...

Page 5: ...d as such Documents Related to Devices Document Name Document No RL78 G1P User s Manual Hardware This manual RL78 Family User s Manual Software R01US0015E Documents Related to Flash Memory Programming Document Name Document No PG FP6 Flash Memory Programmer User s Manual R20UT4025E E1 E20 Emulator User s Manual R20UT0398E E2 Emulator User s Manual R20UT3538E E2 Lite Emulator User s Manual R20UT324...

Page 6: ...e without notice Be sure to use the latest version of each document when designing All trademarks and registered trademarks are the property of their respective owners EEPROM is a trademark of Renesas Electronics Corporation SuperFlash is a registered trademark of Silicon Storage Technology Inc in several countries including the United States and Japan Caution This product uses SuperFlash technolo...

Page 7: ...32 pin products 13 2 2 Functions Other Than Port Pins 14 2 2 1 With functions for each product 14 2 2 2 Function descriptions 15 2 3 Description of Pin Functions 17 2 3 1 P10 to P17 port 1 17 2 3 2 P20 to P27 port 2 17 2 3 3 P30 to P35 port 3 18 2 3 4 P40 port 4 19 2 3 5 P60 P61 port 6 20 2 3 6 P121 P122 port 12 20 2 3 7 P137 port 13 21 2 3 8 VDD VSS 21 2 3 9 RESET 21 2 3 10 REGC 21 2 4 Connection...

Page 8: ...ressing 49 3 4 Addressing for Processing Data Addresses 50 3 4 1 Implied addressing 50 3 4 2 Register addressing 50 3 4 3 Direct addressing 51 3 4 4 Short direct addressing 52 3 4 5 SFR addressing 53 3 4 6 Register indirect addressing 54 3 4 7 Based addressing 55 3 4 8 Based indexed addressing 59 3 4 9 Stack addressing 60 CHAPTER 4 PORT FUNCTIONS 64 4 1 Port Functions 64 4 2 Port Configuration 64 ...

Page 9: ... 0 1 PER0 PER1 107 5 3 7 High speed on chip oscillator frequency select register HOCODIV 109 5 3 8 High speed on chip oscillator trimming register HIOTRM 110 5 4 System Clock Oscillator 111 5 4 1 X1 oscillator 111 5 4 2 High speed on chip oscillator 114 5 4 3 Low speed on chip oscillator 114 5 5 Clock Generator Operation 115 5 6 Controlling Clock 117 5 6 1 Example of setting high speed on chip osc...

Page 10: ...ration function 158 6 4 2 Basic rules of 8 bit timer operation function channels 1 and 3 only 160 6 5 Operation of Counter 161 6 5 1 Count clock fTCLK 161 6 5 2 Start timing of counter 163 6 5 3 Operation of counter 164 6 6 Channel Output TOmn pin Control 169 6 6 1 TOmn pin output circuit configuration 169 6 6 2 TOmn pin output setting 170 6 6 3 Cautions on channel output operation 171 6 6 4 Colle...

Page 11: ...tchdog Timer 233 8 2 Configuration of Watchdog Timer 234 8 3 Register Controlling Watchdog Timer 235 8 3 1 Watchdog timer enable register WDTE 235 8 4 Operation of Watchdog Timer 236 8 4 1 Controlling operation of watchdog timer 236 8 4 2 Setting overflow time of watchdog timer 237 8 4 3 Setting window open period of watchdog timer 238 8 4 4 Setting watchdog timer interval interrupt 240 CHAPTER 9 ...

Page 12: ...0 9 6 11 Hardware trigger wait mode scan mode sequential conversion mode 281 9 6 12 Hardware trigger wait mode scan mode one shot conversion mode 282 9 7 A D Converter Setup Flowchart 283 9 7 1 Setting up software trigger mode 284 9 7 2 Setting up hardware trigger no wait mode 285 9 7 3 Setting up hardware trigger wait mode 286 9 7 4 Setup when temperature sensor output voltage internal reference ...

Page 13: ...register m SEm 328 11 3 11 Serial output enable register m SOEm 329 11 3 12 Serial output register m SOm 330 11 3 13 Serial output level register m SOLm 331 11 3 14 Serial standby control register m SSCm 332 11 3 15 Input switch control register ISC 333 11 3 16 Noise filter enable register 0 NFEN0 334 11 3 17 Port mode register 3 PM3 335 11 4 Operation Stop Mode 336 11 4 1 Stopping the operation b...

Page 14: ...12 3 2 IICA control register n0 IICCTLn0 471 12 3 3 IICA status register n IICSn 476 12 3 4 IICA flag register n IICFn 478 12 3 5 IICA control register n1 IICCTLn1 480 12 3 6 IICA low level width setting register n IICWLn 482 12 3 7 IICA high level width setting register n IICWHn 482 12 3 8 Port mode register 6 PM6 483 12 4 I2 C Bus Mode Functions 484 12 4 1 Pin configuration 484 12 4 2 Setting tr...

Page 15: ...rmination of DMA transfer 558 13 5 Example of Setting of DMA Controller 559 13 5 1 CSI consecutive transmission 559 13 5 2 Consecutive capturing of A D conversion results 561 13 5 3 UART consecutive reception ACK transmission 563 13 5 4 Holding DMA transfer pending by DWAITn bit 565 13 5 5 Forced termination by software 566 13 6 Cautions on Using DMA Controller 568 CHAPTER 14 EVENT LINK CONTROLLER...

Page 16: ... time select register OSTS 595 16 3 Standby Function Operation 596 16 3 1 HALT mode 596 16 3 2 STOP mode 600 16 3 3 SNOOZE mode 605 CHAPTER 17 RESET FUNCTION 608 17 1 Timing of Reset Operation 610 17 2 Register for Confirming Reset Source 616 17 2 1 Reset control flag register RESF 616 CHAPTER 18 POWER ON RESET CIRCUIT 619 18 1 Functions of Power on reset Circuit 619 18 2 Configuration of Power on...

Page 17: ...register RPECTL 649 20 6 RAM guard function 651 20 6 1 Invalid memory access detection control register IAWCTL 651 20 7 SFR guard function 652 20 7 1 Invalid memory access detection control register IAWCTL 652 20 8 Invalid memory access detection function 653 20 8 1 Invalid memory access detection control register IAWCTL 654 20 9 Frequency detection function 655 20 9 1 Timer input select register ...

Page 18: ...ng data flash memory 678 23 5 Programming Method 679 23 5 1 Controlling flash memory 679 23 5 2 Flash memory programming mode 680 23 5 3 Selecting communication mode 681 23 5 4 Communication commands 682 23 5 5 Description of signature data 684 23 6 Security Settings 685 23 7 Flash Memory Programming by Self programming 687 23 7 1 Flash shield window function 689 23 8 Processing Time for Each Comm...

Page 19: ...eristics 729 27 5 Peripheral Functions Characteristics 733 27 5 1 Serial array unit 733 27 5 2 Serial interface IICA 737 27 5 3 Dedicated Flash Memory Programmer Communication UART 738 27 6 Analog Characteristics 738 27 6 1 A D converter characteristics 738 27 6 2 Temperature sensor internal reference voltage characteristics 741 27 6 3 D A converter 741 27 6 4 POR circuit characteristics 742 27 6 ...

Page 20: ...erase writing function Self programming On chip debug function On chip power on reset POR circuit and voltage detector LVD On chip watchdog timer operable with the dedicated low speed on chip oscillator On chip clock output buzzer output controller On chip BCD adjustment I O ports 26 or 28 N ch open drain 2 Timer 16 bit timer TAU 4 channels Watchdog timer 1 channel Serial interface CSI 1 channel U...

Page 21: ...ed in the table below for self programming or rewriting of the data flash memory See below for the RAM areas used by the flash library RAM FSL Type01 FDL Type04 EEL Pack01 EEL Pack02 Self RAM size 896 bytes Note Self RAM size 136 bytes R5F11Z7AANA R5F11Z7ADNA R5F11ZBAAFP R5F11ZBADFP 1 5 KB FF900H to FFC7FH FF900H to FF987H Not available Note Functions supported in FSL Type01 are only basic functio...

Page 22: ...ial applications TA 40 to 85 C ROM capacity A 16 KB RL78 G1P group Memory type F Flash memory Renesas semiconductor product Renesas MCU Pin count 7 24 pin B 32 pin Pin Count Package Data Flash Fields of Application Packaging Specification Part Number 24 pins 24 pin plastic HWQFN 4 4 mm 0 5 mm pitch 2 KB A Tray R5F11Z7AANA 00 R5F11Z7AANA 20 Embossed Tape R5F11Z7AANA 40 D Tray R5F11Z7ADNA 00 R5F11Z7...

Page 23: ...0 TOOL0 RESET exposed die pad P27 ANI7 P10 ANI16 P12 TI03 TO03 INTP4 PCLBUZ0 P13 TI00 TO00 P15 PCLBUZ1 P16 TI01 TO01 INTP5 P137 INTP0 P122 X2 EXCLK P121 X1 REGC V SS V DD P30 INTP2 TxD0 TOOLTxD SO00 P31 INTP1 RxD0 TOOLRxD SI00 P32 INTP3 SCK00 P33 TI02 TO02 SSI00 P61 SDAA0 SDAA1 P60 SCLA0 SCLA1 INDEX MARK Caution Connect the REGC pin to VSS via a capacitor 0 47 to 1 F Remarks 1 For pin identificati...

Page 24: ...1 P10 P11 P12 TI03 TO03 INTP4 PCLBUZ0 P13 TI00 TO00 P14 P15 PCLBUZ1 P16 TI01 TO01 INTP5 P17 P40 TOOL0 RESET P137 INTP0 P122 X2 EXCLK P121 X1 REGC V SS V DD 16 15 14 13 12 11 10 9 25 26 27 28 29 30 31 32 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 P27 ANI7 P26 ANI6 P25 ANI5 P21 ANI1 AVREFM P20 ANI0 AVREFP P22 ANI2 ANO0 P23 ANI3 ANO1 P24 ANI4 Caution Connect the REGC pin to VSS via a capacitor 0 47 to 1...

Page 25: ...61 Port 6 P121 P122 Port 12 P137 Port 13 PCLBUZ0 PCLBUZ1 Programmable clock output buzzer output REGC Regulator capacitance RESET Reset RxD0 Receive data SCK00 Serial clock input output SCLA0 SCLA1 Serial clock input output SDAA0 SDAA1 Serial data input output SI00 Serial data input SO00 Serial data output SSI00 Serial interface chip select input TI00 to TI03 Timer input TO00 to TO03 Timer output ...

Page 26: ...MER ARRAY UNIT 4ch ch2 ch3 TI02 TO02 P33 TI03 TO03 P12 ch0 ch1 6 2 INTP0 P137 INTP1 P31 INTP2 P30 INTP3 P32 INTP4 P12 INTP5 P16 A D CONVERTER 6 ANI0 P20 to ANI3 P23 ANI7 P27 ANI16 P10 AVREFP P20 AVREFM P21 2 PORT 13 P137 TI00 TO00 P13 BCD ADJUSTMENT SCK00 P32 SO00 P30 SI00 P31 CSI00 VSS TOOLRxD P31 TOOLTxD P30 VDD SERIAL INTERFACE IICA0 IICA1 SDAA0 SDAA1 P61 SCLA0 SCLA1 P60 BUZZER OUTPUT PCLBUZ0 P...

Page 27: ...RAY UNIT 4ch ch2 ch3 TI02 TO02 P33 TI03 TO03 P12 ch0 ch1 6 2 INTP0 P137 INTP1 P31 INTP2 P30 INTP3 P32 INTP4 P12 INTP5 P16 A D CONVERTER 8 ANI0 P20 to ANI7 P27 AVREFP P20 AVREFM P21 2 PORT 13 P137 TI00 TO00 P13 BCD ADJUSTMENT SCK00 P32 SO00 P30 SI00 P31 CSI00 VSS TOOLRxD P31 TOOLTxD P30 VDD BUZZER OUTPUT PCLBUZ0 P12 PCLBUZ1 P15 CLOCK OUTPUT CONTROL PORT 6 P60 P61 2 2 TI01 TO01 P16 CODE FLASH MEMORY...

Page 28: ...Hz operation Instruction set Data transfer 8 16 bits Adder and subtractor logical operation 8 16 bits Multiplication 8 bits 8 bits Rotate barrel shift and bit manipulation set reset test and boolean operation etc I O port Total 20 28 CMOS I O 15 23 CMOS input 3 3 N ch O D I O 6 V tolerance 2 2 Timer 16 bit timer 4 channels TAU Watchdog timer 1 channel Timer output 4 PWM outputs 3 Clock output buzz...

Page 29: ...te Internal reset by RAM parity error Internal reset by illegal memory access Power on reset circuit Power on reset 1 51 0 03 V Power down reset 1 50 0 03 V Voltage detector 2 75 V to 3 13 V 4 stages On chip debug function Provided Power supply voltage VDD 2 7 to 3 6 V Operating ambient temperature TA 40 to 85 C Note The illegal instruction is generated when instruction code FFH is executed Reset ...

Page 30: ... O buffer power supplies are unique for all products The relationship between these power supplies and the pins is shown below The input and output buffer and pull up resistor settings for each port are also valid for the alternate function Table 2 1 Pin I O Buffer Power Supplies Power Supply Corresponding Pins VDD All pins ...

Page 31: ...I3 ANO1 P27 ANI7 P30 I O Port 3 4 bit I O port Input output can be specified Use of an on chip pull up resistor can be specified by a software setting at input port Input port INTP2 TxD0 TOOLTxD SO00 P31 INTP1 RxD0 TOOLRxD SI00 P32 INTP3 SCK00 P33 TI02 TO02 SSI00 P40 I O Port 4 1 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a soft...

Page 32: ...I5 P26 ANI6 P27 ANI7 P30 I O Port 3 6 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor can be specified by a software setting at input port Input port INTP2 TxD0 TOOLTxD SO00 P31 INTP1 RxD0 TOOLRxD SI00 P32 INTP3 SCK00 P33 TI02 TO02 SSI00 P34 P35 P40 I O Port 4 1 bit I O port Input output can be specified in 1 bit units Use of an on chip pull up resistor...

Page 33: ...ch product Function Name 32 pin 24 pin ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI16 ANO0 ANO1 AVREFM AVREFP INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 PCLBUZ0 PCLBUZ1 REGC RESET RxD0 SCK00 SCLA0 SCLA1 SDAA0 SDAA1 SI00 SO00 SSI00 TI00 TI01 TI02 TI03 TO00 TO01 TO02 Function Name 32 pin 24 pin TO03 TxD0 X1 X2 EXCLK VDD VSS TOOLRxD TOOLTxD TOOL0 ...

Page 34: ...ation capacitance for internal operation Connect to VSS via a capacitor 0 47 to 1 F RESET Input External reset input RxD0 Input Serial data input to UART0 SCK00 I O Clock I O for CSI00 SCLA0 I O Clock I O for I2 C SCLA1 SDAA0 I O Serial data I O for I2 C SDAA1 SI00 Input Serial data input to CSI00 SO00 Output Serial data output from CSI00 SSI00 Input Chip select input to CSI00 TI00 Input External ...

Page 35: ...ternal device connection used during flash memory programming TOOL0 I O Data I O for flash Memory programmer debugger Caution The relationship between the voltage on P40 TOOL0 and the operating mode after release from the reset state is as follows Table 2 2 Relationship between the Voltage on P40 TOOL0 and Operating Mode After Release from the Reset State P40 TOOL0 Operating Mode VDD Normal operat...

Page 36: ...lock capture trigger to 16 bit timers 00 01 and 03 b TO00 TO01 TO03 These are the timer output pins of 16 bit timers 00 01 and 03 c INTP4 INTP5 These are the external interrupt request input pins for which the valid edge rising edge falling edge or both rising and falling edges can be specified d PCLBUZ0 PCLBUZ1 These are the clock buzzer output pins e ANI16 24 pin products only This is an analog ...

Page 37: ...ion modes can be specified in 1 bit units 1 Port mode P30 to P35 function as an I O port P30 and P31 can be set to input or output port in 1 bit units using port mode register 3 PM3 2 Control mode P30 to P35 unction as external interrupt request input serial interface data I O clock I O chip select input programming UART I O and timer I O a INTP1 INTP2 INTP3 These are the external interrupt reques...

Page 38: ...erface data I O Use of an on chip pull up resistor can be specified by pull up resistor option register 4 PU4 Be sure to connect an external pull up resistor to P40 when on chip debugging is enabled by using an option byte The following operation modes can be specified in 1 bit units 1 Port mode P40 functions as an I O port P40 can be set to input or output port in 1 bit units using port mode regi...

Page 39: ...nput and timer I O a SCLA0 SCLA1 These are the serial clock I O pins of serial interface IICA0 and IICA1 b SDAA0 SDAA1 These are the serial data I O pins of serial interface IICA0 and IICA1 2 3 6 P121 P122 port 12 P121 and P122 function as an input port These pins also function as connecting resonator for main system clock and external clock input for main system clock The following operation mode...

Page 40: ...tial pin Remark Use bypass capacitors about 0 1 F as noise and latch up countermeasures with relatively thick wires at the shortest distance to VDD to VSS line 2 3 9 RESET This is the active low system reset input pin When the external reset pin is not used connect this pin directly or via a resistor to VDD When the external reset pin is used design the circuit based on VDD 2 3 10 REGC This is the...

Page 41: ... ANO0 44 P23 ANI3 ANO1 P24 ANI4Note 2 11 G P25 ANI5Note 2 P26 ANI6Note 2 P27 ANI7 P30 INTP2 TxD0 TOOLTxD SO00 8 R P31 INTP1 RxD0 TOOLRxD SI00 P32 INTP3 SCK00 P33 TI02 TO02 SSI00 P34Note 2 P35Note 2 P40 TOOL0 I O Input Independently connect to VDD or leave open Output Leave open P60 SCLA0 SCLA1 13 R Input Independently connect to VDD or VSS via a resistor Output Leave open P61 SDAA0 SDAA1 P121 X1 3...

Page 42: ...s characteristics IN data output disable VDD P ch IN OUT N ch VSS pullup enable VDD P ch Type 11 G Type 11 T data output disable VDD P ch IN OUT N ch input enable VSS P ch N ch _ VSS Series resistor string voltage Comparator data output disable VDD P ch IN OUT N ch P ch N ch input enable AVREFP AVREFM VSS P ch N ch _ VSS Series resistor string voltage Comparator ...

Page 43: ...or string voltage Comparator IN OUT N ch data output disable VSS Type 37 C Type 44 X1 input enable input enable P ch N ch X2 amp enable data output disable VDD P ch IN OUT N ch P ch N ch VREF Threshold voltage Comparator input enable _ VSS VSS P ch N ch Analog output voltage Caution A through current may flow if the pin is at an intermediate potential because the input buffer is still turned on wh...

Page 44: ...8 G1P CHAPTER 3 CPU ARCHITECTURE R01UH0895EJ0100 Rev 1 00 25 Nov 29 2019 CHAPTER 3 CPU ARCHITECTURE 3 1 Memory Space Products in the RL78 G1P can access a 1 MB address space Figure 3 1 shows the memory map ...

Page 45: ...ffers for use by the flash library arguments of library functions branch destinations in the processing of vectored interrupts or destinations or sources for DTC transfer to the area from FFE20H to FFEDFH when performing self programming or rewriting of the data flash memory 2 Instructions can be executed from the RAM area excluding the general purpose register area 3 Set the option bytes to 000C0...

Page 46: ...19 Remark The flash memory is divided into blocks one block 1 KB For the address values and block numbers see Table 3 1 Correspondence Between Address Values and Block Numbers in Flash Memory Block 00H Block 01H Block 0FH 1 KB 003FFH 00400H 00000H 007FFH 02BFFH 03C00H 03FFFH ...

Page 47: ...dress Values and Block Numbers in Flash Memory Address Value Block Number 00000H to 003FFH 00H 00400H to 007FFH 01H 00800H to 00BFFH 02H 00C00H to 00FFFH 03H 01000H to 013FFH 04H 01400H to 017FFH 05H 01800H to 01BFFH 06H 01C00H to 01FFFH 07H 02000H to 023FFH 08H 02400H to 027FFH 09H 02800H to 02BFFH 0AH 02C00H to 02FFFH 0BH 03000H to 033FFH 0CH 03400H to 037FFH 0DH 03800H to 03BFFH 0EH 03C00H to 0...

Page 48: ...384 8 bits 00000H to 03FFFH The internal program memory space is divided into the following areas 1 Vector table area The 128 byte area 00000H to 0007FH is reserved as a vector table area The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area Furthermore the interrupt jump address is a 64 K address of 00000H to 0FFFFH because t...

Page 49: ...02AH INTIICA1 0002CH INTTM00 0002EH INTTM01 00030H INTTM02 00032H INTTM03 2 CALLT instruction table area The 64 byte area 00080H to 000BFH can store the subroutine entry address of a 2 byte call instruction CALLT Set the subroutine entry address to a value in a range of 00000H to 0FFFFH because an address code is of 2 bytes 3 Option byte area A 4 byte area of 000C0H to 000C3H can be used as an opt...

Page 50: ...e fetched from this area The following show examples Example RL78 G1P Flash memory 16 KB RAM 1 5 KB RAM 1 5 KB General purpose registers 32 bytes Code flash memory Extended special function registers 2nd SFR 2 KB Mirror Data flash memory Reserved Reserved Code flash memory For example 03789H is mirrored to F3789H Data can therefore be read by MOV A 3789H instead of MOV ES 00H and MOV A ES 3789H Mi...

Page 51: ...generation sets this register to 00H Figure 3 2 Format of Processor Mode Control Register PMC Address FFFFEH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PMC 0 0 0 0 0 0 0 MAA MAA Selection of flash memory space for mirroring to area from F2000H to F3FFFH 0 02000H to 03FFFH is mirrored to F2000H to F3FFFH 1 Setting prohibited Cautions 1 Be sure to clear bit 0 MAA of this register to 0 default value ...

Page 52: ...r to RL78 Family Flash Self Programming Library Type 01 User s Manual and RL78 Family Data Flash Library Type 04 User s Manual RL78 G1P FFE20H to FFEFFH 3 The flash libraries use the parts of the RAM area referred to as self RAM in self programming or rewriting of the data flash memory For the sizes of the RAM areas used by the flash libraries see ROM RAM capacities in 1 1 Features 3 1 4 Special f...

Page 53: ...s correspondence between data memory and addressing For details of each addressing see 3 4 Addressing for Processing Data Addresses Figure 3 3 Correspondence Between Data Memory and Addressing Short direct addressing SFR addressing Register addressing Direct addressing Register indirect addressing Based addressing Based indexed addressing Special function registers SFR 256 bytes General purpose re...

Page 54: ...ecution Program status word contents are stored in the stack area upon vectored interrupt request is acknowledged or PUSH PSW instruction execution and are restored upon execution of the RETB RETI and POP PSW instructions Reset signal generation sets the PSW register to 06H Figure 3 5 Format of Program Status Word IE Z RBS1 AC RBS0 ISP0 CY 7 0 ISP1 PSW a Interrupt enable flag IE This flag controls...

Page 55: ...ea can be set as the stack area Figure 3 6 Format of Stack Pointer 15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 0 0 In stack addressing through a stack pointer the SP is decremented ahead of write save to the stack memory and is incremented after read restore from the stack memory Cautions 1 Since reset signal generation makes the SP contents undefined be sure to initial...

Page 56: ...Register banks to be used for instruction execution are set by the CPU control instruction SEL RBn Because of the 4 register bank configuration an efficient program can be created by switching between a register for normal processing and a register for interrupt processing for each bank Caution It is prohibited to use the general purpose register FFEE0H to FFEFFH space for fetching instructions or...

Page 57: ...uration of ES and CS Registers 0 0 0 0 ES3 ES2 ES1 ES0 7 0 ES 6 5 4 3 2 1 0 0 0 0 CS3 CP2 CP1 CP0 7 0 CS 6 5 4 3 2 1 Though the data area which can be accessed with 16 bit addresses is the 64 Kbytes from F0000H to FFFFFH using the ES register as well extends this to the 1 Mbyte from 00000H to FFFFFH Figure 3 9 Extension of Data Area Which Can Be Accessed Special function register SFR 256 bytes Ext...

Page 58: ...6 bit manipulation Describe the symbol defined by the assembler for the 16 bit manipulation instruction operand sfrp When specifying an address describe an even address Table 3 5 gives a list of the SFRs The meanings of items in the table are as follows Symbol Symbol indicating the address of a special function register It is a reserved word in the assembler and is defined as an sfr variable using...

Page 59: ...FFF1FH 8 bit A D conversion result register ADCRH R 00H FFF21H Port mode register 1 PM1 R W FFH FFF22H Port mode register 2 PM2 R W FFH FFF23H Port mode register 3 PM3 R W FFH FFF24H Port mode register 4 PM4 R W FFH FFF26H Port mode register 6 PM6 R W FFH FFF30H A D converter mode register 0 ADM0 R W 00H FFF31H Analog input channel specification register ADS R W 00H FFF32H A D converter mode regis...

Page 60: ...dog timer enable register WDTE R W 1AH 9AHNote 4 FFFACH CRC input register CRCIN R W 00H FFFB0H DMA SFR address register 0 DSA0 R W 00H FFFB1H DMA SFR address register 1 DSA1 R W 00H FFFB2H DMA RAM address register 0L DRA0L DRA0 R W 00H FFFB3H DMA RAM address register 0H DRA0H R W 00H FFFB4H DMA RAM address register 1L DRA1L DRA1 R W 00H FFFB5H DMA RAM address register 1H DRA1H R W 00H FFFB6H DMA ...

Page 61: ... MK0 R W FFH FFFE5H Interrupt mask flag register 0H MK0H R W FFH FFFE6H Interrupt mask flag register 1L MK1L R W FFH FFFE8H Priority specification flag register 00L PR00L PR00 R W FFH FFFE9H Priority specification flag register 00H PR00H R W FFH FFFEAH Priority specification flag register 01L PR01L R W FFH FFFECH Priority specification flag register 10L PR10L PR10 R W FFH FFFEDH Priority specifica...

Page 62: ...on Describe the symbol defined by the assembler for the 8 bit manipulation instruction operand addr16 This manipulation can also be specified with an address 16 bit manipulation Describe the symbol defined by the assembler for the 16 bit manipulation instruction operand addr16 When specifying an address describe an even address Table 3 6 gives a list of the extended SFRs The meanings of items in t...

Page 63: ...register 1 NFEN1 R W 00H F0073H Input switch control register ISC R W 00H F0074H Timer input select register 0 TIS0 R W 00H F0076H A D port configuration register ADPC R W 00H F0078H Invalid memory access detection control register IAWCTL R W 00H F007AH Peripheral enable register 1 PER1 R W 00H F0090H Data flash control register DFLCTL R W 00H F00A0H High speed on chip oscillator trimming register...

Page 64: ... SS0L SS0 R W 0000H F0123H F0124H Serial channel stop register 0 ST0L ST0 R W 0000H F0125H F0126H Serial clock select register 0 SPS0L SPS0 R W 0000H F0127H F0128H Serial output register 0 SO0 R W 0303H F0129H F012AH Serial output enable register 0 SOE0L SOE0 R W 0000H F012BH F0134H Serial output level register 0 SOL0L SOL0 R W 0000H F0135H F0138H Serial standby control register 0 SSC0L SSC0 R W 0...

Page 65: ...H F01B8H Timer output register 0 TO0L TO0 R W 0000H F01B9H F01BAH Timer output enable register 0 TOE0L TOE0 R W 0000H F01BBH F01BCH Timer output level register 0 TOL0L TOL0 R W 0000H F01BDH F01BEH Timer output mode register 0 TOM0L TOM0 R W 0000H F01BFH F0230H IICA control register 00 IICCTL00 R W 00H F0231H IICA control register 01 IICCTL01 R W 00H F0232H IICA low level width setting register 0 I...

Page 66: ...utput destination select register 02 ELSELR02 R W 00H F0303H Event output destination select register 03 ELSELR03 R W 00H F0304H Event output destination select register 04 ELSELR04 R W 00H F0305H Event output destination select register 05 ELSELR05 R W 00H F0306H Event output destination select register 06 ELSELR06 R W 00H F0307H Event output destination select register 07 ELSELR07 R W 00H F0308H...

Page 67: ...tructions Figure 3 10 Outline of Relative Addressing OP code PC DISPLACE 8 16 bits Instruction code 3 3 2 Immediate addressing Function Immediate addressing stores immediate data of the instruction word in the program counter and specifies the program address to be used as the branch destination For immediate addressing CALL addr20 or BR addr20 is used to specify 20 bit addresses and CALL addr16 o...

Page 68: ... branching is enabled only to the 64 KB space from 00000H to 0FFFFH Figure 3 13 Outline of Table Indirect Addressing Low Addr High Addr 0 0000 OPcode 0 0 0 0 0 0 0 0 10 Table add ress PCS PC PCH PCL Memory 3 3 4 Register indirect addressing Function Register indirect addressing stores in the program counter PC the contents of a general purpose register pair AX BC DE HL and CS register of the curre...

Page 69: ...employed with an instruction no particular operand format is necessary Implied addressing can be applied only to MULU X Figure 3 15 Outline of Implied Addressing A register OP code Memory register area Instruction code 3 4 2 Register addressing Function Register addressing accesses a general purpose register as an operand The instruction word of 3 bit long is used to select an 8 bit register and t...

Page 70: ...in the 64 KB area from F0000H to FFFFFH specifies the target location for use in access to the 2nd SFRs etc MOV addr16 A Instruction code Target memory Memory 1 1 OP code Low Addr High Addr FFFFFH Figure 3 18 Example of ES addr16 00000H X0000H OP code Low Addr High Addr ES The ES register 1 specifies a 64 KB area within the overall 1 MB space as the four higher order bits X of the address range A ...

Page 71: ...E20H to FFF1FH immediate data SADDRP Label or FFE20H to FFF1FH immediate data even address only Figure 3 19 Outline of Short Direct Addressing OP code Memory saddr FFF1FH FFE20H saddr Instruction code Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16 bit immediate data higher 4 bits of actual address are omitted and the values of addresses FFE20H to FFF1FH...

Page 72: ...fies the target SFR addresses using 8 bit data in the instruction word This type of addressing is applied only to the space from FFF00H to FFFFFH Operand format Identifier Description SFR SFR name SFRP 16 bit manipulatable SFR name even address Figure 3 20 Outline of SFR Addressing OP code Memory SFR FFFFFH FFF00H SFR Instruction code ...

Page 73: ...FFFFH F0000H rp HL DE Either pair of registers 1 specifies the target location as an address in the 64 KB area from F0000H to FFFFFH DE HL Target memory Memory 1 1 1 1 Specifies the address in memory Instruction code OP code Figure 3 22 Example of ES DE ES HL FFFFFH 00000H X0000H ES OP code rp HL DE The ES register 1 specifies a 64 KB area within the overall 1 MB space as the four higher order bit...

Page 74: ... word B word C only the space from F0000H to FFFFFH is specifiable word BC only the space from F0000H to FFFFFH is specifiable ES HL byte ES DE byte higher 4 bit addresses are specified by the ES register ES word B ES word C higher 4 bit addresses are specified by the ES register ES word BC higher 4 bit addresses are specified by the ES register Figure 3 23 Example of SP byte FFFFFH F0000H SP Targ...

Page 75: ... C OP code Low Addr High Addr Instruction code Array of word sized data word 1 specifies the address where the target array of word sized data starts in the 64 KB area from F0000H to FFFFFH Either register 2 specifies an offset within the array to the target location in memory Target memory Memory 1 1 2 1 2 2 2 Address of a word within an array Offset Figure 3 26 Example of word BC FFFFFH F0000H r...

Page 76: ...n memory The ES register 1 specifies a 64 Kbyte area within the overall 1 MB space as the four higher order bits X of the address range Figure 3 28 Example of ES word B ES word C XFFFFH X0000H r B C X0000H ES ES word B ES word C Specifies a 64 KB area Array of word sized data Offset Address of a word within an array Target memory Instruction code 1 2 2 3 3 3 3 1 1 1 2 2 Memory OP code Low Addr Hig...

Page 77: ... Target memory Memory XFFFFH Array of word sized data Address of a word within an array The ES register 1 specifies a 64 Kbyte area within the overall 1 Mbyte space as the four higher order bits X of the address range word 2 specifies the address where the target array of word sized data starts in the 64 KB area specified in the ES register 1 A pair of registers 3 specifies an offset within the ar...

Page 78: ...et memory Memory Address of an array A pair of registers 1 specifies the address where the target array of data starts in the 64 KB area from F0000H to FFFFFH Either register 2 specifies an offset within the array to the target location in memory Target array of data Other data in the array Figure 3 31 Example of ES HL B ES HL C X0000H rp HL X0000H ES ES HL B ES HL C r B C OP code byte XFFFFH Targ...

Page 79: ...scription PUSH PSW AX BC DE HL POP PSW AX BC DE HL CALL CALLT RET BRK RETB Interrupt request generated RETI The data saved restored by each stack operation is shown in Figures 3 32 to 3 37 Figure 3 32 Example of PUSH rp Higher order byte of rp SP F0000H PUSH rp Lower order byte of rp SP 1 SP 2 rp SP OP code 1 1 2 2 3 Stack area Memory Stack addressing is specified 1 The higher order and lower orde...

Page 80: ...increased by two if rp is the program status word PSW the content of address SP 1 is stored in the PSW Instruction code Figure 3 34 Example of CALL CALLT CALL 00H SP F0000H PC SP SP 1 SP 2 SP 3 SP 4 OP code 1 1 2 Stack area Memory Instruction code 3 Stack addressing is specified 1 The value of the program counter PC changes to indicate the address of the instruction following the CALL instruction ...

Page 81: ...he value of SP 3 is increased by four Figure 3 36 Example of Interrupt BRK PSW SP F0000H PC19 PC16 PC SP PC15 PC8 PC7 PC0 or PSW SP 1 SP 2 SP 3 SP 4 OP code 1 2 2 Stack area Memory Instruction code Interrupt 3 Stack addressing is specified 1 In response to a BRK instruction or acceptance of an interrupt the value of the program counter PC changes to indicate the address of the next instruction The...

Page 82: ...ETI RETB SP F0000H PC SP PSW Stack area Memory SP 3 SP 2 SP 3 SP 2 SP 1 SP SP 1 SP SP 4 OP code 1 1 Instruction code 2 3 Stack addressing is specified 1 The contents of addresses SP SP 1 SP 2 and SP 3 are stored in PC bits 7 to 0 15 to 8 19 to 16 and the PSW respectively 2 The value of SP 3 is increased by four ...

Page 83: ...tion Ports include the following hardware Table 4 1 Port Configuration Item Configuration Control registers Port mode registers PM1 to PM4 PM6 Port registers P1 to P4 P6 P12 P13 Pull up resistor option registers PU1 PU3 PU4 Port mode control register 1 PMC1 A D port configuration register ADPC Port 24 pin products Total 20 CMOS I O 15 CMOS input 3 N ch open drain I O 2 32 pin products Total 28 CMO...

Page 84: ...tput 0Note 3 CMOS output P13 Input 1 CMOS input Output 0 TO00 output 0Note 3 CMOS output P14 Input 1 CMOS input Output 0 CMOS output P15 Input 1 CMOS input Output 0 PCLBUZ1 output 0Note 2 CMOS output P16 Input 1 CMOS input Output 0 TO01 output 0Note 3 CMOS output P17 Input 1 CMOS input Output 0 CMOS output Notes 1 To use P12 TI03 TO03 INTP4 PCLBUZ0 as a general purpose port set bit 7 PCLOE0 of clo...

Page 85: ...ms of port 1 Figure 4 1 Block Diagrams of P10 24 pin products P10 ANI16 WRPU RD WRPORT WRPM PU10 Output latch P10 PM10 VDD P ch PU1 PM1 P1 A D converter WRPMC PMC1 PMC10 Selector Internal bus P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 PMC1 Port mode control register 1 WR Write signal ...

Page 86: ... of P10 P11 P14 and P17 32 pin products P10 P11 P14 P17 WRPU RD WRPORT WRPM VDD P ch PU1 PM1 P1 PM10 PM11 PM14 PM17 Output latch P10 P11 P14 P17 PU10 PU11 PU14 PU17 Internal bus Selector P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 87: ...I03 TO03 INTP4 PCLBUZ0 P13 TI00 TO00 P16 TI01 TO01 INTP5 WRPU RD WRPORT WRPM PU12 PU13 PU16 Output latch P12 P13 P16 PM12 PM13 PM16 VDD P ch PU1 PM1 P1 Alternate function Alternate function Selector Internal bus P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 88: ...2019 Figure 4 4 Block Diagrams of P15 P15 PCLBUZ1 WRPU RD WRPORT WRPM PU15 Output latch P15 PM15 VDD P ch PU1 PM1 P1 Internal bus Selector Alternate function P1 Port register 1 PU1 Pull up resistor option register 1 PM1 Port mode register 1 RD Read signal WR Write signal ...

Page 89: ... these pins starting from the next pin of P20 or P21 In other case use these pins as following order P24 P23 P22 P20 P21 P25 P26 P27 Table 4 3 Settings of Registers When Using Port 2 Name I O PM2n ADPC Alternate Function Setting Remark P2n Input 1 1 To use P2n as a port use these pins from a higher bit Output 0 1 Remarks 1 PM2 Port mode register 2 ADPC A D port configuration register 2 n 0 to 7 Ta...

Page 90: ...nput selection Input mode Enables D A conversion operation Selects ANI Setting prohibited Does not select ANI Analog output Stops D A conversion operation Selects ANI Analog input to be converted Does not select ANI Analog input not to be converted Output mode Enables D A conversion operation Selects ANI Setting prohibited Does not select ANI Stops D A conversion operation Selects ANI Does not sel...

Page 91: ...27 PM2 A D converter P2 WRADPC ADPC0 ADPC1 ADPC4 to ADPC7 ADPC 0 Analog input 1 Digital I O Internal bus Selector ADPC A D port configuration register P2 Port register 2 PM2 Port mode register 2 RD Read signal WR Write signal Figure 4 6 Block Diagram of P22 and P23 RD WRPORT WRPM PM2 A D converter P2 WRADPC ADPC2 ADPC3 ADPC 0 Analog input 1 Digital I O Output latch P22 P23 PM22 PM23 D A converter ...

Page 92: ...to input mode Table 4 6 Settings of Registers When Using Port 3 Name I O PM3 Alternate Function Setting Remark P30 Input 1 Output 0 SO00 TxD0 output 1Note 1 P31 Input 1 Output 0 P32 Input 1 Output 0 SCK00 output 1Note 1 P33 Input 1 Output 0 TO02 output 0Note 2 P34 P35 Input 1 Output 0 Notes 1 To use P30 INTP2 TxD0 TOOLTxD SO00 P32 INTP3 SCK00 as a general purpose port set bit 0 SE00 of serial chan...

Page 93: ...f port 3 for 32 pin products Figure 4 7 Block Diagram of P30 P30 INTP2 TxD0 TOOLTxD SO00 WRPU RD WRPORT WRPM PU30 Output latch P30 PM30 VDD P ch PU3 PM3 P3 Alternate function Internal bus Selector Alternate function P3 Port register 3 PU3 Pull up resistor option register 3 PM3 Port mode register 3 RD Read signal WR Write signal ...

Page 94: ...ure 4 8 Block Diagram of P31 P31 INTP1 RxD0 TOOLRxD SI00 WRPU RD WRPORT WRPM PU31 Output latch P31 PM31 VDD P ch PM3 PU3 P3 Alternate function Internal bus Selector P3 Port register 3 PU3 Pull up resistor option register 3 PM3 Port mode register 3 RD Read signal WR Write signal ...

Page 95: ... 4 9 Block Diagram of P32 P32 INTP3 SCK00 WRPU RD WRPORT WRPM PU32 Output latch P32 PM32 VDD P ch PU3 PM3 P3 Alternate function Internal bus Selector Alternate function P3 Port register 3 PU3 Pull up resistor option register 3 PM3 Port mode register 3 RD Read signal WR Write signal ...

Page 96: ...10 Block Diagram of P33 P33 TI02 TO02 SSI00 WRPU RD WRPORT WRPM PU33 Output latch P33 PM33 VDD P ch PU3 PM3 P3 Alternate function Internal bus Selector Alternate function P3 Port register 3 PU3 Pull up resistor option register 3 PM3 Port mode register 3 RD Read signal WR Write signal ...

Page 97: ...2019 Figure 4 11 Block Diagram of P34 and P35 P34 P35 WRPU RD WRPORT WRPM VDD P ch PU3 PM3 P3 PM34 PM35 Output latch P34 P35 PU34 PU35 Internal bus Selector P3 Port register 3 PU3 Pull up resistor option register 3 PM3 Port mode register 3 RD Read signal WR Write signal ...

Page 98: ...r debugger Reset signal generation sets port 4 to input mode Table 4 7 Settings of Registers When Using Port 4 Name I O PM4 Alternate Function Setting Remark P40 Input 1 Output 0 Caution When a tool is connected the P40 pin cannot be used as a port pin Remark don t care PM4 Port mode register 4 Figure 4 12 shows a block diagram of port 4 Figure 4 12 Block Diagram of P40 P40 TOOL0 RD WRPORT WRPM PM...

Page 99: ...Settings of Registers When Using Port 6 Name I O PM6 Alternate Function Setting Remark P60 Input 1 SCLA0 output 0Note Output 0 P61 Input 1 SDAA0 output 0Note Output 0 Note Stop the operation of serial interface IICA when using P60 SCLA0 SCLA1 and P61 SDAA0 SDAA1 as general purpose ports Remark don t care PM6 Port mode register 6 Figure 4 13 shows a block diagram of port 6 Figure 4 13 Block Diagram...

Page 100: ...nction Setting Remark P121 Input OSCSEL bit of CMC register 0 or EXCLK bit 1 P122 Input OSCSEL bit of CMC register 0 Caution The function setting on P121 and P122 is available only once after the reset release The port once set for connection to an X1 oscillator external clock input cannot be used as an input port unless the reset is performed Figure 4 14 shows a block diagram of port 12 Figure 4 ...

Page 101: ...xed to an input ports This port can also be used for external interrupt request input Table 4 10 Settings of Registers When Using Port 13 Name I O Alternate Function Setting Remark P137 Input Remark don t care Figure 4 15 shows a block diagram of port 13 Figure 4 15 Block Diagram of P137 P137 INTP0 Alternate function Internal bus ...

Page 102: ...each product see Table 4 11 Be sure to set bits that are not mounted to their initial values Table 4 11 PMxx Pxx PUxx PMC1 Registers and Bits Mounted on Each Product 1 2 Port Bit Name 32 Pin 24 Pin PMxx Register Pxx Register PUxx Register PMC1 RegisterNote Port 1 0 PM10 P10 PU10 PMC10Note 1 PM11 P11 PU11 2 PM12 P12 PU12 3 PM13 P13 PU13 4 PM14 P14 PU14 5 PM15 P15 PU15 6 PM16 P16 PU16 7 PM17 P17 PU1...

Page 103: ...Mxx Pxx PUxx PMC1 Registers and Bits Mounted on Each Product 2 2 Port Bit Name 32 Pin 24 Pin PMxx Register Pxx Register PUxx Register PMC1 Register Port 4 0 PM40 P40 PU40 1 2 3 4 5 6 7 Port 6 0 PM60 P60 1 PM61 P61 2 3 4 5 6 7 Port 12 0 1 P121 2 P122 3 4 5 6 7 Port 13 0 1 2 3 4 5 6 7 P137 ...

Page 104: ...ction Figure 4 16 Format of Port Mode Register Symbol 7 6 5 4 3 2 1 0 Address After reset R W PM1 PM17Note PM16 PM15 PM14Note PM13 PM12 PM11Note PM10 FFF21H FFH R W PM2 PM27 PM26Note PM25Note PM24Note PM23 PM22 PM21 PM20 FFF22H FFH R W PM3 1 1 PM35Note PM34Note PM33 PM32 PM31 PM30 FFF23H FFH R W PM4 1 1 1 1 1 1 1 PM40 FFF24H FFH R W PM6 1 1 1 1 1 1 PM61 PM60 FFF26H FFH R W PMmn Pmn pin I O mode se...

Page 105: ...re 4 17 Format of Port Register Symbol 7 6 5 4 3 2 1 0 Address After reset R W P1 P17Note 3 P16 P15 P14Note 3 P13 P12 P11Note 3 P10 FFF01H 00H output latch R W P2 P27 P26Note 3 P25Note 3 P24Note 3 P23 P22 P21 P20 FFF02H 00H output latch R W P3 0 0 P35Note 3 P34Note 3 P33 P32 P31 P30 FFF03H 00H output latch R W P4 0 0 0 0 0 0 0 P40 FFF04H 00H output latch R W P6 0 0 0 0 0 0 P61 P60 FFF06H 00H outpu...

Page 106: ...ion output pins and analog setting PMC 1 regardless of the settings of these registers These registers can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears these registers to 00H Only PU4 is set to 01H Figure 4 18 Format of Pull up Resistor Option Register Symbol 7 6 5 4 3 2 1 0 Address After reset R W PU1 PU17Note PU16 PU15 PU14Note PU13 PU12 PU11Note PU10...

Page 107: ...4 19 Format of Port Mode Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset R W PMC1 1 1 1 1 1 1 1 PMC10 F0061H FFH R W PMC10 P10 pin digital I O analog input selection 0 Digital I O alternate function other than analog input 1 Analog input Cautions1 Set the channel used for A D conversion to the input mode by using port mode register 1 PM1 2 Do not set the pin set by the PMC register as ...

Page 108: ...C Address F0076H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADPC ADPC7 ADPC6Note ADPC5Note ADPC4Note ADPC3 ADPC2 ADPC1 ADPC0 ADPCn Analog input A digital I O D selection of P2n ANIn 0 Analog input A default 1 Digital I O D Note These are not provided in 24 pin products Cautions 1 Set the port to analog input by ADPC register to the input mode by using port mode register 2 PM2 2 Do not set the pin ...

Page 109: ...again The data of the output latch is cleared when a reset signal is generated 4 4 2 Reading from I O port 1 Output mode The output latch contents are read by a transfer instruction The output latch contents do not change 2 Input mode The pin status is read by a transfer instruction The output latch contents do not change 4 4 3 Operations on I O port 1 Output mode An operation is performed on the ...

Page 110: ...ion 1 2 Pin Name Alternate Function PM P Name I O P12 TI03 Input 1 TO03 Output 0 0 INTP4 Input 1 PCLBUZ0 Output 0 0 P13 TI00 Input 1 TO00 Output 0 0 P15 PCLBUZ1 Output 0 0 P16 TI01 Input 1 TO01 Output 0 0 INTP5 Input 1 P20Note ANI0Note Input 1 AVREFP Note Input 1 P21Note ANI1Note Input 1 AVREFM Note Input 1 P22Note ANI2Note Input 1 ANO0 Output 1 P23Note ANI3Note Input 1 ANO1 Output 1 P24 to P27Not...

Page 111: ... this table indicates the relationship when a 32 pin product is used In other products alternate functions might be assigned to different pins but even in this case the PMxx and Pxx set in the same way Note The functions of the ANI0 P20 to ANI7 P27 pins can be selected by using the A D port configuration register ADPC analog input channel specification register ADS and port mode register 2 PM2 Tab...

Page 112: ...sion operation Selects ANI Setting prohibited Does not select ANI Analog output Stops D A conversion operation Selects ANI Analog input to be converted Does not select ANI Analog input not to be converted Output mode Enables D A conversion operation Selects ANI Setting prohibited Does not select ANI Stops D A conversion operation Selects ANI Does not select ANI The functions of the ANI16 P10 pin o...

Page 113: ...it manipulation instruction is executed in the following order in the RL78 G1P 1 The Pn register is read in 8 bit units 2 The targeted one bit is manipulated 3 The Pn register is written in 8 bit units In step 1 the output latch value 0 of P10 which is an output port is read while the pin statuses of P11 to P17 which are input ports are read If the pin statuses of P11 to P17 are high level at this...

Page 114: ...0 Make sure that bit 0 SE00 of serial channel enable status register 0 SE0 bit 0 SO00 of serial output register 0 SO0 and bit 0 SOE00 of serial output enable register 0 SOE0 are set to their initial value 1 for SO00 and 0 for others IICA SCLAn SDAAn Disable the IICA operation by setting bit 7 IICEn of the IICCTLn0 register to 0 Example P12 TI03 TO03 INTP4 PCLBUZ0 pin 1 When the pin is used as PCLB...

Page 115: ...ystem clock control register CKC The frequency specified by using an option byte can be changed by using the high speed on chip oscillator frequency select register HOCODIV For details about the frequency see Figure 5 9 Format of High speed On chip Oscillator Frequency Select Register HOCODIV The frequencies that can be specified for the high speed on chip oscillator by using the option byte and t...

Page 116: ...mode control register CMC System clock control register CKC Clock operation status control register CSC Oscillation stabilization time counter status register OSTC Oscillation stabilization time select register OSTS Peripheral enable registers 0 1 PER0 PER1 High speed on chip oscillator frequency select register HOCODIV High speed on chip oscillator trimming register HIOTRM Oscillators X1 oscillat...

Page 117: ...P122 f X f EX MCM0 MCS CPU MOST 10 MOST 9 MOST 8 Clock operation status control register CSC HIOS TOP f IH f MAIN Main system clock source selector Low speed on chip oscillator 15 kHz TYP Option byte 000C0H WDTON WDSTBYON f IL HALT STOP mode signal Standby controller HALT mode STOP mode Normal operation mode Internal bus Serial array unit 0 Serial interface IICA0 A D converter Peripheral enable re...

Page 118: ...abilization time counter status register OSTC Oscillation stabilization time select register OSTS Peripheral enable registers 0 1 PER0 PER1 High speed on chip oscillator frequency select register HOCODIV High speed on chip oscillator trimming register HIOTRM Caution Which registers and bits are included depends on the product Be sure to set registers and bits that are not mounted in a product to t...

Page 119: ...z fX 20 MHz Cautions 1 The CMC register can be written only once after reset release by an 8 bit memory manipulation instruction When using the CMC register with its initial value 00H be sure to set the register to 00H after a reset ends in order to prevent malfunction due to a program loop Such a malfunction becomes unrecoverable when a value other than 00H is mistakenly written 2 After reset rel...

Page 120: ...s FFFA4H After reset 00H R WNote Symbol 7 6 5 4 3 2 1 0 CKC 0 0 MCS MCM0 0 0 0 0 MCS Status of Main system clock fMAIN 0 High speed on chip oscillator clock fIH 1 High speed system clock fMX MCM0 Main system clock fMAIN operation control 0 Selects the high speed on chip oscillator clock fIH as the main system clock fMAIN 1 Selects the high speed system clock fMX as the main system clock fMAIN Note...

Page 121: ...me select register OSTS before setting the MSTOP bit to 0 after releasing reset Note that if the OSTS register is being used with its default settings the OSTS register is not required to be set here 3 To start X1 oscillation as set by the MSTOP bit check the oscillation stabilization time of the X1 clock by using the oscillation stabilization time counter status register OSTC 4 Do not stop the cl...

Page 122: ...lator clock is being used as the CPU clock If the STOP mode is entered and then released while the high speed on chip oscillator clock is being used as the CPU clock with the X1 clock oscillating The OSTC register can be read by a 1 bit or 8 bit memory manipulation instruction When reset signal is generated the STOP instruction and MSTOP bit 7 of clock operation status control register CSC 1 clear...

Page 123: ...1 After the above time has elapsed the bits are set to 1 in order from the MOST8 bit and remain 1 2 The oscillation stabilization time counter counts up to the oscillation stabilization time set by the oscillation stabilization time select register OSTS In the following cases set the oscillation stabilization time of the OSTS register to the value greater than the count value which is to be checke...

Page 124: ...ime set using the OSTS register after the STOP mode is released When the CPU clock is switched from the high speed on chip oscillator clock to the X1 clock or when STOP mode is entered while the high speed on chip oscillator is used as the CPU clock and the X1 clock is also oscillating and then STOP mode is released The oscillation stabilization time can be checked up to the time set using the OST...

Page 125: ... counter counts up to the oscillation stabilization time set by the OSTS register In the following cases set the oscillation stabilization time of the OSTS register to the value greater than the count value which is to be checked by the OSTC register after the oscillation starts If the X1 clock starts oscillation while the high speed on chip oscillator clock is being used as the CPU clock If the S...

Page 126: ...ble Register 0 PER0 1 2 Address F00F0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PER0 0 IICA1EN ADCEN IICA0EN 0 SAU0EN 0 TAU0EN IICA1EN Control of serial interface IICA1 input clock supply 0 Stops input clock supply SFR used by the serial interface IICA1 cannot be written The serial interface IICA1 is in the reset status 1 Enables input clock supply SFR used by the serial interface IICA1 can be r...

Page 127: ...ontrol of timer array unit 0 input clock supply 0 Stops input clock supply SFR used by timer array unit 0 cannot be written Timer array unit 0 is in the reset status 1 Enables input clock supply SFR used by timer array unit 0 can be read and written Caution Be sure to clear bits 1 3 and 7 to 0 Figure 5 8 Format of Peripheral Enable Register 1 PER1 Address F007AH After reset 00H R W Symbol 7 6 5 4 ...

Page 128: ...D IV1 HOCOD IV0 High Speed On Chip Oscillator Clock Frequency FRQSEL3 Bit is 0 FRQSEL3 Bit is 1 0 0 0 24 MHz 32 MHz 0 0 1 12 MHz 16 MHz 0 1 0 6 MHz 8 MHz 0 1 1 3 MHz 4 MHz 1 0 0 Setting prohibited 2 MHz 1 0 1 Setting prohibited 1 MHz Other than above Setting prohibited Cautions 1 Set the HOCODIV register within the operable voltage range of the flash operation mode set in the option byte 000C2H be...

Page 129: ...ge accuracy adjustment must be executed regularly or before the frequency accuracy is required Figure 5 10 Format of High Speed On Chip Oscillator Trimming Register HIOTRM Address F00A0H After reset Note R W Symbol 7 6 5 4 3 2 1 0 HIOTRM 0 0 HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 High speed on chip oscillator 0 0 0 0 0 0 Minimum speed 0 0 0 ...

Page 130: ... either see Table 2 3 Connection of Unused Pins Figure 5 11 shows an example of the external circuit of the X1 oscillator Figure 5 11 Example of External Circuit of X1 Oscillator a Crystal or ceramic oscillation b External clock VSS X1 X2 Crystal resonator or ceramic resonator EXCLK External clock Caution When using the X1 oscillator wire as follows in the area enclosed by the broken lines in the ...

Page 131: ...PORT c The X1 and X2 signal line wires cross d A power supply GND pattern exists under the X1 and X2 wires X2 VSS X1 X1 Power supply GND pattern VSS X2 Note Note Do not place a power supply GND pattern under the wiring section section indicated by a broken line in the figure of the X1 and X2 pins and the resonators in a multi layer board or double sided board Do not configure a layout that will ca...

Page 132: ...gure 5 12 Examples of Incorrect Resonator Connection 2 2 e Wiring near high alternating current f Current flowing through ground line of oscillator potential at points A B and C fluctuates VSS X1 X2 VSS X1 X2 A B C Pmn VDD High current High current g Signals are fetched VSS X1 X2 ...

Page 133: ...tomatically starts oscillating after reset release 5 4 3 Low speed on chip oscillator The low speed on chip oscillator is incorporated in the RL78 G1P The low speed on chip oscillator clock is used only as the watchdog timer The low speed on chip oscillator clock cannot be used as the CPU clock This clock operates when bit 4 WDTON of the option byte 000C0H is set to 1 If the watchdog timer operate...

Page 134: ...re 5 1 Main system clock fMAIN High speed system clock fMX X1 clock fX External main system clock fEX High speed on chip oscillator clock fIH Low speed on chip oscillator clock fIL CPU peripheral hardware clock fCLK The CPU starts operation when the high speed on chip oscillator starts outputting after a reset release in the RL78 G1P When the power supply voltage is turned on the clock generator o...

Page 135: ...is in use 2 When the power supply voltage exceeds 1 51 V TYP the reset is released and the high speed on chip oscillator automatically starts oscillation 3 The CPU starts operation on the high speed on chip oscillator clock after waiting for the voltage to stabilize and a reset processing have been performed after reset release 4 Set the start of oscillation of the X1 clock via software see 5 6 2 ...

Page 136: ...ed main mode VDD 2 7 V to 3 6 V 1 MHz to 8 MHz 1 1 HS high speed main mode VDD 2 7 V to 3 6 V 1 MHz to 32 MHz Other than above Setting prohibited FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 Frequency of the high speed on chip oscillator 1 0 0 0 32 MHz 0 0 0 0 24 MHz 1 0 0 1 16 MHz 0 0 0 1 12 MHz 1 0 1 0 8 MHz 0 0 1 0 6 MHz 1 0 1 1 4 MHz 0 0 1 1 3 MHz 1 1 0 0 2 MHz 1 1 0 1 1 MHz Other than above Setting prohib...

Page 137: ...t for the cases where fX 10 MHz in such cases set 1 the AMPH bit to operate the X1 oscillator 7 6 5 4 3 2 1 0 CMC EXCLK 0 OSCSEL 1 0 0 0 0 0 AMPHNote 0 1 Note Set AMPH bit to 0 when X1 clock is 10 MHz or below 2 Using the OSTS register select the oscillation stabilization time of the X1 oscillator at releasing of the STOP mode Example Setting values when a wait of at least 102 s is set based on a ...

Page 138: ...oscillation EXCLK input Stops High speed on chip oscillator Operating X1 oscillation EXCLK input Stops High speed on chip oscillator Operating X1 oscillation EXCLK input Oscillatable High speed on chip oscillator Stops X1 oscillation EXCLK input Stops CPU High speed on chip oscillator STOP CPU High speed on chip oscillator SNOOZE CPU High speed on chip oscillator HALT CPU X1 oscillation EXCLK inpu...

Page 139: ...e 1 OSTS Register CSC Register OSTC Register CKC Register EXCLK OSCSEL AMPH MSTOP MCM0 A B C X1 clock 1 MHz fX 10 MHz 0 1 0 Note 2 0 Must be checked 1 A B C X1 clock 10 MHz fX 20 MHz 0 1 1 Note 2 0 Must be checked 1 A B C external main clock 1 1 Note 2 0 Must not be checked 1 Notes 1 The clock operation mode control register CMC can be written only once by an 8 bit memory manipulation instruction ...

Page 140: ...ssary if it has already been set 2 Set the oscillation stabilization time as follows Desired the oscillation stabilization time counter status register OSTC oscillation stabilization time Oscillation stabilization time set by the oscillation stabilization time select register OSTS Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set see CHAPTER 27 ...

Page 141: ... high speed on chip oscillator clock B STOP mode G set while CPU is operating with high speed system clock C Setting sequence Status Transition Setting B F Stopping peripheral functions that cannot operate in STOP mode Executing STOP instruction C G In X1 oscillation Sets the OSTS register External main system clock 7 CPU changing from STOP mode F to SNOOZE mode H For details about the setting for...

Page 142: ...he CPU clock has been switched to the clock after transition External main system clock Enabling input of external clock from the EXCLK pin OSCSEL 1 EXCLK 1 MSTOP 0 X1 clock High speed on chip oscillator clock Enabling oscillation of high speed on chip oscillator HIOSTOP 0 After elapse of oscillation stabilization time X1 oscillation can be stopped MSTOP 1 after checking that the CPU clock has bee...

Page 143: ...IH fMX clock 1 fMAIN fMX fMX fIH 2fMX fIH clock fMX fIH 2 clock Remarks 1 The number of clocks listed in Table 5 6 is the number of CPU clocks before switchover 2 Calculate the number of clocks in Table 5 6 by removing the decimal portion Example When switching the main system clock from the high speed system clock to the high speed on chip oscillator clock oscillation with fIH 8 MHz fMX 10 MHz 2f...

Page 144: ...r evaluation by the manufacturers For actual applications request evaluation by the manufacturer of the oscillator circuit mounted on a board Furthermore if you are switching from a different product to this microcontroller and whenever you change the board again request evaluation by the manufacturer of the oscillator circuit mounted on the new board 2 The oscillation voltage and oscillation freq...

Page 145: ...PTER 6 TIMER ARRAY UNIT The number of units or channels of the timer array unit differs depending on the product Units Channels 24 32 pin Unit 0 Channel 0 Channel 1 Channel 2 Channel 3 Caution Most of the following descriptions in this chapter use the 32 pin products as an example ...

Page 146: ...ation Function Interval timer see 6 8 1 Square wave output see 6 8 1 External event counter see 6 8 2 Input pulse interval measurement see 6 8 3 Measurement of high low level width of input signal see 6 8 4 Delay counter see 6 8 5 One shot pulse output see 6 9 1 PWM output see 6 9 2 Multiple PWM output see 6 9 3 It is possible to use the 16 bit timer of channels 1 and 3 of the unit 0 as two 8 bit ...

Page 147: ...l event counter Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid edges of a signal input to the timer input pin TImn has reached a specific value Interrupt signal INTTMmn Edge detection Timer input TImn Compare operation Channel n 4 Input pulse interval measurement Counting is started by the valid edge of a pulse signal input to a timer ...

Page 148: ...nels timers operating according to the master channel channels can be used for the following purposes 1 One shot pulse output Two channels are used as a set to generate a one shot pulse with a specified output timing and a specified pulse width Timer output TOmp Interrupt signal INTTMmn Edge detection Timer input TImn Set Master Output timing Pulse width Start Master Reset Slave Channel n master C...

Page 149: ...tion Timer output TOmp Timer output TOmq Caution For details about the rules of simultaneous channel operation function see 6 4 1 Basic rules of simultaneous channel operation function Remark m Unit number m 0 n Channel number n 0 to 3 p q Slave channel number n p q 3 6 1 3 8 bit timer operation function channels 1 and 3 only The 8 bit timer operation function makes it possible to use a 16 bit tim...

Page 150: ...ister m TEm Timer channel start register m TSm Timer channel stop register m TTm Timer input select register 0 TIS0 Timer output enable register m TOEm Timer output register m TOm Timer output level register m TOLm Timer output mode register m TOMm Registers of each channel Timer mode register mn TMRmn Timer status register mn TSRmn Noise filter enable register 1 NFEN1 Port mode register PMxx Note...

Page 151: ...nnel 1 Slave master controller Slave master controller 2 2 Timer clock select register 0 TPS0 4 4 fCLK fCLK 20 to fCLK 215 Selector Selector TAU0EN Peripheral enable register 0 PER0 Prescaler Selector Selector fCLK 21 fCLK 22 fCLK 24 fCLK 26 fCLK 28 fCLK 210 fCLK 212 fCLK 214 PRS013 PRS003 PRS012PRS011 PRS010 PRS002 PRS001 PRS000 PRS031PRS030 PRS021 PRS020 Timer input select register 0 TIS0 TIS02 ...

Page 152: ...filter enable register 1 NFEN1 STS 002 STS 001 STS 000 Figure 6 3 Internal Block Diagram of Channel 1 of Timer Array Unit 0 Mode selection Timer controller INTTM01H Timer interrupt Interrupt controller Output controller OVF01 Interrupt controller CK00 CK01 CK02 CK03 Edge detection TI01 fMCK Operating clock selection Count clock selection Trigger selection Interrupt signal from master channel Timer...

Page 153: ... master channel Slave master controller Noise filter TNFEN02 Noise filter enable register 1 NFEN1 STS 022 STS 021 STS 020 Figure 6 5 Internal Block Diagram of Channel 3 of Timer Array Unit 0 Mode selection Timer controller INTTM03H Timer interrupt Interrupt controller Output controller OVF03 Interrupt controller CK00 CK01 CK02 CK03 Edge detection fMCK Operating clock selection Count clock selectio...

Page 154: ...cleared to 0000H in the following cases When the start trigger is input in the capture mode When capturing has been completed in the capture mode Caution The count value is not captured to timer data register mn TDRmn even when the TCRmn register is read The TCRmn register read value differs as follows according to operation mode changes and the operating status Table 6 2 Timer Count Register mn T...

Page 155: ...dress FFF18H FFF19H TDR00 FFF64H FFF65H TDR02 After reset 0000H R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDRmn Figure 6 8 Format of Timer Data Register mn TDRmn n 1 3 Address FFF1AH FFF1BH TDR01 FFF66H FFF67H TDR03 After reset 0000H R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDRmn i When timer data register mn TDRmn is used as compare register Counting down is started from the value set to the TDR...

Page 156: ...er m TEm Timer channel start register m TSm Timer channel stop register m TTm Timer input select register 0 TIS0 Timer output enable register m TOEm Timer output register m TOm Timer output level register m TOLm Timer output mode register m TOMm Input switch control register ISC Noise filter enable register 1 NFEN1 Port mode register PMxx Port register Pxx Caution Which registers and bits are incl...

Page 157: ...t clock 0 Stops supply of input clock SFR used by the timer array unit 0 cannot be written The timer array unit 0 is in the reset status 1 Supplies input clock SFR used by the timer array unit 0 can be read written Cautions 1 When setting the timer array unit be sure to set the following registers first while the TAUmEN bit is set to 1 If TAUmEN 0 writing to a control register of timer array unit ...

Page 158: ... operation is possible only in the following cases If the PRSm00 to PRSm03 bits can be rewritten n 0 to 3 All channels for which CKm0 is selected as the operation clock CKSmn1 CKSmn0 0 0 are stopped TEmn 0 If the PRSm10 to PRSm13 bits can be rewritten n 0 to 3 All channels for which CKm1 is selected as the operation clock CKSmn1 CKSmn0 0 1 are stopped TEmn 0 If the PRSm20 and PRSm21 bits can be re...

Page 159: ...9 1 kHz 78 1 kHz 125 kHz 1 0 0 1 fCLK 29 3 91 kHz 9 76 kHz 19 5 kHz 39 1 kHz 62 5 kHz 1 0 1 0 fCLK 210 1 95 kHz 4 88 kHz 9 76 kHz 19 5 kHz 31 25 kHz 1 0 1 1 fCLK 211 976 Hz 2 44 kHz 4 88 kHz 9 76 kHz 15 63 kHz 1 1 0 0 fCLK 212 488 Hz 1 22 kHz 2 44 kHz 4 88 kHz 7 81 kHz 1 1 0 1 fCLK 213 244 Hz 610 Hz 1 22 kHz 2 44 kHz 3 91 kHz 1 1 1 0 fCLK 214 122 Hz 305 Hz 610 Hz 1 22 kHz 1 95 kHz 1 1 1 1 fCLK 215...

Page 160: ...5 kHz 1 0 fCLK 212 488 Hz 1 22 kHz 2 44 kHz 4 88 kHz 7 81 kHz 1 1 fCLK 214 122 HZ 305 Hz 610 Hz 1 22 kHz 1 95 kHZ Note When changing the clock selected for fCLK by changing the system clock control register CKC value stop timer array unit TTm 00FFH The timer array unit must also be stopped if the operating clock fMCK specified by using the CKSmn0 and CKSmn1 bits or the valid edge of the signal inp...

Page 161: ...t or capture and one count Rewriting the TMRmn register is prohibited when the register is in operation when TEmn 1 However bits 7 and 6 CISmn1 CISmn0 can be rewritten even while the register is operating with some functions when TEmn 1 for details see 6 8 Independent Channel Operation Function of Timer Array Unit and 6 9 Simultaneous Channel Operation Function of Timer Array Unit The TMRmn regist...

Page 162: ...select register m TPSm 1 1 Operation clock CKm3 set by timer clock select register m TPSm Operation clock fMCK is used by the edge detector A count clock fTCLK and a sampling clock are generated depending on the setting of the CCSmn bit The operation clocks CKm2 and CKm3 can only be selected for channels 1 and 3 CCS mn Selection of count clock fTCLK of channel n 0 Operation clock fMCK specified by...

Page 163: ...unction Only channel 2 can be set as a master channel MASTERmn 1 Channel 0 is fixed to 0 channel 0 always operates as master regardless of the bit setting because it is the highest channel Clear the MASTERmn bit to 0 for a channel that is used with the independent channel operation function Bit 11 of TMRmn n 1 3 SPLI Tmn Selection of 8 or 16 bit timer operation for channels 1 and 3 0 Operates as 1...

Page 164: ...ed Start trigger Falling edge Capture trigger Rising edge 1 1 Both edges when high level width is measured Start trigger Rising edge Capture trigger Falling edge If both the edges are specified when the value of the STSmn2 to STSmn0 bits is other than 010B set the CISmn1 to CISmn0 bits to 10B MD mn3 MD mn2 MD mn1 Operation mode of channel n Corresponding function Count operation of TCR 0 0 0 Inter...

Page 165: ...ounting is started timer output does not change either 1 Timer interrupt is generated when counting is started timer output also changes Event counter mode 0 1 1 0 Timer interrupt is not generated when counting is started timer output does not change either One count modeNote 2 1 0 0 0 Start trigger is invalid during counting operation At that time interrupt is not generated 1 Start trigger is val...

Page 166: ...mer Status Register mn TSRmn Address F01A0H F01A1H TSR00 to F01A6H F01A7H TSR03 After reset 0000H R Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF OVF Counter overflow status of channel n 0 Overflow does not occur 1 Overflow occurs When OVF 1 this flag is cleared OVF 0 when the next value is captured without overflow Remark m Unit number m 0 n Channel number n...

Page 167: ...et signal generation clears this register to 0000H Figure 6 13 Format of Timer Channel Enable Status register m TEm Address F01B0H F01B1H TE0 After reset 0000H R Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEm 0 0 0 0 TEHm 3 0 TEHm 1 0 0 0 0 0 TEm 3 TEm 2 TEm 1 TEm 0 TEH 03 Indication of whether operation of the higher 8 bit timer is enabled or stopped when channel 3 is in the 8 bit timer mode 0 ...

Page 168: ...ount operation enabled state see Table 6 5 in 6 5 2 Start timing of counter TSH m1 Trigger to enable operation start operation of the higher 8 bit timer when channel 1 is in the 8 bit timer mode 0 No trigger operation 1 The TEHm1 bit is set to 1 and the count operation becomes enabled The TCRm1 register count operation start in the interval timer mode in the count operation enabled state see Table...

Page 169: ...4H F01B5H TT0 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TTm 0 0 0 0 TTHm 3 0 TTHm 1 0 0 0 0 0 TTm 3 TTm 2 TTm 1 TTm 0 TTH m3 Trigger to stop operation of the higher 8 bit timer when channel 3 is in the 8 bit timer mode 0 No trigger operation 1 TEHm3 bit is cleared to 0 and the count operation is stopped TTH m1 Trigger to stop operation of the higher 8 bit timer when channe...

Page 170: ...n clears this register to 00H Figure 6 16 Format of Timer Input Select register 0 TIS0 Address F0074H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TIS0 0 0 0 0 0 TIS02 TIS01 TIS00 TIS02 TIS01 TIS00 Selection of timer input used with channel 1 0 0 0 Input signal of timer input pin TI01 0 0 1 0 1 0 0 1 1 1 0 0 Low speed on chip oscillator clock fIL Other than above Setting prohibited Caution High leve...

Page 171: ... with a 1 bit or 8 bit memory manipulation instruction with TOEmL Reset signal generation clears this register to 0000H Figure 6 17 Format of Timer Output Enable register m TOEm Address F01BAH F01BBH TOE0 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOEm 0 0 0 0 0 0 0 0 0 0 0 0 TOE m3 TOE m2 TOE m1 TOE m0 TOE mn Timer output enable disable of channel n 0 Disable output of tim...

Page 172: ...O00 P16 TI01 TO01 INTP5 P33 TI02 TO02 SSI00 or P12 TI03 TO03 INTP4 PCLBUZ0 pin as a port function pin set the corresponding TOmn bit to 0 The TOm register can be set by a 16 bit memory manipulation instruction The lower 8 bits of the TOm register can be set with an 8 bit memory manipulation instruction with TOmL Reset signal generation clears this register to 0000H Figure 6 18 Format of Timer Outp...

Page 173: ...8 bits of the TOLm register can be set with an 8 bit memory manipulation instruction with TOLmL Reset signal generation clears this register to 0000H Figure 6 19 Format of Timer Output Level register m TOLm Address F01BCH F01BDH TOL0 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOLm 0 0 0 0 0 0 0 0 0 0 0 0 TOL m3 TOL m2 TOL m1 0 TOL mn Control of timer output level of channel...

Page 174: ... The lower 8 bits of the TOMm register can be set with an 8 bit memory manipulation instruction with TOMmL Reset signal generation clears this register to 0000H Figure 6 20 Format of Timer Output Mode register m TOMm Address F01BEH F01BFH TOM0 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOMm 0 0 0 0 0 0 0 0 0 0 0 0 TOM m3 TOM m2 TOM m1 0 TOM mn Control of timer output mode o...

Page 175: ... by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears this register to 00H Note For details see 6 5 1 2 When valid edge of input signal via the TImn pin is selected CCSmn 1 and 6 5 2 Start timing of counter Figure 6 21 Format of Noise Filter Enable Register 1 NFEN1 Address F0071H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 NFEN1 0 0 0 0 TNFEN03 TNFEN02 TNFEN01 TNFEN00 ...

Page 176: ... the timer input pin for timer input set the port mode register PMxx bit corresponding to each port to 1 At this time the port register Pxx bit may be 0 or 1 Example When using P33 TO02 TI02 SSI00 for timer input Set the PM33 bit of port mode register 3 to 1 Set the P33 bit of port register 3 to 0 or 1 The PM1 and PM3 registers can be set by a 1 bit or 8 bit memory manipulation instruction Reset s...

Page 177: ...ware trigger or the count clock of the master channel as a source clock but cannot transmit its own INTTMmn interrupt start software trigger or count clock to channels with lower channel numbers 9 A master channel cannot use INTTMmn interrupt a start software trigger or the count clock from the other higher master channel as a source clock 10 To simultaneously start channels that operate in combin...

Page 178: ... A channel that operates independent channel operation function may be between a master and a slave of channel group Furthermore the operating clock may be set separately CK01 Channel 1 Slave Channel 0 Master Channel group 1 simultaneous channel operation function The operating clock of channel group 1 may be different from that of channel group 2 Channel 2 Master Channel 3 Slave CK00 CK01 Channel...

Page 179: ...1 and CKSmn0 bits of the lower bit TMRmn register 6 For the higher 8 bits the TSHm1 TSHm3 bit is manipulated to start channel operation and the TTHm1 TTHm3 bit is manipulated to stop channel operation The channel status can be checked using the TEHm1 TEHm3 bit 7 The lower 8 bits operate according to the TMRmn register settings The following three functions support operation of the lower 8 bits Int...

Page 180: ...n 0 The count clock fTCLK is between fCLK to fCLK 215 by setting of timer clock select register m TPSm When a divided fCLK is selected however the clock selected in TPSmn register but a signal which becomes high level for one period of fCLK from its rising edge When a fCLK is selected fixed to high level Counting of timer count register mn TCRmn delayed by one period of fCLK from rising edge of th...

Page 181: ...ence Figure 6 24 Timing of fCLK and Count Clock fTCLK When CCSmn 1 Noise Filter Unused 1 Setting TSmn bit to 1 enables the timer to be started and to become wait state for valid edge of input signal via the TImn pin 2 The rise of input signal via the TImn pin is sampled by fMCK 3 The edge is detected by the rising of the sampled signal and the detection signal count clock is output Remarks1 Rising...

Page 182: ...count down operation see 6 5 3 2 Operation of event counter mode Capture mode No operation is carried out from start trigger detection TSmn 1 until count clock generation The first count clock loads 0000H to the TCRmn register and the subsequent count clock performs count up operation see 6 5 3 3 Operation of capture mode input pulse interval measurement One count mode The waiting for start trigge...

Page 183: ...s in the interval timer mode 5 When the TCRmn register counts down and its count value is 0000H INTTMmn is generated and the value of timer data register mn TDRmn is loaded to the TCRmn register and counting keeps on Figure 6 25 Operation Timing In Interval Timer Mode Caution In the first cycle operation of count clock after writing the TSmn bit an error at a maximum of one clock is generated sinc...

Page 184: ...TCRmn register value is counted down according to the count clock of the valid edge of the TImn input Figure 6 26 Operation Timing In Event Counter Mode Remark The above figure shows the timing when the noise filter is not in use By making the noise filter on state the edge detection becomes 2 fMCK cycles it sums up to 3 to 4 cycles later than the normal cycle of TImn input The error per one perio...

Page 185: ...If a clock has been input to TImn the trigger exists when capturing starts counting starts when a trigger is detected even if no edge is detected Therefore the first captured value 4 does not determine a pulse interval in the above figure 0001 just indicates two clock cycles but does not determine the pulse interval and so the user can ignore it Caution In the first cycle operation of count clock ...

Page 186: ...lue is 0000H INTTMmn is generated and the value of the TCRmn register becomes FFFFH and counting stops Figure 6 28 Operation Timing In One count Mode Remark The above figure shows the timing when the noise filter is not in use By making the noise filter on state the edge detection becomes 2 fMCK cycles it sums up to 3 to 4 cycles later than the normal cycle of TImn input The error per one period o...

Page 187: ...t the value of the TCRmn register is captured to timer data register mn TDRmn and INTTMmn is generated Figure 6 29 Operation Timing In Capture One count Mode High level Width Measurement Remark The above figure shows the timing when the noise filter is not in use By making the noise filter on state the edge detection becomes 2 fMCK cycles it sums up to 3 to 4 cycles later than the normal cycle of ...

Page 188: ...et INTTMmp reset When TOLmn 1 Negative logic output INTTMmn reset INTTMmp set When INTTMmn and INTTM0p are simultaneously generated 0 output of PWM INTTM0p reset signal takes priority and INTTMmn set signal is masked 3 While timer output is enabled TOEmn 1 INTTMmn master channel timer interrupt and INTTM0p slave channel timer interrupt are transmitted to the TOm register Writing to the TOm registe...

Page 189: ...t TOLmn 4 Set the port to output mode 2 Set TOmn 3 Set TOEmn 5 Timer operation start Write operation disabled period to TOmn Hi Z 1 The operation mode of timer output is set TOMmn bit 0 Master channel output mode 1 Slave channel output mode TOLmn bit 0 Positive logic output 1 Negative logic output 2 The timer output signal is set to the initial status by setting timer output register m TOm 3 The t...

Page 190: ... TOLm does not affect the timer operation the values can be changed during timer operation To output an expected waveform from the TOmn pin by timer operation however set the TOm TOEm TOLm and TOMm registers to the values stated in the register setting example of each operation shown by 6 7 and 6 8 When the values set to the TOEm and TOMm registers but not the TOm register are changed close to the...

Page 191: ...tting of timer output level register m TOLm is invalid when master channel output mode TOMmn 0 When the timer operation starts after setting the default level the toggle signal is generated and the output level of the TOmn pin is reversed Figure 6 32 TOmn Pin Output Status at Toggle Output TOMmn 0 Hi Z TOEmn TOmn output TOmn bit 0 Default status Low Default status Port output is enabled Toggle Tog...

Page 192: ...PWM Output TOMmp 1 Hi Z Active TOEmp Default status Set Reset Set Reset Set Port output is enabled TOmp output Active Active TOmp bit 0 Default status Low TOmp bit 1 Default status High TOmp bit 0 Default status Low TOmp bit 1 Default status High TOLmp bit 0 Active high TOLmp bit 1 Active low Remarks 1 Set The output signal of the TOmp pin changes from inactive level to active level Reset The outp...

Page 193: ...as Been Changed Contents during Timer Operation TOLm Active Set Reset Set Reset Set TOmn output Active Reset Set Reset Active Active Remarks 1 Set The output signal of the TOmn pin changes from inactive level to active level Reset The output signal of the TOmn pin changes from active level to inactive level 2 m Unit number m 0 n Channel number n 0 to 3 b Set reset timing To realize 0 100 output at...

Page 194: ...l number n 0 to 3 n 0 2 for master channel p Slave channel number n p 3 TOmn pin TOmn INTTMmp fTCLK INTTMmn Internal reset signal Internal set signal Internal reset signal TOmp pin TOmp Master channel Slave channel 1 clock delay Toggle Toggle Set Set Reset Reset has priority Reset Reset has priority TCRmp 0000 0001 0000 0001 TOmn pin TOmn INTTMmp fTCLK INTTMmn Internal reset signal Internal reset ...

Page 195: ...be written 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 After writing TO0 0 0 0 0 0 0 0 0 TO07 1 TO06 1 TO05 1 TO04 0 TO03 0 TO02 0 TO01 1 TO00 0 Writing is done only to the TOmn bit with TOEmn 0 and writing to the TOmn bit with TOEmn 1 is ignored TOmn channel output to which TOEmn 1 is set is not affected by the write operation Even if the write operation is done to the TOmn bit it is ignored and the output c...

Page 196: ...lled Figure 6 38 shows operation examples when the interval timer mode TOEmn 1 TOMmn 0 is set Figure 6 38 Operation examples of timer interrupt at count operation start and TOmn output a When MDmn0 is set to 1 TCRmn TEmn TOmn INTTMmn Count operation start b When MDmn0 is set to 0 TCRmn TEmn TOmn INTTMmn Count operation start When MDmn0 is set to 1 a timer interrupt INTTMmn is output at count opera...

Page 197: ... the noise filter is disabled the input signal is only synchronized with the operating clock fMCK for channel n When the noise filter is enabled after synchronization with the operating clock fMCK for channel n whether the signal keeps the same value for two clock cycles is detected The following shows differences in waveforms output from the noise filter between when the noise filter is enabled a...

Page 198: ... the timer input pin 1 Noise filter is disabled When bits 12 CCSmn 9 STSmn1 and 8 STSmn0 in the timer mode register mn TMRmn are 0 and then one of them is set to 1 wait for at least two cycles of the operating clock fMCK and then set the operation enable trigger bit in the timer channel start register TSm 2 Noise filter is enabled When bits 12 CCSmn 9 STSmn1 and 8 STSmn0 in the timer mode register...

Page 199: ...of TDRmn 1 2 Frequency of square wave output from TOmn Frequency of count clock Set value of TDRmn 1 2 Timer count register mn TCRmn operates as a down counter in the interval timer mode The TCRmn register loads the value of timer data register mn TDRmn at the first count clock after the channel start trigger bit TSmn TSHm1 TSHm3 of timer channel start register m TSm is set to 1 If the MDmn0 bit o...

Page 200: ...ction Operation clockNote Note When channels 1 and 3 the clock can be selected from CKm0 CKm1 CKm2 and CKm3 Figure 6 42 Example of Basic Timing of Operation as Interval Timer Square Wave Output MDmn0 1 TSmn TEmn TDRmn TCRmn TOmn INTTMmn a a 1 b 0000H a 1 a 1 b 1 b 1 b 1 Remarks 1 m Unit number m 0 n Channel number n 0 to 3 2 TSmn Bit n of timer channel start register m TSm TEmn Bit n of timer chan...

Page 201: ... Selects only software start Setting of MASTERmn bit channel 2 0 Independent channel operation function Setting of SPLITmn bit channels 1 3 0 16 bit timer mode 1 8 bit timer mode Count clock selection 0 Selects operation clock fMCK Operation clock fMCK selection 00B Selects CKm0 as operation clock of channel n 10B Selects CKm1 as operation clock of channel n 01B Selects CKm2 as operation clock of ...

Page 202: ...Registers During Operation as Interval Timer Square Wave Output 2 2 d Timer output level register m TOLm Bit n TOLm TOLmn 0 0 Cleared to 0 when TOMmn 0 master channel output mode e Timer output mode register m TOMm Bit n TOMm TOMmn 0 0 Sets master channel output mode Remark m Unit number m 0 n Channel number n 0 to 3 ...

Page 203: ...e because channel stops operating The TOmn pin outputs the TOmn set level Operation start Sets the TOEmn bit to 1 only if using TOmn output and resuming operation Sets the TSmn TSHm1 TSHm3 bit to 1 The TSmn TSHm1 TSHm3 bit automatically returns to 0 because it is a trigger bit TEmn TEHm1 TEHm3 1 and count operation starts Value of the TDRmn register is loaded to timer count register mn TCRmn at th...

Page 204: ...he value to be held is set to the port register When holding the TOmn pin output level is not necessary Setting not required The TOmn pin output level is held by port function The TAUmEN bit of the PER0 register is cleared to 0 Input clock supply for timer array unit 0 is stopped All circuits are initialized and SFR of each channel is also initialized The TOmn bit is cleared to 0 and the TOmn pin ...

Page 205: ... channel start register m TSm to 1 The TCRmn register counts down each time the valid input edge of the TImn pin has been detected When TCRmn 0000H the TCRmn register loads the value of the TDRmn register again and outputs INTTMmn After that the above operation is repeated An irregular waveform that depends on external events is output from the TOmn pin Stop the output by setting the TOEmn bit of ...

Page 206: ...Emn TImn TDRmn TCRmn 0003H 0002H 0 0000H 1 3 0 1 2 0 1 2 1 2 3 2 INTTMmn 4 events 4 events 3 events Remarks 1 m Unit number m 0 n Channel number n 0 to 3 2 TSmn Bit n of timer channel start register m TSm TEmn Bit n of timer channel enable status register m TEm TImn TImn pin input signal TCRmn Timer count register mn TCRmn TDRmn Timer data register mn TDRmn ...

Page 207: ...igger selection 000B Selects only software start Setting of MASTERmn bit channel 2 0 Independent channel operation function Setting of SPLITmn bit channels 1 3 0 16 bit timer mode 1 8 bit timer mode Count clock selection 1 Selects the TImn pin input valid edge Operation clock fMCK selection 00B Selects CKm0 as operation clock of channel n 10B Selects CKm1 as operation clock of channel n 01B Select...

Page 208: ...ontents of Registers in External Event Counter Mode 2 2 d Timer output level register m TOLm Bit n TOLm TOLmn 0 0 Cleared to 0 when TOMmn 0 master channel output mode e Timer output mode register m TOMm Bit n TOMm TOMmn 0 0 Sets master channel output mode Remark m Unit number m 0 n Channel number n 0 to 3 ...

Page 209: ...Smn bit to 1 The TSmn bit automatically returns to 0 because it is a trigger bit TEmn 1 and count operation starts Value of the TDRmn register is loaded to timer count register mn TCRmn and detection of the TImn pin input edge is awaited During operation Set value of the TDRmn register can be changed The TCRmn register can always be read The TSRmn register is not used Set values of the TMRmn regis...

Page 210: ...register is cleared to 0000H and the INTTMmn is output If the counter overflows at this time the OVF bit of timer status register mn TSRmn is set to 1 If the counter does not overflow the OVF bit is cleared After that the above operation is repeated As soon as the count value has been captured to the TDRmn register the OVF bit of the TSRmn register is updated depending on whether the counter overf...

Page 211: ...mn TEmn TImn TDRmn TCRmn 0000H c b 0000H a c d INTTMmn FFFFH b a d OVF Remarks 1 m Unit number m 0 n Channel number n 0 to 3 2 TSmn Bit n of timer channel start register m TSm TEmn Bit n of timer channel enable status register m TEm TImn TImn pin input signal TCRmn Timer count register mn TCRmn TDRmn Timer data register mn TDRmn OVF Bit 0 of timer status register mn TSRmn ...

Page 212: ... bit channel 2 0 Independent channel operation Setting of SPLITmn bit channels 1 3 0 16 bit timer mode Count clock selection 0 Selects operation clock fMCK Operation clock fMCK selection 00B Selects CKm0 as operation clock of channel n 10B Selects CKm1 as operation clock of channel n 01B Selects CKm2 as operation clock of channels 1 3 This can only be selected channels 1 and 3 11B Selects CKm3 as ...

Page 213: ...r mn TCRmn is cleared to 0000H at the count clock input When the MDmn0 bit of the TMRmn register is 1 INTTMmn is generated During operation Set values of only the CISmn1 and CISmn0 bits of the TMRmn register can be changed The TDRmn register can always be read The TCRmn register can always be read The TSRmn register can always be read Set values of the TOMmn TOLmn TOmn and TOEmn bits cannot be cha...

Page 214: ...l width is to be measured is detected later the count value is transferred to timer data register mn TDRmn and at the same time INTTMmn is output If the counter overflows at this time the OVF bit of timer status register mn TSRmn is set to 1 If the counter does not overflow the OVF bit is cleared The TCRmn register stops at the value value transferred to the TDRmn register 1 and the TImn pin start...

Page 215: ...tion Trigger selection Note For channels 1 and 3 the clock can be selected from CKm0 CKm1 CKm2 and CKm3 Figure 6 54 Example of Basic Timing of Operation as Input Signal High Low Level Width Measurement TSmn TEmn TImn TDRmn TCRmn b 0000H a c INTTMmn FFFFH b a c OVF 0000H Remarks 1 m Unit number m 0 n Channel number n 0 to 3 2 TSmn Bit n of timer channel start register m TSm TEmn Bit n of timer chan...

Page 216: ... channel operation function Setting of SPLITmn bit channels 1 3 1 16 bit timer mode Count clock selection 0 Selects operation clock fMCK Operation clock fMCK selection 00B Selects CKm0 as operation clock of channel n 10B Selects CKm1 as operation clock of channel n 01B Selects CKm2 as operation clock of channels 1 3 This can only be selected channels 1 and 3 11B Selects CKm3 as operation clock of ...

Page 217: ...tion wait status is set Detects the TImn pin input count start valid edge Clears timer count register mn TCRmn to 0000H and starts counting up During operation Set value of the TDRmn register can be changed The TCRmn register can always be read The TSRmn register is not used Set values of the TMRmn register TOMmn TOLmn TOmn and TOEmn bits cannot be changed When the TImn pin start edge is detected ...

Page 218: ...EHm3 bits are set to 1 and the TImn pin input valid edge detection wait status is set Timer count register mn TCRmn starts operating upon TImn pin input valid edge detection and loads the value of timer data register mn TDRmn The TCRmn register counts down from the value of the TDRmn register it has loaded in synchronization with the count clock When TCRmn 0000H it outputs INTTMmn and stops counti...

Page 219: ...elay Counter TEmn TDRmn TCRmn INTTMmn a b 0000H a 1 b 1 FFFFH TImn TSmn Remarks 1 m Unit number m 0 n Channel number n 0 to 3 2 TSmn Bit n of timer channel start register m TSm TEmn Bit n of timer channel enable status register m TEm TImn TImn pin input signal TCRmn Timer count register mn TCRmn TDRmn Timer data register mn TDRmn ...

Page 220: ... the TImn pin input valid edge Setting of MASTERmn bit channel 2 0 Independent channel operation function Setting of SPLITmn bit channels 1 3 0 16 bit timer mode 1 8 bit timer mode Count clock selection 0 Selects operation clock fMCK Operation clock fMCK selection 00B Selects CKm0 as operation clock of channel n 10B Selects CKm1 as operation clock of channel n 01B Selects CKm2 as operation clock o...

Page 221: ...f Set Contents of Registers to Delay Counter 2 2 d Timer output level register m TOLm Bit n TOLm TOLmn 0 0 Cleared to 0 when TOMmn 0 master channel output mode e Timer output mode register m TOMm Bit n TOMm TOMmn 0 0 Sets master channel output mode Remark m Unit number m 0 n Channel number n 0 to 3 ...

Page 222: ...The TSmn bit automatically returns to 0 because it is a trigger bit TEmn 1 and the start trigger detection the valid edge of the TImn pin input is detected or the TSmn bit is set to 1 wait status is set The counter starts counting down by the next start trigger detection Detects the TImn pin input valid edge Sets the TSmn bit to 1 by the software Value of the TDRmn register is loaded to the timer ...

Page 223: ...es in the one count mode and counts the pulse width The TCRmp register of the slave channel starts operation using INTTMmn of the master channel as a start trigger and loads the value of the TDRmp register The TCRmp register counts down from the value of The TDRmp register it has loaded in synchronization with the count value When count value 0000H it outputs INTTMmp and stops counting until the n...

Page 224: ...troller Operation clock CKm0 CKm1 TOmp pin Output controller Master channel one count mode Slave channel one count mode Edge detection Timer counter register mn TCRmn Timer data register mn TDRmn Timer counter register mp TCRmp Timer data register mp TDRmp TImn pin TNFENmn NFEN1 register Noise filter Clock selection Trigger selection Clock selection Trigger selection Remark m Unit number m 0 n Mas...

Page 225: ...l Slave channel a 2 b a 2 FFFFH FFFFH TImn TSmn Remarks 1 m Unit number m 0 n Master channel number n 0 2 p Slave channel number n 0 p 1 2 3 n 2 p 3 2 TSmn TSmp Bit n p of timer channel start register m TSm TEmn TEmp Bit n p of timer channel enable status register m TEm TImn TImp TImn and TImp pins input signal TCRmn TCRmp Timer count registers mn mp TCRmn TCRmp TDRmn TDRmp Timer data registers mn...

Page 226: ...tects both edges 11B Setting prohibited Start trigger selection 001B Selects the TImn pin input valid edge Setting of the MASTERmn bit channel 2 1 Master channel Count clock selection 0 Selects operation clock fMCK Operation clock fMCK selection 00B Selects CKm0 as operation clock of channels n 10B Selects CKm1 as operation clock of channels n b Timer output register m TOm Bit n TOm TOmn 0 0 Outpu...

Page 227: ...t channels 1 3 1 16 bit timer mode Count clock selection 0 Selects operation clock fMCK Operation clock fMCK selection 00B Selects CKm0 as operation clock of channel p 10B Selects CKm1 as operation clock of channel p Make the same setting as master channel b Timer output register m TOm Bit p TOm TOmp 1 0 0 Outputs 0 from TOmp 1 Outputs 1 from TOmp c Timer output enable register m TOEm Bit p TOEm T...

Page 228: ...1 to 1 Sets timer mode register mn mp TMRmn TMRmp of two channels to be used determines operation mode of channels An output delay is set to timer data register mn TDRmn of the master channel and a pulse width is set to the TDRmp register of the slave channel Channel stops operating Clock is supplied and some power is consumed Sets slave channel The TOMmp bit of timer output mode register m TOMm i...

Page 229: ...nter starts counting down When the count value reaches TCRmn 0000H the INTTMmn output is generated and the counter stops until the next valid edge is input to the TImn pin The slave channel triggered by INTTMmn of the master channel loads the value of the TDRmp register to the TCRmp register and the counter starts counting down The output level of TOmp becomes active one count clock after generati...

Page 230: ...period until the master channel counts down to 0000H is the PWM output TOmp cycle The slave channel operates in one count mode By using INTTMmn from the master channel as a start trigger the TCRmp register loads the value of the TDRmp register and the counter counts down to 0000H When the counter reaches 0000H it outputs INTTMmp and waits until the next start trigger INTTMmn from the master channe...

Page 231: ...Km0 CKm1 TSmn Interrupt signal INTTMmp Interrupt controller Clock selection Trigger selection Operation clock CKm0 CKm1 TOmp pin Output controller Master channel interval timer mode Slave channel one count mode Timer counter register mn TCRmn Timer data register mn TDRmn Timer counter register mp TCRmp Timer data register mp TDRmp Remark m Unit number m 0 n Master channel number n 0 2 p Slave chan...

Page 232: ...0000H c d Master channel Slave channel a 1 a 1 b 1 FFFFH FFFFH Remark 1 m Unit number m 0 n Master channel number n 0 2 p Slave channel number n 0 p 1 2 3 n 2 p 3 2 TSmn TSmp Bit n p of timer channel start register m TSm TEmn TEmp Bit n p of timer channel enable status register m TEm TCRmn TCRmp Timer count registers mn mp TCRmn TCRmp TDRmn TDRmp Timer data registers mn mp TDRmn TDRmp TOmn TOmp TO...

Page 233: ...ause these are not used Start trigger selection 000B Selects only software start Setting of the MASTERmn bit channel 2 1 Master channel Count clock selection 0 Selects operation clock fMCK Operation clock fMCK selection 00B Selects CKm0 as operation clock of channel n 10B Selects CKm1 as operation clock of channel n b Timer output register m TOm Bit n TOm TOmn 0 0 Outputs 0 from TOmn c Timer outpu...

Page 234: ...s 1 3 0 16 bit timer mode Count clock selection 0 Selects operation clock fMCK Operation clock fMCK selection 00B Selects CKm0 as operation clock of channel p 10B Selects CKm1 as operation clock of channel p Make the same setting as master channel b Timer output register m TOm Bit p TOm TOmp 1 0 0 Outputs 0 from TOmp 1 Outputs 1 from TOmp c Timer output enable register m TOEm Bit p TOEm TOEmp 1 0 ...

Page 235: ...Rmp of two channels to be used determines operation mode of channels An interval period value is set to timer data register mn TDRmn of the master channel and a duty factor is set to the TDRmp register of the slave channel Channel stops operating Clock is supplied and some power is consumed Sets slave channel The TOMmp bit of timer output mode register m TOMm is set to 1 slave channel output mode ...

Page 236: ...alue of the TDRmp register is loaded to the TCRmp register triggered by INTTMmn of the master channel and the counter starts counting down The output level of TOmp becomes active one count clock after generation of the INTTMmn output from the master channel It becomes inactive when TCRmp 0000H and the counting operation is stopped After that the above operation is repeated Operation stop The TTmn ...

Page 237: ...el and inactive when TCRmp 0000H In the same way as the TCRmp register of the slave channel 1 the TCRmq register of the slave channel 2 operates in one count mode counts the duty factor and outputs a PWM waveform from the TOmq pin The TCRmq register loads the value of the TDRmq register using INTTMmn of the master channel as a start trigger and starts counting down When TCRmq 0000H the TCRmq regis...

Page 238: ...Omp pin Output controller Master channel interval timer mode Slave channel 1 one count mode Interrupt signal INTTMmq Interrupt controller Clock selection Trigger selection Operation clock CKm0 CKm1 TOmq pin Output controller Slave channel 2 one count mode Timer counter register mn TCRmn Timer data register mn TDRmn Timer counter register mp TCRmp Timer data register mp TDRmp Timer counter register...

Page 239: ... Multiple PWM Output Function Output two types of PWMs TSmn TEmn TDRmn TCRmn TOmn INTTMmn a b 0000H TSmp TEmp TDRmp TCRmp TOmp INTTMmp c c d 0000H c d Master channel Slave channel 1 a 1 a 1 b 1 FFFFH FFFFH TSmq TEmq TDRmq TCRmq TOmq INTTMmq e f 0000H e f Slave channel 2 a 1 a 1 b 1 FFFFH e f d Remarks are listed on the next page ...

Page 240: ...umber 2 n p q 3 Where p and q are integers greater than n 2 TSmn TSmp TSmq Bit n p q of timer channel start register m TSm TEmn TEmp TEmq Bit n p q of timer channel enable status register m TEm TCRmn TCRmp TCRmq Timer count registers mn mp mq TCRmn TCRmp TCRmq TDRmn TDRmp TDRmq Timer data registers mn mp mq TDRmn TDRmp TDRmq TOmn TOmp TOmq TOmn TOmp and TOmq pins output signal ...

Page 241: ...ese are not used Start trigger selection 000B Selects only software start Setting of MASTERmn bit channel 2 1 Master channel Count clock selection 0 Selects operation clock fMCK Operation clock fMCK selection 00B Selects CKm0 as operation clock of channel n 10B Selects CKm1 as operation clock of channel n b Timer output register m TOm Bit n TOm TOmn 0 0 Outputs 0 from TOmn c Timer output enable re...

Page 242: ...tting of SPLITmp SPLITmq bits channels 1 3 1 16 bit timer mode Count clock selection 0 Selects operation clock fMCK Operation clock fMCK selection 00B Selects CKm0 as operation clock of channel p q 10B Selects CKm1 as operation clock of channel p q Make the same setting as master channel b Timer output register m TOm Bit q Bit p TOm TOmq 1 0 TOmp 1 0 0 Outputs 0 from TOmp or TOmq 1 Outputs 1 from ...

Page 243: ...ion mode of channels An interval period value is set to timer data register mn TDRmn of the master channel and a duty factor is set to the TDRmp and TDRmq registers of the slave channels Channel stops operating Clock is supplied and some power is consumed Sets slave channels The TOMmp and TOMmq bits of timer output mode register m TOMm are set to 1 slave channel output mode Sets the TOLmp and TOLm...

Page 244: ...master channel It becomes inactive when TCRmp 0000H and the counting operation is stopped At the slave channel 2 the values of the TDRmq register are transferred to TCRmq register triggered by INTTMmn of the master channel and the counter starts counting down The output levels of TOmq become active one count clock after generation of the INTTMmn output from the master channel It becomes inactive w...

Page 245: ...er output and other alternate functions In this case outputs of the other alternate functions must be set in initial status Using TO03 output assigned to the P12 So that the alternated PCLBUZ0 output becomes 0 not only set the port mode register the PM12 bit and the port register the P12 bit to 0 but also use the bit 7 of the clock output select register 0 CKS0 with the same setting as the initial...

Page 246: ...r carrier output during remote controlled transmission and clock output for supply to peripheral ICs Buzzer output is a function to output a square wave of buzzer frequency One pin can be used to output a clock or buzzer sound Two output pins PCLBUZ0 and PCLBUZ1 are available The PCLBUZn pin outputs a clock selected by clock output select register n CKSn Figure 7 1 shows the block diagram of clock...

Page 247: ...ck buzzer controller Prescaler Internal bus 0 Clock output select register 0 CKS0 CCS02 CCS01 CCS00 Output latch P15 PM15 PM12 Output latch P12 PCLOE1 0 0 0 0 Clock output select register 1 CKS1 CCS12 CCS11 CCS10 Internal bus Clock buzzer controller PCLOE1 fMAIN to fMAIN 24 fMAIN 211 to fMAIN 213 fMAIN 211 to fMAIN 213 fMAIN to fMAIN 24 Selector Selector Note For output frequencies available from ...

Page 248: ...rs Clock output select registers n CKSn Port mode register 1 PM1 Port register 1 P1 7 3 Registers Controlling Clock Output Buzzer Output Controller 7 3 1 Clock output select registers n CKSn These registers set output enable disable for clock output or for the buzzer frequency output pin PCLBUZn and set the output clock Select the clock to be output from the PCLBUZn pin by using the CKSn register ...

Page 249: ...e Setting prohibitedNote 0 0 1 fMAIN 2 2 5 MHz 5 MHz Setting prohibitedNote Setting prohibitedNote 0 1 0 fMAIN 22 1 25 MHz 2 5 MHz 5 MHz 8 MHzNote 0 1 1 fMAIN 23 625 kHz 1 25 MHz 2 5 MHz 4 MHz 1 0 0 fMAIN 24 312 5 kHz 625 kHz 1 25 MHz 2 MHz 1 0 1 fMAIN 211 2 44 kHz 4 88 kHz 9 76 kHz 15 63 kHz 1 1 0 fMAIN 212 1 22 kHz 2 44 kHz 4 88 kHz 7 81 kHz 1 1 1 fMAIN 213 610 Hz 1 22 kHz 2 44 kHz 3 91 kHz Note...

Page 250: ...t mode register PMxx port register Pxx For details see 4 3 1 Port mode registers PMxx and 4 3 2 Port registers Pxx Specifically using a port pin with a multiplexed clock or buzzer output function e g P12 TI03 TO03 INTP4 PCLBUZ0 P15 PCLBUZ1 for clock or buzzer output requires setting the corresponding bits in the port mode register PMxx and port register Pxx to 0 Example When P12 TI03 TO03 INTP4 PC...

Page 251: ...ock output select register CKSn of the PCLBUZn pin output in disabled status 3 Set bit 7 PCLOEn of the CKSn register to 1 to enable clock buzzer output Remarks 1 The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or disabling clock output PCLOEn bit is switched At this time pulses with a narrow width are not output Figure 7 3 shows enabling o...

Page 252: ...reset signal is generated Program loop is detected in the following cases If the watchdog timer counter overflows If a 1 bit manipulation instruction is executed on the watchdog timer enable register WDTE If data other than ACH is written to the WDTE register If data is written to the WDTE register during a window close period When a reset occurs due to the watchdog timer bit 4 WDTRF of the reset ...

Page 253: ...NDOW1 WINDOW0 Controlling counter operation of watchdog timer Bit 4 WDTON Overflow time of watchdog timer Bits 3 to 1 WDCS2 to WDCS0 Controlling counter operation of watchdog timer in HALT STOP mode Bit 0 WDSTBYON Remark For the option byte see CHAPTER 22 OPTION BYTE Figure 8 1 Block Diagram of Watchdog Timer fIL WDTON of option byte 000C0H WDTINT of option byte 000C0H Interval time interrupt WDCS...

Page 254: ... Register WDTE 0 1 2 3 4 5 6 7 Symbol WDTE Address FFFABH After reset 9AH 1AHNote R W Note The WDTE register reset value differs depending on the WDTON bit setting value of the option byte 000C0H To operate watchdog timer set the WDTON bit to 1 WDTON Bit Setting Value WDTE Register Reset Value 0 watchdog timer count operation disabled 1AH 1 watchdog timer count operation enabled 9AH Cautions 1 If ...

Page 255: ...atchdog timer starts counting and before the overflow time set by the option byte the watchdog timer is cleared and starts counting again 4 After that write the WDTE register the second time or later after a reset release during the window open period If the WDTE register is written during a window close period an internal reset signal is generated 5 If the overflow time expires without ACH writte...

Page 256: ...ilization time causing a reset Consequently set the overflow time in consideration of the oscillation stabilization time when operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP mode release by an interval interrupt 8 4 2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 WDCS2 to WDCS0 of the opt...

Page 257: ... ACH is written to the WDTE register during the window close period an abnormality is detected and an internal reset signal is generated Example If the window open period is 50 Window close period 50 Window open period 50 Counting starts Overflow time Counting starts again when ACH is written to WDTE Internal reset signal is generated if ACH is written to WDTE Caution When data is written to the W...

Page 258: ... regardless of the values of the WINDOW1 and WINDOW0 bits Remark If the overflow time is set to 29 fIL the window close time and open time are as follows Setting of Window Open Period 50 75 100 Window close time 0 to 20 08 ms 0 to 10 04 ms None Window open time 20 08 to 29 68 ms 10 04 to 29 68 ms 0 to 29 68 ms When window open period is 50 Overflow time 29 fIL MAX 29 17 25 kHz 29 68 ms Window clos...

Page 259: ...r releasing the STOP mode the CPU starts operating after the oscillation stabilization time has elapsed Therefore if the period between the STOP mode release and the watchdog timer overflow is short an overflow occurs during the oscillation stabilization time causing a reset Consequently set the overflow time in consideration of the oscillation stabilization time when operating with the X1 oscilla...

Page 260: ... inputs ANI0 to ANI7 ANI16 12 bit or 8 bit resolution can be selected by the ADTYP bit of the A D converter mode register 2 ADM2 The A D converter has the following function 12 bit or 8 bit resolution A D conversion 12 bit or 8 bit resolution A D conversion is carried out repeatedly for one analog input channel selected from ANI0 to ANI7 and ANI16 Each time an A D conversion operation ends an inte...

Page 261: ...ecify the hardware trigger wait mode Channel selection mode Select mode A D conversion is performed on the analog input of one selected channel Scan mode A D conversion is performed on the analog input of four channels in order Four consecutive channels can be selected from ANI0 to ANI7 as analog input channels Conversion operation mode One shot conversion mode A D conversion is performed on the s...

Page 262: ...r SAR Temperature sensor Internal reference voltage 1 45 V Analog input channel specification register ADS A D converter mode register 2 ADM2 A D converter mode register 1 ADM1 A D converter mode register 0 ADM0 A D conversion result register ADCR ADCRH AV REFM ANI1 P21 ADREFP 1 ADREFP 0 ADREFPM ADRCK AWC ADTYP ADTMD 1 ADTMD 0 ADSCM ADTRS1ADTRS0 ADTES1ADTES0 ANI0 AV REFP P20 ANI1 AV REFM P21 ANI3 ...

Page 263: ...cessive approximation register SAR is set If the analog input voltage is less than the reference voltage 1 2 AVREF the MSB bit of the SAR is reset After that bit 10 of the SAR register is automatically set and the next comparison is made The voltage tap of the comparison voltage generator is selected by the value of bit 11 to which the result has been already set Bit 11 0 1 4 AVREF Bit 11 1 3 4 AV...

Page 264: ...on register to this register each time A D conversion is completed and the ADCRH register stores the higher 8 bits of the A D conversion result 8 Controller This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal as well as starting and stopping of the conversion operation When A D conversion has been completed this controller generates INT...

Page 265: ...ter 1 ADM1 A D converter mode register 2 ADM2 12 bit A D conversion result register ADCR 8 bit A D conversion result register ADCRH Analog input channel specification register ADS Conversion result comparison upper limit setting register ADUL Conversion result comparison lower limit setting register ADLL A D test register ADTES A D port configuration register ADPC Port mode control register 1 PMC1...

Page 266: ...r cannot be written The A D converter is in the reset status 1 Enables input clock supply SFR used by the A D converter can be read written Cautions 1 When setting the A D converter be sure to set the following registers first while the ADCEN bit is set to 1 If ADCEN 0 the values of the A D converter control registers are cleared to their initial values and writing to them is ignored except for po...

Page 267: ... A D conversion see Table 9 3 A D Conversion Time Selection 2 While in the software trigger mode or hardware trigger no wait mode the operation of the A D voltage comparator is controlled by the ADCS and ADCE bits and it takes stabilization wait status from the start of operation for the operation to stabilize Therefore when the ADCS bit is set to 1 after stabilization wait status or more has elap...

Page 268: ...ne shot conversion mode When 0 is written to ADCS The bit is automatically cleared to 0 when conversion ends on the specified four channels Hardware trigger no wait mode Select mode Sequential conversion mode When 0 is written to ADCS One shot conversion mode When 0 is written to ADCS Scan mode Sequential conversion mode When 0 is written to ADCS One shot conversion mode When 0 is written to ADCS ...

Page 269: ...annel 0 5 s If a test mode setting ADTES1 bit of ADTES register 1 is selected 0 5 s If a standard channel is selected as the analog input channel 2 s If a temperature sensor output internal reference voltage output are selected as the analog input channel ADISS bit of ADS register 1 2 s 2 For the second and subsequent conversion in sequential conversion mode and for conversion of the channel speci...

Page 270: ...Setting prohibited Setting prohibited Setting prohibited Setting prohibited 66 s 0 0 1 fCLK 16 1056 fCLK 66 s 33 s 0 1 0 fCLK 8 528 fCLK 66 sNote 33 s 16 5 s 0 1 1 fCLK 6 396 fCLK 49 5 sNote 24 75 s 12 375 s 1 0 0 fCLK 5 330 fCLK 41 25 sNote 20 625 s 10 3125 s 1 0 1 fCLK 4 264 fCLK 66 sNote 33 sNote 16 5 s 8 25 s 1 1 0 fCLK 2 132 fCLK 33 sNote 16 5 sNote 8 25 s 4 125 s 1 1 1 fCLK 1 66 fCLK 66 sNot...

Page 271: ...bited Setting prohibited Setting prohibited 67 8125 s 0 0 1 fCLK 16 1114 fCLK 69 625 s 34 8125 s 0 1 0 fCLK 8 586 fCLK 73 25 s Note 2 36 625 s 18 3125 s 0 1 1 fCLK 6 454 fCLK 56 75 s Note 2 28 375 s 14 1875 s 1 0 0 fCLK 5 388 fCLK 48 5 s Note 2 24 25 s 12 125 s 1 0 1 fCLK 4 322 fCLK 80 5 s Note 2 40 25 s Note 2 20 125 s 10 0625 s 1 1 0 fCLK 2 190 fCLK 47 5 s Note 2 23 75 s Note 2 11 875 s 5 9375 s...

Page 272: ... fCLK Setting prohibited Setting prohibited Setting prohibited Setting prohibited 53 s 0 0 1 fCLK 16 848 fCLK 53 s 26 5 s 0 1 0 fCLK 8 424 fCLK 53 sNote 26 5 s 13 25 s 0 1 1 fCLK 6 318 fCLK 39 75 s Note 19 875 s 9 9375 s 1 0 0 fCLK 5 265 fCLK 33 125 s Note 16 5625 s 8 28125 s 1 0 1 fCLK 4 212 fCLK 53 sNote 26 5 s Note 13 25 s 6 625 s 1 1 0 fCLK 2 106 fCLK 26 5 s Note 13 25 s Note 6 625 s 3 3125 s ...

Page 273: ...2 fCLK 43 fCLK 43 s Note 2 10 75 s Note 2 5 375 s Note 2 2 6875 s Note 2 Setting prohibited 0 0 0 1 Normal 2 fCLK 32 58 fCLK 53 fAD number of sampling clock 23 fAD 1754 fCLK Setting prohibited Setting prohibited Setting prohibited Setting prohibited 54 8125 s 0 0 1 fCLK 16 906 fCLK 56 625 s 28 3125 s 0 1 0 fCLK 8 482 fCLK 60 25 s Note 2 30 125 s 15 0625 s 0 1 1 fCLK 6 376 fCLK 47 s Note 2 23 5 s 1...

Page 274: ...h that the following conditions are satisfied fAD must be in the range from 1 to 16 MHz When the setting of the ADISS bit of the ADS register is 1 selecting the temperature sensor or internal reference voltage output the following condition applies Setting LV0 to 0 is prohibited Only setting LV0 to 1 is permitted Remark fCLK CPU peripheral hardware clock frequency ...

Page 275: ...019 Figure 9 5 A D Converter Sampling and A D Conversion Timing Example for Software Trigger Mode ADCS Conversion time Conversion time Sampling timing INTAD ADCS 1 or ADS rewrite Successive conversion SAR clear Sampling SAR clear Sampling Transfer to ADCR INTAD generation ...

Page 276: ...er no wait mode 1 1 Hardware trigger wait mode ADSCM Specification of the A D conversion mode 0 Sequential conversion mode 1 One shot conversion mode ADTRS1 ADTRS0 Selection of the hardware trigger signal 0 0 End of timer channel 01 count or capture interrupt signal INTTM01 0 1 Event signal selected by ELC Other than above Setting prohibited Cautions 1 Only rewrite the value of the ADM1 register w...

Page 277: ... to 1 and 0 A 10 s When ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1 A 1 s The stabilization wait time indicated by 5 is required when the value of the ADCE bit is changed to 1 If a high accuracy channel is selected as the analog input channel 0 5 s If a test mode setting ADTES1 bit of ADTES register 1 is selected 0 5 s If a standard channel is selected as the analog input channel 2 s If ...

Page 278: ...NOOZE mode function can only be specified when the high speed on chip oscillator clock is selected for the CPU peripheral hardware clock fCLK If any other clock is selected specifying this mode is prohibited Using the SNOOZE mode function in the software trigger mode or hardware trigger no wait mode is prohibited Using the SNOOZE mode function in the sequential conversion mode is prohibited When u...

Page 279: ...000000B ADCR register value A D conversion result INTAD is generated when ADRCK 1 INTAD is generated when ADRCK 0 INTAD is generated when ADRCK 1 ADUL register setting ADLL register setting AREA 2 ADCR ADLL AREA 1 ADLL ADCR ADUL AREA 3 ADUL ADCR Remark If INTAD does not occur the A D conversion result is not stored in the ADCR or ADCRH register ...

Page 280: ...memory manipulation instruction Reset signal generation clears this register to 0000H Note If the A D conversion result is outside the range specified by using the A D conversion comparison function the value specified by the ADRCK bit of the ADM2 register and ADUL ADLL registers see Figure 9 8 the result is not stored Figure 9 9 Format of 12 bit A D Conversion Result Register ADCR Symbol Address ...

Page 281: ...Figure 9 8 the result is not stored Figure 9 10 Format of 8 bit A D Conversion Result Register ADCRH Symbol Address FFF1FHNote After reset 00H R FFF1FH FFF1EH 0 0 0 0 ADCRH ADCRH Note The ADCRH data the lower 4 bits of FFF1FH the higher 4 bits of FFF1EH is to be read as a FFF1FH address Cautions 1 When writing to the A D converter mode register 0 ADM0 analog input channel specification register AD...

Page 282: ... Select mode ADMD 0 ADISS ADS4 ADS2 ADS1 ADS0 Analog input channel Input source 0 0 0 0 0 ANI0 P20 ANI0 AVREFP pin 0 0 0 0 1 ANI1 P21 ANI1 AVREFM pin 0 0 0 1 0 ANI2 P22 ANI2 pin 0 0 0 1 1 ANI3 P23 ANI3 pin 0 0 1 0 0 ANI4 P24 ANI4 pinNote 1 0 0 1 0 1 ANI5 P25 ANI5 pinNote 1 0 0 1 1 0 ANI6 P26 ANI6 pinNote 1 0 0 1 1 1 ANI7 P27 ANI7 pin 0 1 0 0 0 ANI16 P10 ANI16 pinNote 2 1 0 0 0 0 Temperature sensor...

Page 283: ...PC as digital I O by the ADS register 4 Rewrite the value of the ADISS bit while conversion is stopped ADCS 0 ADCE 0 5 If using AVREFP as the side reference voltage of the A D converter do not select ANI0 as an A D conversion channel 6 If using AVREFM as the side reference voltage of the A D converter do not select ANI1 as an A D conversion channel 7 If ADISS is set to 1 the internal reference vol...

Page 284: ...mit Setting Register ADUL Address F0011H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 ADUL ADUL7 ADUL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADUL0 9 3 9 Conversion result comparison lower limit setting register ADLL This register is used to specify the setting for checking the lower limit of the A D conversion results The A D conversion results and ADLL register value are compared and interrupt signal INTAD...

Page 285: ...ss F0013H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADTES 0 0 0 0 0 0 ADTES1 ADTES0 ADTES1 ADTES0 A D conversion target 0 0 ANIxx temperature sensor output voltageNote internal reference voltage output 1 45 V Note This is specified using the analog input channel specification register ADS 1 0 The side reference voltage selected by the ADREFM bit of the ADM2 register 1 1 The side reference voltage...

Page 286: ...ster ADPC For details see 4 3 1 Port mode registers PMxx 4 3 4 Port mode control register 1 PMC1 24 pin products only and 4 3 5 A D port configuration register ADPC When using the ANI0 to ANI7 pins for analog input of the A D converter set the port mode register PMxx bit corresponding to each port to 1 and select analog input through the A D port configuration register ADPC When using the ANI16 pi...

Page 287: ...ated as follows Sampled voltage Voltage tap Bit 10 1 Sampled voltage Voltage tap Bit 10 0 6 Comparison is continued in this way up to bit 0 of the SAR register 7 Upon completion of the comparison of 12 bits an effective digital result value remains in the SAR register and the result value is transferred to the A D conversion result register ADCR ADCRH and then latchedNote 1 At the same time the A ...

Page 288: ...ly cleared to 0 after completion of A D conversion In sequential conversion mode A D conversion operations proceed continuously until the software clears bit 7 ADCS of the A D converter mode register 0 ADM0 to 0 Writing to the analog input channel specification register ADS during A D conversion interrupts the current conversion after which A D conversion of the analog input specified by the ADS r...

Page 289: ...eses VAIN Analog input voltage AVREF AVREF pin voltage ADCR A D conversion result register ADCR value Figure 9 16 shows the relationship between the analog input voltage and the A D conversion result Figure 9 16 Relationship Between Analog Input Voltage and A D Conversion Result 4095 4094 4093 3 2 1 0 0FFFH 0FFEH 0FFDH 0003H 0002H 0001H 0000H A D conversion result SAR ADCR 1 8192 1 4096 3 8192 2 4...

Page 290: ...erted data is discarded 6 Even if a hardware trigger is input during conversion operation A D conversion does not start 7 When ADCS is cleared to 0 during conversion operation the current A D conversion is interrupted and the system enters the A D conversion standby status 8 When ADCE is cleared to 0 while in the A D conversion standby status the A D converter enters the stop status When ADCE 0 sp...

Page 291: ... the current A D conversion is interrupted and the system enters the A D conversion standby status 8 When ADCE is cleared to 0 while in the A D conversion standby status the A D converter enters the stop status When ADCE 0 specifying 1 for ADCS is ignored and A D conversion does not start In addition A D conversion does not start even if a hardware trigger is input while in the A D conversion stan...

Page 292: ...7 When ADCS is cleared to 0 during conversion operation the current A D conversion is interrupted and the system enters the A D conversion standby status 8 When ADCE is cleared to 0 while in the A D conversion standby status the A D converter enters the stop status When ADCE 0 specifying 1 for ADCS is ignored and A D conversion does not start Note If a high accuracy channel is selected as the anal...

Page 293: ...nterrupted and the system enters the A D conversion standby status 8 When ADCE is cleared to 0 while in the A D conversion standby status the A D converter enters the stop status When ADCE 0 specifying 1 for ADCS is ignored and A D conversion does not start In addition A D conversion does not start even if a hardware trigger is input while in the A D conversion standby status Note If a high accura...

Page 294: ...upted and conversion restarts The partially converted data is discarded 8 When ADCS is cleared to 0 during conversion operation the current A D conversion is interrupted and the system enters the A D conversion standby status However the A D converter does not stop in this status 9 When ADCE is cleared to 0 while in the A D conversion standby status the A D converter enters the stop status When AD...

Page 295: ...d conversion restarts The partially converted data is discarded 9 When ADCS is cleared to 0 during conversion operation the current A D conversion is interrupted and the system enters the A D conversion standby status However the A D converter does not stop in this status 10 When ADCE is cleared to 0 while in the A D conversion standby status the A D converter enters the stop status When ADCS 0 in...

Page 296: ...red to 0 during conversion operation the current A D conversion is interrupted and the system enters the A D conversion standby status However the A D converter does not stop in this status 9 When ADCE is cleared to 0 while in the A D conversion standby status the A D converter enters the stop status When ADCE 0 specifying 1 for ADCS is ignored and A D conversion does not start Note If a high accu...

Page 297: ...ded 9 When ADCS is cleared to 0 during conversion operation the current A D conversion is interrupted and the system enters the A D conversion standby status However the A D converter does not stop in this status 10 When ADCE is cleared to 0 while in the A D conversion standby status the A D converter enters the stop status When ADCS 0 inputting a hardware trigger is ignored and A D conversion doe...

Page 298: ...discarded 6 When ADCS is overwritten with 1 during conversion operation the current A D conversion is interrupted and conversion restarts The partially converted data is discarded 7 When ADCS is cleared to 0 during conversion operation the current A D conversion is interrupted the system enters the hardware trigger standby status and the A D converter enters the stop status When ADCE 0 inputting a...

Page 299: ...terrupted and conversion restarts The partially converted data is initialized 8 When ADCS is cleared to 0 during conversion operation the current A D conversion is interrupted the system enters the hardware trigger standby status and the A D converter enters the stop status When ADCE 0 inputting a hardware trigger is ignored and A D conversion does not start Figure 9 26 Example of Hardware Trigger...

Page 300: ...t the first channel The partially converted data is discarded 7 When ADCS is cleared to 0 during conversion operation the current A D conversion is interrupted the system enters the hardware trigger standby status and the A D converter enters the stop status When ADCE 0 inputting a hardware trigger is ignored and A D conversion does not start Figure 9 27 Example of Hardware Trigger Wait Mode Scan ...

Page 301: ... data is discarded 8 When ADCS is cleared to 0 during conversion operation the current A D conversion is interrupted the system enters the hardware trigger standby status and the A D converter enters the stop status When ADCE 0 inputting a hardware trigger is ignored and A D conversion does not start Figure 9 28 Example of Hardware Trigger Wait Mode Scan Mode One Shot Conversion Mode Operation Tim...

Page 302: ...RL78 G1P CHAPTER 9 A D CONVERTER R01UH0895EJ0100 Rev 1 00 283 Nov 29 2019 9 7 A D Converter Setup Flowchart The A D converter setup flowchart in each operation mode is described below ...

Page 303: ...ct the analog input channels ADCE bit setting The ADCE bit of the ADM0 register is set 1 and the system enters the A D conversion standby status Reference voltage stabilization wait time count B If a high accuracy channel is selected as the analog input channel B 0 5 s If a standard channel is selected as the analog input channel B 2 s Start of A D conversion End of A D conversion The A D conversi...

Page 304: ... limit and lower limit A D conversion result comparison values ADS register ADS4 ADS2 to ADS0 bits These are used to select the analog input channels The ADCE bit of the ADM0 register is set 1 and the system enters the A D conversion standby status If a high accuracy channel is selected as the analog input channel B 0 5 s If a standard channel is selected as the analog input channel B 2 s The A D ...

Page 305: ...t channels ADCE bit setting The ADCE bit of the ADM0 register is set 1 and the system enters the A D conversion standby status Hardware trigger generation The system automatically counts up to the stabilization wait time of A D conversion Start of A D conversion After counting up to the reference voltage stabilization wait time ends A D conversion starts End of A D conversion The A D conversion op...

Page 306: ...zation wait time count B Start of A D conversion ADCS bit setting ADCS bit setting End of A D conversion The ADCE bit of the ADM0 register is set 1 and the system enters the A D conversion standby status If a temperature sensor output voltage or internal reference output ADISS bit of ADS register 1 is selected as the analog input channel B 2 µs The A D conversion end interrupt INTAD will be genera...

Page 307: ... register setting ADM2 register setting ADUL ADLL register setting ADS register setting ADTES register setting The order of the settings is irrelevant If a test mode is selected ADTES1 bit of ADTES register 1 as the analog input channel B 0 5 s Reference voltage stabilization wait time count B Start of A D conversion End of A D conversion Storage of conversion results in the ADCR and ADCRH registe...

Page 308: ...internal signal High speed on chip oscillator clock A D converter Clock generator A D conversion end interrupt request signalNote 1 INTAD When using the SNOOZE mode function the initial setting of each register is specified before switching to the STOP mode For details about these settings see 9 7 3 Setting up hardware trigger wait modeNote 2 Just before move to STOP mode bit 2 AWC of A D converte...

Page 309: ...lly in the subsequent SNOOZE or normal operation mode While in the scan mode If even one A D conversion end interrupt request signal INTAD is generated during A D conversion of the four channels the clock request signal remains at the high level and the A D converter switches from the SNOOZE mode to the normal operation mode At this time be sure to clear bit 2 AWC 0 SNOOZE mode release of A D conv...

Page 310: ...ger is input later A D conversion work is again performed in the SNOOZE mode While in the scan mode If the A D conversion end interrupt request signal INTAD is not generated even once during A D conversion of the four channels the clock request signal an internal signal is automatically set to the low level after A D conversion of the four channels ends and supplying the high speed on chip oscilla...

Page 311: ...R and ADCRH registers Reference voltage stabilization wait time A The reference voltage stabilization wait time count A indicated by A below may be required if the values of the ADREFP1 and ADREFP0 bits are changed If the values of ADREFP1 and ADREFP0 are changed to 1 and 0 respectively A 5 µs A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1 respectivel...

Page 312: ... in the overall error in the characteristics table 3 Quantization error When analog values are converted to digital values a 1 2LSB error naturally occurs In an A D converter an analog input voltage in a range of 1 2LSB is converted to the same digital code so a quantization error cannot be avoided Note that the quantization error is not included in the overall error zero scale error full scale er...

Page 313: ...alue Figure 9 40 Zero Scale Error Figure 9 41 Full Scale Error 111 011 010 001 Ideal line 000 0 1 2 3 4096 4096 4096 Digital output Lower 3 bits AVREF AVREF AVREF AVREF Zero scale error Analog input V 111 110 101 000 0 Ideal line AVREF Digital output Lower 3 bits Full scale error Analog input V AVREF AVREF AVREF 4093 4094 4095 4096 4096 4096 Figure 9 42 Integral Linearity Error Figure 9 43 Differe...

Page 314: ...o Figure 22 3 Format of User Option Byte 000C2H 3 Conflicting operations 1 Conflict between the A D conversion result register ADCR ADCRH write and the ADCR or ADCRH register read by instruction upon the end of conversion The ADCR or ADCRH register read has priority After the read operation the new conversion result is written to the ADCR or ADCRH registers 2 Conflict between the ADCR or ADCRH reg...

Page 315: ...This A D converter charges a sampling capacitor for sampling during sampling time Therefore only a leakage current flows when sampling is not in progress and a current that charges the capacitor flows during sampling Consequently the input impedance fluctuates depending on whether sampling is in progress and on the other states To make sure that sampling is effective however we recommend using the...

Page 316: ...IF ANIn ANIn ANIm ANIm ANIn ANIn ANIm ANIm ADS rewrite start of ANIm conversion ADIF is set but ANIm conversion has not ended 8 Conversion results just after A D conversion start While in the software trigger mode or hardware trigger no wait mode the first A D conversion value immediately after A D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after ...

Page 317: ...alent Circuit of ANIn Pin ANIn C1 C2 R1 Table 9 4 Resistance and Capacitance Values of Equivalent Circuit Reference Values VDD ANIn Pin R1 k C1 pF C2 pF 2 7 V VDD 3 6 V ANI0 to ANI7 7 4 8 6 3 ANI16 12 3 8 7 4 Remark The resistance and capacitance values shown in Table 9 4 are not guaranteed values 11 Starting the A D converter Start the A D converter after the AVREFP and VDD voltages stabilize ...

Page 318: ...digital inputs into analog signals It is used to control analog outputs for two independent channels 10 1 Function of D A Converter The D A converter has the following features 10 bit resolution 2 channels R 2R ladder method Output analog voltage 10 bit resolution VDD m10 1024 m10 Value set to DACSi register Operation mode Normal mode Real time output mode Remark i 0 1 ...

Page 319: ...0 1 DACS0 DACS1 Port mode register 2 PM2 Figure 10 1 shows the block diagram of D A converter Figure 10 1 Block Diagram of D A Converter Internal bus Selector ANO0 P22 pin Write signal of DACS0 register DAMD0 DAM ELCREQ0 DACE0 DAM VDD pin VSS pin Selector ANO1 P23 pin D A conversion value setting register 1 DACS1 D A converter mode register DAM Write signal of DACS1 register DAMD1 DAM ELCREQ1 Inte...

Page 320: ... ADPC register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 00H Figure 10 2 Format of A D Port Configuration Register ADPC Address F0076H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADPC ADPC7 Note ADPC6Note ADPC5Note ADPC4Note ADPC3 ADPC2 ADPC1 ADPC0 ADPCn Analog I O A digital I O D selection of P2n ANI2n 0 Analog I O A default 1 Digital I ...

Page 321: ...generation clears this register to 00H Figure 10 3 Format of Peripheral Enable Register 1 PER1 Address F007AH After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PER1 DACEN 0 0 0 0 0 0 0 DACEN Control of D A converter input clock 0 Stops input clock supply SFR used by the D A converter cannot be written The D A converter is in the reset status 1 Supplies input clock SFR used by the D A converter can be rea...

Page 322: ...0 1 This register is used to set the analog voltage value to be output to the ANO0 and ANO1 pins when the D A converter is used The DACSi register can be read by a 16 bit memory manipulation instruction Reset signal generation clears this register to 00H Figure 10 5 Format of D A Conversion Value Setting Register i DACSi i 0 1 Address FFF58H FFF59H DACS0 FFF5AH FFF5BH DACS1 After reset 0000H R W S...

Page 323: ...r on 1 Input mode output buffer off Note These are not provided in 24 pin products The function of the ANO0 ANI2 P22 to ANO1 ANI3 P23 pins can be selected by using the A D port configuration register ADPC the D A converter mode register DAM the analog input channel specification register ADS and the PM2 register Table 10 2 Setting Functions of ANO0 ANI2 P22 to ANO1 ANI3 P23 Pins ADPC PM2 DAM ADS F...

Page 324: ...CEi bit of the DAM register to 1 D A conversion enable D A conversion starts and then after the settling time elapses the analog voltage set in step 4 is output to the ANOi pin 6 To perform subsequent D A conversions write to the DACSi register The previous D A conversion result is held until the next D A conversion is performed When the DACEi bit of the DAM register is set to 0 D A conversion ope...

Page 325: ...neration of the real time output triggers starts D A conversion and the analog voltage set in step 4 will be output to the ANOi pin after a settling time has elapsed Set the analog voltage value to be output to the ANOi pin to the DACSi register before performing the next D A conversion real time output trigger is generated Set the analog voltage value to be output to the ANOi pin to the DACSi reg...

Page 326: ...herefore clear the DACEi bit to 0 and execute the HALT or STOP instruction after stopping the operation of the D A converter Remark i 0 1 3 To stop the real time output mode including when changing to normal mode one of the following procedures must be used Wait for at least three clocks after stopping the trigger output source and then set bits DACEi and DAMDi to 0 After setting bits DACEi and DA...

Page 327: ...rial array unit 0 has a serial channel that can achieve 3 wire serial CSI and UART communication Function assignment of each channel supported by the RL78 G1P is as shown below Unit Channel Used as CSI Used as UART 0 0 CSI00 supporting slave select input function UART0 1 When UART0 is used CSI00 cannot be used ...

Page 328: ...unication Data transmission reception Data length of 7 or 8 bits Phase control of transmit receive data MSB LSB first selectable Level setting of transmit receive data Clock control Master slave selection Phase control of I O clock Setting of transfer period by prescaler and internal counter of each channel Maximum transfer rate Note During master communication Max fMCK 2 During slave communicatio...

Page 329: ...d by using a channel dedicated to transmission even numbered channel and a channel dedicated to reception odd numbered channel Data transmission reception Data length of 7 8 or 9 bits Select the MSB LSB first Level setting of transmit receive data and select of reverse Parity bit appending and parity check functions Stop bit appending Interrupt function Transfer end interrupt buffer empty interrup...

Page 330: ... status register m SEm Serial channel start register m SSm Serial channel stop register m STm Serial output enable register m SOEm Serial output register m SOm Serial output level register m SOLm Serial standby control register m SSCm Input switch control register ISC Noise filter enable register 0 NFEN0 Registers of each channel Serial data register mn SDRmn Serial mode register mn SMRmn Serial c...

Page 331: ... Serial output enable register 0 SOE0 Serial output level register 0 OL0 Serial output register 0 SO0 Peripheral enable register 0 PER0 Serial clock select register 0 SPS0 fCLK 20 to fCLK 215 fCLK 20 to fCLK 215 Selector Selector Selector Selector Prescaler Serial clock I O pin when CSI00 SCK00 Serial data register 00 SDR00 Clock controller Shift register Buffer register block Output controller In...

Page 332: ...erted by the shift register is stored in the lower 8 9 bits When data is to be transmitted set transmit to be transferred to the shift register to the lower 8 9 bits The data stored in the lower 8 9 bits of this register is as follows depending on the setting of bits 0 and 1 DLSmn0 DLSmn1 of serial communication operation setting register mn SCRmn regardless of the output sequence of the data 7 bi...

Page 333: ...Serial Data Register mn SDRmn mn 00 Address FFF10H FFF11H SDR00 FFF12H FFF13H SDR01 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn 8 7 6 5 4 3 2 1 0 Shift register Remark For the function of the higher 7 bits of the SDRmn register see 11 3 Registers Controlling Serial Array Unit FFF11H SDR00 FFF10H SDR00 ...

Page 334: ...mn SCRmn Serial data register mn SDRmn Serial flag clear trigger register mn SIRmn Serial status register mn SSRmn Serial channel start register m SSm Serial channel stop register m STm Serial channel enable status register m SEm Serial output enable register m SOEm Serial output level register m SOLm Serial output register m SOm Serial standby control register m SSCm Input switch control register...

Page 335: ...ten Serial array unit m is in the reset status 1 Enables input clock supply SFR used by serial array unit m can be read written Cautions 1 When setting serial array unit m be sure to first set the following registers with the SAUmEN bit set to 1 If SAUmEN 0 writing to a control register of serial array unit m is ignored and even if the register is read only the default value is read except for the...

Page 336: ... 0 0 0 0 fCLK 2 MHz 5 MHz 10 MHz 20 MHz 32 MHz 0 0 0 1 fCLK 2 1 MHz 2 5 MHz 5 MHz 10 MHz 16 MHz 0 0 1 0 fCLK 22 500 kHz 1 25 MHz 2 5 MHz 5 MHz 8 MHz 0 0 1 1 fCLK 23 250 kHz 625 kHz 1 25 MHz 2 5 MHz 4 MHz 0 1 0 0 fCLK 24 125 kHz 313 kHz 625 kHz 1 25 MHz 2 MHz 0 1 0 1 fCLK 25 62 5 kHz 156 kHz 313 kHz 625 kHz 1 MHz 0 1 1 0 fCLK 26 31 3 kHz 78 1 kHz 156 kHz 313 kHz 500 kHz 0 1 1 1 fCLK 27 15 6 kHz 39 ...

Page 337: ... fMCK of channel n 0 Operation clock CKm0 set by the SPSm register 1 Operation clock CKm1 set by the SPSm register Operation clock fMCK is used by the edge detector In addition depending on the setting of the CCSmn bit and the higher 7 bits of the SDRmn register a transfer clock fTCLK is generated CCS mn Selection of transfer clock fTCLK of channel n 0 Divided operation clock fMCK specified by the...

Page 338: ...s when data is transferred from the SDRmn register to the shift register For successive transmission the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has run out Note The SMR01 register only Caution Be sure to clear bits 13 to 9 7 and 4 to 2 or bits 13 to 6 and 4 to 2 for the SMR00 register to 0 Be sure to set bit 5 to 1 Remark m Unit number m 0 n Channel number n 0 ...

Page 339: ... 4 Be sure to set DAPmn CKPmn 0 0 in the UART mode EOC mn Mask control of error interrupt signal INTSREx x 0 0 Disables generation of error interrupt INTSREx INTSRx is generated 1 Enables generation of error interrupt INTSREx INTSRx is not generated if an error occurs Set EOCmn 0 in the CSI mode and during UART transmissionNote 2 Notes 1 The SCR00 register only 2 When using CSImn not with EOCmn 0 ...

Page 340: ... n1Note 1 SLC mn0 Setting of stop bit in UART mode 0 0 No stop bit 0 1 Stop bit length 1 bit 1 0 Stop bit length 2 bits mn 00 only 1 1 Setting prohibited When the transfer end interrupt is selected the interrupt is generated when all stop bits have been completely transferred Set 1 bit SLCmn1 SLCmn0 0 1 during UART reception Set no stop bit SLCmn1 SLCmn0 0 0 in the CSI mode Set 1 bit SLCmn1 SLCmn0...

Page 341: ... transmitted to the shift register is set to the lower 9 bits The SDRmn register can be read or written in 16 bit units However the higher 7 bits can be written or read only when the operation is stopped SEmn 0 During operation SEmn 1 a value is written only to the lower 9 bits of the SDRmn register When the SDRmn register is read during operation 0 is always read Reset signal generation clears th...

Page 342: ... SIRmnL Reset signal generation clears the SIRmn register to 0000H Figure 11 8 Format of Serial Flag Clear Trigger Register mn SIRmn Address F0108H F0109H SIR00 F010AH F010BH SIR01 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 FECT mnNote PEC Tmn OVC Tmn FEC Tmn Clear trigger of framing error of channel n 0 Not cleared 1 Clears the FEFmn bit of ...

Page 343: ...mn bit of the SSm register is set to 1 communication is suspended Communication ends Set condition Communication starts BFF mn Buffer register status indication flag of channel n 0 Valid data is not stored in the SDRmn register 1 Valid data is stored in the SDRmn register Clear conditions Transferring transmit data from the SDRmn register to the shift register ends during transmission Reading rece...

Page 344: ...2 C transmission Clear condition 1 is written to the PECTmn bit of the SIRmn register Set condition The parity of the transmit data and the parity bit do not match when UART reception ends parity error OVF mn Overrun error detection flag of channel n 0 No error occurs 1 An error occurs Clear condition 1 is written to the OVCTmn bit of the SIRmn register Set condition Even though receive data is st...

Page 345: ...ars the SSm register to 0000H Figure 11 10 Format of Serial Channel Start Register m SSm Address F0122H F0123H SS0 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS01 SS00 SSmn Operation start trigger of channel n 0 No trigger operation 1 Sets the SEmn bit to 1 and enters the communication wait statusNote Note If set the SSmn 1 to during a commun...

Page 346: ... bits of the STm register can be set with a 1 bit or 8 bit memory manipulation instruction with STmL Reset signal generation clears the STm register to 0000H Figure 11 11 Format of Serial Channel Stop Register m STm Address F0124H F0125H ST0 After reset 0000H W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST01 ST00 STm n Operation stop trigger of channel n 0 No trig...

Page 347: ...ation is output from the serial clock pin Channel n that stops operation can set the value of the CKOmn bit of the SOm register by software and output its value from the serial clock pin In this way any waveform such as that of a start condition stop condition can be created by software The SEm register can be read by a 16 bit memory manipulation instruction The lower 8 bits of the SEm register ca...

Page 348: ...an be output from the serial data output pin In this way any waveform of the start condition and stop condition can be created by software The SOEm register can be set by a 16 bit memory manipulation instruction The lower 8 bits of the SOEm register can be set with a 1 bit or 8 bit memory manipulation instruction with SOEmL Reset signal generation clears the SOEm register to 0000H Figure 11 13 For...

Page 349: ...bled SEmn 1 rewriting by software is ignored and the value of the CKOmn bit can be changed only by a serial communication operation To use a pin for the serial interface as a port function pin other than a serial interface function pin set the corresponding the CKOmn and SOmn bits to 1 The SOm register can be set by a 16 bit memory manipulation instruction Reset signal generation clears the SOm re...

Page 350: ...r can be set with an 8 bit memory manipulation instruction with SOLmL Reset signal generation clears the SOLm register to 0000H Figure 11 15 Format of Serial Output Level Register m SOLm Address F0134H F0135H SOL0 After reset 0000H R W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOL 00 SOL mn Selects inversion of the level of the transmit data of channel n in UA...

Page 351: ...n be set to 1 or 0 only when both the SWCm and EOCmn bits are set to 1 during UART reception in the SNOOZE mode In other cases clear the SSECm bit to 0 Setting SSECm SWCm 1 0 is prohibited SWCm Setting of the SNOOZE mode 0 Do not use the SNOOZE mode function 1 Use the SNOOZE mode function When there is a hardware trigger signal in the STOP mode the STOP mode is exited and A D conversion is perform...

Page 352: ...high impedance While a low level is being input to the SSI00 pin a transmission reception operation is performed according to each mode setting if a serial clock is input The ISC register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears the ISC register to 00H Figure 11 19 Format of Input Switch Control Register ISC Address F0073H After reset 00H R W Sy...

Page 353: ...CPU peripheral hardware clock fCLK is synchronized with 2 clock match detection When the noise filter is OFF only synchronization is performed with the CPU peripheral hardware clock fMCK The NFEN0 register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation clears the NFEN0 register to 00H Figure 11 20 Format of Noise Filter Enable Register 0 NFEN0 Address F0070H...

Page 354: ...ial data input pin or serial clock input pin for serial data input or serial clock input set the port mode register PMxx bit corresponding to each port to 1 At this time the port register Pxx bit may be 0 or 1 Example When using P30 INTP2 TxD0 TOOLTxD SO0 for serial data input Set the PM30 bit of port mode register 3 to 1 Set the P30 bit of port register 3 to 0 or 1 The PM3 register can be set by ...

Page 355: ...019 11 4 Operation Stop Mode Each serial interface of serial array unit has the operation stop mode In this mode serial communication cannot be executed thus reducing the power consumption In addition the pin for serial interface can be used as port function pins in this mode ...

Page 356: ...ns 1 If SAUmEN 0 writing to a control register of serial array unit m is ignored and even if the register is read only the default value is read Note that this does not apply to the following registers Input switch control register ISC Noise filter enable register 0 NFEN0 Port mode register 3 PM3 Port register 3 P3 2 Be sure to clear bits 7 3 and 1 to 0 Remark Bits not used with serial array units...

Page 357: ...th a channel whose operation is stopped the value of the CKOmn bit of the SOm register can be set by software c Serial output enable register m SOEm This register is a register that is used to enable or stop output of the serial communication operation of each channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm0 0 1 0 Stops output by serial communication operation...

Page 358: ...ter slave selection Phase control of I O clock Setting of transfer period by prescaler and internal counter of each channel Maximum transfer rate Note During master communication Max fMCK 2 During slave communication Max fMCK 6 Interrupt function Transfer end interrupt buffer empty interrupt Error detection flag Overrun error In addition CSI00 supports the SNOOZE mode When SCK input is detected wh...

Page 359: ...as UART 0 0 CSI00 supporting slave select input function UART0 1 3 wire serial I O CSI00 performs the following seven types of communication operations Master transmission See 11 5 1 Master reception See 11 5 2 Master transmission reception See 11 5 3 Slave transmission See 11 5 4 Slave reception See 11 5 5 Slave transmission reception See 11 5 6 SNOOZE mode function See 11 5 7 ...

Page 360: ...ransfer rate Note Max fMCK 2 Hz Min fCLK 2 215 128 Hz fCLK System clock frequency Data phase Selectable by the DAPmn bit of the SCRmn register DAPmn 0 Data output starts from the start of the operation of the serial clock DAPmn 1 Data output starts half a clock before the start of the serial clock operation Clock phase Selectable by the CKPmn bit of the SCRmn register CKPmn 0 Non reverse CKPmn 1 R...

Page 361: ...lock phase For details about the setting see 11 3 Registers Controlling Serial Array Unit c Serial data register mn SDRmn lower 8 bits SIOp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn Baud rate setting Operation clock fMCK division setting 0 Transmit data Transmit data setting d Serial output register m SOm Sets only the bits of the target channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOm 0 0 0 0 ...

Page 362: ... Release the serial array unit from the reset status and start clock supply Set the operation clock Set a communication format Set the initial output level of the serial clock CKOmn and serial data SOmn Set the SOEmn bit to 1 and enable data output of the target channel Setting a port register and a port mode register Enable data output and clock output of the target channel by Setting of SAU is c...

Page 363: ...nd stop the output of the target channel Writing the STm register Changing setting of the SOEm register TSFmn 0 If there is any data being transferred wait for their completion If there is an urgent must stop do not wait Yes No The levels of the serial clock CKOmn and serial data SOmn on the target channel can be changed if necessitated by an emergency To use the STOP mode reset the serial array u...

Page 364: ...ster to change serial mode register mn SMRmn setting Set the initial output level of the serial clock CKOmn and serial data SOmn Enable data output and clock output of the target channel by setting a port register and a port mode register Set the SSmn bit of the target channel to 1 SEmn 1 to enable operation Setting is completed Sets transmit data to the SIOp register bits 7 to 0 of the SDRmn regi...

Page 365: ...gle Transmission Mode Type 1 DAPmn 0 CKPmn 0 Shift operation Shift operation Shift operation SSmn SEmn SDRmn STmn INTCSIp TSFmn Data transmission Data transmission Data transmission Transmit data 3 Transmit data 2 Transmit data 1 Transmit data 3 Transmit data 2 Transmit data 1 SCKp pin SOp pin Shift register mn Remark m Unit number m 0 n Channel number n 0 p CSI number p 00 mn 00 ...

Page 366: ...rrupt mask XXMK and set interrupt enable EI Disable interrupt MASK Set data for transmission and the number of data Clear communication end flag Storage area Transmission data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software Check completion of transmission by verifying transmit end flag Writing to SIOp makes SOp and SCKp signal...

Page 367: ...smission Shift operation Shift operation Shift operation SCKp pin SOp pin Shift register mn 2 3 2 3 2 3 5 4 6 1 Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn SSRmn is 1 valid data is stored in serial data register mn SDRmn the transmit data is overwritten Caution The MDmn0 bit of serial mode register mn SMRmn can be rewritten even during op...

Page 368: ...n data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software Clear interrupt request flag XXIF reset interrupt mask XXMK and set interrupt enable EI 1 2 3 5 4 Read transmit data from storage area and write it to SIOp Update transmit data pointer Writing to SIOp makes SOp and SCKp signals out communication starts When transfer end int...

Page 369: ...h 7 or 8 bits Transfer rate Note Max fMCK 2 Hz Min fCLK 2 215 128 Hz fCLK System clock frequency Data phase Selectable by the DAPmn bit of the SCRmn register DAPmn 0 Data input starts from the start of the operation of the serial clock DAPmn 1 Data input starts half a clock before the start of the serial clock operation Clock phase Selectable by the CKPmn bit of the SCRmn register CKPmn 0 Non reve...

Page 370: ...ng see 11 3 Registers Controlling Serial Array Unit c Serial data register mn SDRmn lower 8 bits SIOp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn Baud rate setting Operation clock fMCK division setting 0 Receive data Write FFH as dummy data d Serial output register m SOm Sets only the bits of the target channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOm 0 0 0 0 0 0 0 CKOm0 0 1 0 0 0 0 0 0 0 SOm0 Co...

Page 371: ... SSm register End of initial setting Release the serial array unit from the reset status and start clock supply Set the operation clock Set a communication format Set the initial output level of the serial clock CKOmn Enable clock output of the target channel by setting a port register and a port mode register Initial setting is completed Set dummy data to the SIOp register bits 7 to 0 of the SDRm...

Page 372: ...it to 0 and stop the output of the target channel Writing the STm register Changing setting of the SOEm register TSFmn 0 If there is any data being transferred wait for their completion If there is an urgent must stop do not wait Yes No The levels of the serial clock CKOmn and serial data SOmn on the target channel can be changed if necessitated by an emergency Reset the serial array unit by stopp...

Page 373: ...tting Re set the register to change the transfer baud rate setting setting the transfer clock by dividing the operation clock fMCK Re set the register to change serial mode register mn SMRmn setting Set the initial output level of the serial clock CKOmn Enable clock output of the target channel by setting a port register and a port mode register Set the SSmn bit of the target channel to 1 SEmn bit...

Page 374: ... data 3 Receive data 2 Receive data 1 Dummy data for reception Dummy data Dummy data Receive data 1 Receive data 2 Receive data 3 SSmn SEmn SDRmn STmn SCKp pin SIp pin Shift register mn INTCSIp TSFmn Data reception Data reception Data reception Reception shift operation Reception shift operation Reception shift operation Write Read Read Read Write Write Remark m Unit number m 0 n Channel number n ...

Page 375: ...interrupt processing routine Writing to SIOp makes SCKp signals out communication starts RETI Transfer end interrupt generated Setting receive data Setting storage area of the receive data number of communication data Storage area Reception data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software Read receive data then writes to st...

Page 376: ...e data 3 Data reception STmn Dummy data Dummy data Dummy data Reception shift operation Data reception Data reception Reception shift operation Reception shift operation Write Read Read Write Write Read 2 Caution The MDmn0 bit can be rewritten even during operation However rewrite it before receive of the last bit is started so that it has been rewritten before the transfer end interrupt of the la...

Page 377: ...Buffer empty transfer end interrupt When interrupt is generated it moves to interrupt processing routine No Read receive data if any then write them to storage area and update receive data pointer also subtract 1 from number of transmit data When number of communication data becomes 0 receive completes Yes 1 2 3 6 End of communication Disable interrupt MASK Subtract 1 from number of transmit data ...

Page 378: ...nsfer data length 7 or 8 bits Transfer rate Note Max fMCK 2 Hz Min fCLK 2 215 128 Hz fCLK System clock frequency Data phase Selectable by the DAPmn bit of the SCRmn register DAPmn 0 Data I O starts at the start of the operation of the serial clock DAPmn 1 Data I O starts half a clock before the start of the serial clock operation Clock phase Selectable by the CKPmn bit of the SCRmn register CKPmn ...

Page 379: ...3 Registers Controlling Serial Array Unit c Serial data register mn SDRmn lower 8 bits SIOp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn Baud rate setting Operation clock fMCK division setting 0 Transmit data setting receive data register d Serial output register m SOm Sets only the bits of the target channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOm 0 0 0 0 0 0 0 CKOm0 0 1 0 0 0 0 0 0 0 SOm0 0 1 C...

Page 380: ...ster Completing initial setting Release the serial array unit from the reset status and start clock supply Set the operation clock Set a communication format Set the initial output level of the serial clock CKOmn and serial data SOmn Set the SOEmn bit to 1 and enable data output of the target channel Enable data output and clock output of the target channel by setting a port register and a port mo...

Page 381: ...OEmn bit to 0 and stop the output of the target channel Writing the STm register Changing setting of the SOEm register TSFmn 0 If there is any data being transferred wait for their completion If there is an urgent must stop do not wait Yes No The levels of the serial clock CKOmn and serial data SOmn on the target channel can be changed if necessitated by an emergency Reset the serial array unit by...

Page 382: ...evel of the serial clock CKOmn and serial data SOmn Enable data output and clock output of the target channel by setting a port register and a port mode register Set the SSmn bit of the target channel to 1 SEmn 1 to enable operation Sets transmit data to the SIOp register bits 7 to 0 of the SDRmn register and start communication Essential Selective Selective Selective Selective Essential Essential...

Page 383: ...e data 3 SSmn SEmn SDRmn STmn SCKp pin SIp pin Shift register mn INTCSIp TSFmn SOp pin Data transmission reception Data transmission reception Data transmission reception Transmit data 3 Transmit data 2 Transmit data 1 Reception shift operation Reception shift operation Reception shift operation Receive data 3 Receive data 2 Receive data 1 Transmit data 3 Transmit data 2 Transmit data 1 Write Read...

Page 384: ...ransfer end interrupt Read receive data then writes to storage area update receive data pointer RETI If there are the next data it continues Write STmn bit to 1 Setting transmission reception data Setting storage data and number of data for transmission reception data Storage area Transmission data pointer Reception data pointer Number of communication data and Communication end flag are optionall...

Page 385: ...smit data 2 Transmit data 3 Receive data 1 Receive data 2 Write Write Write Read Read Read Notes 1 If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn SSRmn is 1 valid data is stored in serial data register mn SDRmn the transmit data is overwritten 2 The transmit data can be read by reading the SDRmn register during this period At this time the transf...

Page 386: ... area and update receive data pointer Yes 1 2 3 6 End of communication Disable interrupt MASK Subtract 1 from number of transmit data Number of communication data RETI Number of communication data 0 Yes Write MDmn0 bit to 1 Continuing Communication 4 7 5 No SAU default setting 0 2 No Yes 1 Read transmit data from storage area and write it to SIOp Update transmit data pointer Writing transmit data ...

Page 387: ...lectable by the DAPmn bit of the SCRmn register DAPmn 0 Data output starts from the start of the operation of the serial clock DAPmn 1 Data output starts half a clock before the start of the serial clock operation Clock phase Selectable by the CKPmn bit of the SCRmn register CKPmn 0 Non reverse CKPmn 1 Reverse Data direction MSB or LSB first Notes 1 Because the external serial clock input to the S...

Page 388: ...length 0 7 bit data length 1 8 bit data length Selection of the data and clock phase For details about the setting see 11 3 Registers Controlling Serial Array Unit c Serial data register mn SDRmn lower 8 bits SIOp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn 0000000 Baud rate setting 0 Transmit data setting d Serial output register m SOm Sets only the bits of the target channel 15 14 13 12 11 10 9 ...

Page 389: ...m register Completing initial setting Release the serial array unit from the reset status and start clock supply Set the operation clock Set a communication format Set the initial output level of the serial data SOmn Set the SOEmn bit to 1 and enable data output of the target channel Enable data output of the target channel by setting a port register and a port mode register Initial setting is com...

Page 390: ...bit to 0 and stop the output of the target channel Writing the STm register Changing setting of the SOEm register TSFmn 0 If there is any data being transferred wait for their completion If there is an urgent must stop do not wait Yes No The levels of the serial clock CKOmn and serial data SOmn on the target channel can be changed if necessitated by an emergency Reset the serial array unit by stop...

Page 391: ...etting a port register and a port mode register Set the SSmn bit of the target channel to 1 SEmn 1 to enable operation Sets transmit data to the SIOp register bits 7 to 0 of the SDRmn register and wait for a clock from the master Selective Selective Selective Essential Essential Essential Essential Re set the register to change serial communication operation setting register mn SCRmn setting Selec...

Page 392: ...le Transmission Mode Type 1 DAPmn 0 CKPmn 0 Shift operation Shift operation Shift operation SSmn SEmn SDRmn STmn SCKp pin SOp pin Shift register mn INTCSIp TSFmn Data transmission Data transmission Data transmission Transmit data 3 Transmit data 2 Transmit data 1 Transmit data 3 Transmit data 2 Transmit data 1 Remark m Unit number m 0 n Channel number n 0 p CSI number p 00 mn 00 ...

Page 393: ...lag are optionally set on the internal RAM by the software Enables interrupt Writing transmit data to SIOp SDRmn 7 0 Start communication when master start providing the clock When transmit end interrupt is generated Determine if it completes by counting number of communication data Read transmit data from storage area and write it to SIOp Update transmit data pointer Transmitting next data No Disa...

Page 394: ...ata 1 Transmit data 2 Transmit data 1 Transmit data 3 Shift operation Shift operation Shift operation Data transmission Data transmission Data transmission Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn SSRmn is 1 valid data is stored in serial data register mn SDRmn the transmit data is overwritten Caution The MDmn0 bit of serial mode regis...

Page 395: ...data is left read them from storage area then write into SIOp and update transmit data pointer If not change the interrupt to transmission complete Yes 1 2 3 5 End of communication Disable interrupt MASK Reading transmit data RETI Number of communication data 1 Yes Write MDmn0 bit to 1 Communication continued No SAU default setting No Yes Read transmit data from buffer and write it to SIOp Update ...

Page 396: ... bit of the SCRmn register DAPmn 0 Data input starts from the start of the operation of the serial clock DAPmn 1 Data input starts half a clock before the start of the serial clock operation Clock phase Selectable by the CKPmn bit of the SCRmn register CKPmn 0 Non reverse CKPmn 1 Reverse Data direction MSB or LSB first Notes 1 Because the external serial clock input to the SCK00 pin is sampled int...

Page 397: ...gth 0 7 bit data length 1 8 bit data length Selection of the data and clock phase For details about the setting see 11 3 Registers Controlling Serial Array Unit c Serial data register mn SDRmn lower 8 bits SIOp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn 0000000 Baud rate setting 0 Receive data d Serial output register m SOm The Register that not used in this mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 398: ...s an urgent must stop do not wait Yes No Reset the serial array unit by stopping the clock supply to it Setting the PER0 register Essential Selective Essential Selective Starting initial settings Setting the PER0 register Setting the SPSm register Setting the SMRmn register Setting the SCRmn register Setting the SDRmn register Setting port Writing to the SSm register Completing initial setting Rel...

Page 399: ...mode register Set the SSmn bit of the target channel to 1 SEmn bit 1 to enable operation and wait for a clock from the master Essential Selective Selective Essential Essential Re set the register to change serial communication operation setting register mn SCRmn setting Selective Changing setting of the SCRmn register If the OVF flag remain set clear this using serial flag clear trigger register m...

Page 400: ...e Type 1 DAPmn 0 CKPmn 0 Receive data 3 Reception shift operation Reception shift operation Reception shift operation SSmn SEmn SDRmn STmn SCKp pin SIp pin Shift register mn INTCSIp TSFmn Data reception Data reception Data reception Receive data 3 Receive data 2 Receive data 1 Receive data 2 Receive data 1 Read Read Read Remark m Unit number m 0 n Channel number n 0 p CSI number p 00 mn 00 ...

Page 401: ... end interrupt is generated Wait for receive completes RETI Transfer end interrupt Read receive data then writes to storage area and counts up the number of receive data Update receive data pointer Check completion of number of receive data Ready for reception Clear storage area setting and the number of receive data Storage area Reception data pointer Number of communication data and Communicatio...

Page 402: ...Notes 1 2 Data phase Selectable by the DAPmn bit of the SCRmn register DAPmn 0 Data I O starts from the start of the operation of the serial clock DAPmn 1 Data I O starts half a clock before the start of the serial clock operation Clock phase Selectable by the CKPmn bit of the SCRmn register CKPmn 0 Non reverse CKPmn 1 Reverse Data direction MSB or LSB first Notes 1 Because the external serial clo...

Page 403: ...e data and clock phase For details about the setting see 11 3 Registers Controlling Serial Array Unit c Serial data register mn SDRmn lower 8 bits SIOp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn 0000000 Baud rate setting 0 Transmit data setting receive data register d Serial output register m SOm Sets only the bits of the target channel 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOm 0 0 0 0 0 0 0 CKOm...

Page 404: ... initial setting Release the serial array unit from the reset status and start clock supply Set the operation clock Set an operation mode etc Set a communication format Set bits 15 to 9 to 0000000B for baud rate setting Set the initial output level of the serial data SOmn Set the SOEmn bit to 1 and enable data output of the target channel Enable data output of the target channel by setting a port ...

Page 405: ...OEmn bit to 0 and stop the output of the target channel Writing the STm register Changing setting of the SOEm register TSFmn 0 If there is any data being transferred wait for their completion If there is an urgent must stop do not wait Yes No The levels of the serial clock CKOmn and serial data SOmn on the target channel can be changed if necessitated by an emergency Reset the serial array unit by...

Page 406: ...hange serial mode register mn SMRmn setting Set the initial output level of the serial data SOmn Enable data output of the target channel by setting a port register and a port mode register Set the SSmn bit of the target channel to 1 SEmn 1 to enable operation Essential Selective Selective Selective Essential Essential Clearing error flag Selective If the OVF flag remain set clear this using seria...

Page 407: ...shift operation Reception shift operation SSmn SEmn SDRmn STmn SCKp pin SIp pin Shift register mn INTCSIp TSFmn SOp pin Data transmission reception Data transmission reception Data transmission reception Transmit data 3 Transmit data 2 Transmit data 1 Receive data 3 Receive data 2 Receive data 1 Transmit data 3 Transmit data 2 Transmit data 1 Receive data 1 Receive data 2 Receive data 3 Write Read...

Page 408: ...efault setting Setting transmission reception data Setting storage area and number of data for transmission reception data Storage area Transmission reception data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software RETI Transfer end interrupt Enables interrupt Clear interrupt request flag XXIF reset interrupt mask XXMK and set int...

Page 409: ...smit data 2 Transmit data 3 Receive data 1 Receive data 2 Write Write Write Read Read Read Notes 1 If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn SSRmn is 1 valid data is stored in serial data register mn SDRmn the transmit data is overwritten 2 The transmit data can be read by reading the SDRmn register during this period At this time the transf...

Page 410: ...tes to storage area update receive data pointer Yes 1 3 6 End of communication Disable interrupt MASK Subtract 1 from number of transmit data Number of communication data RETI Number of communication data 0 Yes Write MDmn0 bit to 1 Communication continued 4 7 5 No SAU default setting 0 2 No Yes 1 Writing transmit data to SIOp SDRmn 7 0 Clear MDmn0 bit to 0 Start communication when master start pro...

Page 411: ...ied when the high speed on chip oscillator clock is selected for fCLK 2 The maximum transfer rate when using CSIp in the SNOOZE mode is 1 Mbps 1 SNOOZE mode operation once startup Figure 11 70 Timing Chart of SNOOZE Mode Operation Once Startup Type 1 DAPmn 0 CKPmn 0 SS00 SE00 SWC0 SSEC0 L SDR00 SCK00 pin CPU operation status STOP mode SNOOZE mode Normal operation Normal operation SI00 pin Clock re...

Page 412: ...NOOZE mode setting 6 The mode switches from SNOOZE to normal operation Become the communication wait status SEm0 1 SNOOZE mode operation Transfer interrupt INTCSIp is generated CSIp is receive completion End of SNOOZE mode Write SSm0 bit to 1 11 Become the operation STOP status SEm0 0 SMRm0 SCRm0 Communication setting SDRm0 15 9 Setting 0000000B Become the operation STOP status SEm0 0 It becomes c...

Page 413: ...ta 2 Reception shift operation Reception shift operation Data reception Data reception Read Note 2 2 5 6 7 5 6 8 10 4 3 9 4 1 3 STOP mode Note Only read received data while SWCm 1 and before the next edge of the SCKp pin input is detected Cautions 1 Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes set the STm0 bit to 1 clear the SEm0 bit and stop the ope...

Page 414: ...lock fCLK supplied to the SAU is stopped 1 2 3 4 5 7 8 9 10 Reset SNOOZE mode setting 6 The mode switches from SNOOZE to normal operation Become the communication wait status SEm0 1 SNOOZE operation Transfer interrupt INTCSIp is generated CSIp is receive completion Become the operation STOP status SEm0 0 SAU default setting SMRm0 SCRm0 Communication setting SDRm0 15 9 Setting 0000000B Enables inte...

Page 415: ...ion clock fMCK frequency of target channel SDRmn 15 9 1 2 Hz 2 Slave Transfer clock frequency Frequency of serial clock SCK supplied by master Note Hz Note The permissible maximum transfer clock frequency is fMCK 6 Remark The value of SDRmn 15 9 is the value of bits 15 to 9 of serial data register mn SDRmn 0000000B to 1111111B and therefore is 0 to 127 The operation clock fMCK is determined by ser...

Page 416: ... 213 3 91 kHz X X X X 1 1 1 0 fCLK 214 1 95 kHz X X X X 1 1 1 1 fCLK 215 977 Hz 1 0 0 0 0 X X X X fCLK 32 MHz 0 0 0 1 X X X X fCLK 2 16 MHz 0 0 1 0 X X X X fCLK 22 8 MHz 0 0 1 1 X X X X fCLK 23 4 MHz 0 1 0 0 X X X X fCLK 24 2 MHz 0 1 0 1 X X X X fCLK 25 1 MHz 0 1 1 0 X X X X fCLK 26 500 kHz 0 1 1 1 X X X X fCLK 27 250 kHz 1 0 0 0 X X X X fCLK 28 125 kHz 1 0 0 1 X X X X fCLK 29 62 5 kHz 1 0 1 0 X X...

Page 417: ...Remark Reads serial data register mn SDRmn The BFFmn bit of the SSRmn register is set to 0 and channel n is enabled to receive data This is to prevent an overrun error if the next reception is completed during error processing Reads serial status register mn SSRmn Error type is identified and the read value is used to clear error flag Writes 1 to serial flag clear trigger register mn SIRmn Error f...

Page 418: ...r and internal counter of each channel Maximum transfer rate Note During slave communication Max fMCK 6 Interrupt function Transfer end interrupt buffer empty interrupt Error detection flag Overrun error Expansion function Slave select function Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical specifications see CHAPTER 27 ELECT...

Page 419: ... data can be communicated from the SO pin to the master When a slave is not selected the SO pin is set to high impedance output Therefore short circuit of the SO pin with SO output of other slave can be avoided Furthermore when a slave is not selected no transmission reception operation is performed even if a serial clock is input from the master Caution Output the slave select signal by port mani...

Page 420: ...o the data output However no shift operation is performed even if the rising edge of SCKmn serial clock arrives and neither is receive data sampled in synchronization with the falling edge When SSImn goes to low level data is output shifted in synchronization with the next rising edge and a reception operation is performed in synchronization with the falling edge While SSImn is at high level trans...

Page 421: ...able by the DAPmn bit of the SCRmn register DAPmn 0 Data output starts from the start of the operation of the serial clock DAPmn 1 Data output starts half a clock before the start of the serial clock operation Clock phase Selectable by the CKPmn bit of the SCRmn register CKPmn 0 Non reverse CKPmn 1 Reverse Data direction MSB or LSB first Slave select Input function Slave select input function oper...

Page 422: ...outputs data with MSB first 1 Inputs outputs data with LSB first Setting of data length 0 7 bit data length 1 8 bit data length Selection of the data and clock phase For details about the setting see 11 3 Registers Controlling Serial Array Unit c Serial data register mn SDRmn lower 8 bits SIOp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn 0000000 Baud rate setting 0 Transmit data setting d Serial ou...

Page 423: ...0 0 0 0 0 SSm3 SSm2 SSm1 SSm0 0 1 g Input switch control register ISC SSI00 input setting in CSI00 slave channel channel 0 of unit 0 7 6 5 4 3 2 1 0 ISC SSIE00 0 1 0 0 0 0 0 ISC1 0 1 ISC0 0 1 0 Disables the input value of the SSI00 pin 1 Enables the input value of the SSI00 pin Remarks 1 m Unit number m 0 n Channel number n 0 p CSI number p 00 2 Setting disabled set to the initial value Bit that c...

Page 424: ... serial array unit from the reset status and start clock supply Set the operation clock Set a communication format Set the initial output level of the serial data SOmn Set the SOEmn bit to 1 and enable data output of the target channel Enable data output of the target channel by setting a port register and a port mode register When connecting multiple slaves set N ch open drain before setting data...

Page 425: ...he output of the target channel After the stop setting is completed go to the next processing The levels of the serial data SOmn on the target channel can be changed if necessitated by an emergency Changing setting of the SOm register Setting the PER0 register Reset the serial array unit by stopping the clock supply to it Selective Selective Essential Essential TSFmn 0 No If there is any data bein...

Page 426: ... 1 SEmn 1 to enable operation Sets transmit data to the SIOp register bits 7 to 0 of the SDRmn register and wait for a clock from the master Completing resumption setting Starting communication Enable data output of the target channel by setting a port register and a port mode register When connecting multiple slaves set N ch open drain before setting data output Writing to the ISC register Port m...

Page 427: ...e Transmission Mode Type 1 DAPmn 0 CKPmn 0 Shift operation Shift operation Shift operation SSmn SEmn SDRmn STmn SCKp pin SOp pin Shift register mn INTCSIp TSFmn Data transmission Data transmission Data transmission Transmit data 3 Transmit data 2 Transmit data 1 Transmit data 3 Transmit data 2 Transmit data 1 SSIp pin Remark m Unit number m 0 n Channel number n 0 p CSI number p 00 ...

Page 428: ...ta for transmit data Storage area Transmission data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software Clear interrupt request flag XXIF reset interrupt mask XXMK and set interrupt enable EI Read transmit data from storage area and write it to SIOp Update transmit data pointer When transmit end interrupt is generated Start communi...

Page 429: ...mit data 1 Transmit data 3 Shift operation Shift operation Shift operation Data transmission Data transmission Data transmission SSIp pin 1 2 2 2 3 3 3 5 6 4 Note Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn SSRmn is 1 valid data is stored in serial data register mn SDRmn the transmit data is overwritten Caution The MDmn0 bit of serial mod...

Page 430: ...smit data pointer Start communication when master start providing the clock When buffer empty transfer end interrupt is generated it moves to interrupt processing routine If transmit data is left read them from storage area then write into SIOp and update transmit data pointer If not change the interrupt to transmission complete Clear MDmn0 bit to 0 4 It is determined as follows depending on the n...

Page 431: ...Rmn register DAPmn 0 Data input starts from the start of the operation of the serial clock DAPmn 1 Data input starts half a clock before the start of the serial clock operation Clock phase Selectable by the CKPmn bit of the SCRmn register CKPmn 0 Non reverse CKPmn 1 Reverse Data direction MSB or LSB first slave select input function Slave select input function operation selectable Notes 1 Because ...

Page 432: ...tputs data with MSB first 1 Inputs outputs data with LSB first Setting of data length 0 7 bit data length 1 8 bit data length Selection of the data and clock phase For details about the setting see 11 3 Registers Controlling Serial Array Unit c Serial data register mn SDRmn lower 8 bits SIOp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn 0000000 Baud rate setting 0 Receive data d Serial output regist...

Page 433: ... 0 0 0 0 SSm3 SSm2 SSm1 SSm0 0 1 g Input switch control register ISC SSI00 input setting in CSI00 slave channel channel 0 of unit 0 7 6 5 4 3 2 1 0 ISC SSIE00 0 1 0 0 0 0 0 ISC1 0 1 ISC0 0 1 0 Disables the input value of the SSI00 pin 1 Enables the input value of the SSI00 pin Remarks 1 m Unit number m 0 n Channel number n 0 p CSI number p 00 2 Setting disabled set to the initial value Bit that ca...

Page 434: ...wait for their completion If there is an urgent must stop do not wait Yes Selective Remark m Unit number m 0 n Channel number n 0 p CSI number p 00 Starting initial settings Setting the PER0 register Setting the SPSm register Setting the SMRmn register Setting the SCRmn register Setting the SDRmn register Setting port Writing to the SSm register Starting communication Release the serial array unit...

Page 435: ...ter to change serial communication operation setting register mn SCRmn setting If the OVF flag remains set clear this using serial flag clear trigger register mn SIRmn Essential Selective Writing to the SSm register Selective Selective Selective Essential Set the SSmn bit of the target channel to 1 SEmn bit 1 to enable operation Wait for a clock from the master Completing master preparations No Wa...

Page 436: ...Type 1 DAPmn 0 CKPmn 0 SSmn SEmn SDRmn STmn SCKp pin SIp pin Shift register mn INTCSIp TSFmn Receive data 3 Receive data 2 Receive data 1 Reception shift operation Reception shift operation Reception shift operation Receive data 3 Receive data 2 Receive data 1 Data reception Data reception Data reception Read Read Read SSIp pin Remark m Unit number m 0 n Channel number n 0 p CSI number p 00 ...

Page 437: ... end interrupt is generated Wait for receive completes RETI Transfer end interrupt Read receive data then writes to storage area and counts up the number of receive data Update receive data pointer Check completion of number of receive data Ready for reception Clear storage area setting and the number of receive data Storage area Reception data pointer Number of communication data and Communicatio...

Page 438: ...a phase Selectable by the DAPmn bit of the SCRmn register DAPmn 0 Data I O starts from the start of the operation of the serial clock DAPmn 1 Data I O starts half a clock before the start of the serial clock operation Clock phase Selectable by the CKPmn bit of the SCRmn register CKPmn 0 Non reverse CKPmn 1 Reverse Data direction MSB or LSB first Slave select input function Slave select input funct...

Page 439: ...st Setting of data length 0 7 bit data length 1 8 bit data length Selection of the data and clock phase For details about the setting see 11 3 Registers Controlling Serial Array Unit c Serial data register mn SDRmn lower 8 bits SIOp 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn 0000000 Baud rate setting 0 Transmit data setting receive data register d Serial output register m SOm Sets only the bits o...

Page 440: ... 0 0 0 0 0 0 0 SSm3 SSm2 SSm1 SSm0 0 1 g Input switch control register ISC SSI00 input setting in CSI00 slave channel channel 0 of unit 0 7 6 5 4 3 2 1 0 ISC SSIE00 0 1 0 0 0 0 0 ISC1 0 1 ISC0 0 1 0 Disables the input value of the SSI00 pin 1 Enables the input value of the SSI00 pin Remarks 1 m Unit number m 0 n Channel number n 0 p CSI number p 00 2 Setting disabled set to the initial value Bit t...

Page 441: ...ease the serial array unit from the reset status and start clock supply Set the operation clock Set an operation mode etc Set a communication format Set bits 15 to 9 to 0000000B for baud rate setting Set the initial output level of the serial data SOmn Set the SOEmn bit to 1 and enable data output of the target channel Enable data output of the target channel by setting a port register and a port ...

Page 442: ...completion If there is an urgent must stop do not wait Write 1 to the STmn bit of the target channel SEmn 0 to operation stop status Set the SOEmn bit to 0 and stop the output of the target channel The levels of the serial data SOmn on the target channel can be changed if necessitated by an emergency After the stop setting is completed go to the next processing Reset the serial array unit by stopp...

Page 443: ...change serial mode register mn SMRmn setting Re set the register to change serial communication operation setting register mn SCRmn setting If the OVF flag remains set clear this using serial flag clear trigger register mn SIRmn Set the SOEmn bit to 0 to stop output from the target channel Set the initial output level of the serial data SOmn Set the SOEmn bit to 1 and enable output from the target...

Page 444: ...hift operation Reception shift operation SSmn SEmn SDRmn STmn SCKp pin SIp pin Shift register mn INTCSIp TSFmn SOp pin Data transmission reception Data transmission reception Data transmission reception Transmit data 3 Transmit data 2 Transmit data 1 Receive data 3 Receive data 2 Receive data 1 Transmit data 3 Transmit data 2 Transmit data Receive data 1 Receive data 2 Receive data 3 Write Read Re...

Page 445: ...ion reception data Setting storage area and number of data for transmission reception data Storage area Transmission reception data pointer Number of communication data and Communication end flag are optionally set on the internal RAM by the software RETI Transfer end interrupt Enables interrupt Clear interrupt request flag XXIF reset interrupt mask XXMK and set interrupt enable EI Disable interru...

Page 446: ...e data 2 Write Write Write Read Read Read SSIp pin 4 5 1 2 3 2 3 4 2 7 8 6 3 Note 1 Note 2 Note 2 Notes 1 If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn SSRmn is 1 valid data is stored in serial data register mn SDRmn the transmit data is overwritten 2 The transmit data can be read by reading the SDRmn register during this period At this time the...

Page 447: ...rst interrupt read reception data then writes to storage area update receive data pointer Yes 1 3 6 End of communication Disable interrupt MASK Subtract 1 from number of transmit data Number of communication data RETI Number of communication data 0 Yes Write MDmn0 bit to 1 Communication continued 4 7 5 No SAU default setting 0 2 No Yes 1 Writing transmit data to SIOp SDRmn 7 0 Clear MDmn0 bit to 0...

Page 448: ...er clock frequency for slave select input function CSI00 communication can be calculated by the following expressions 1 Slave Transfer clock frequency Frequency of serial clock SCK supplied by master Note Hz Note The permissible maximum transfer clock frequency is fMCK 6 Remark m Unit number m 0 n Channel number n 0 p CSI number p 00 ...

Page 449: ...X X X X 0 1 0 1 fCLK 25 1 MHz X X X X 0 1 1 0 fCLK 26 500 kHz X X X X 0 1 1 1 fCLK 27 250 kHz X X X X 1 0 0 0 fCLK 28 125 kHz X X X X 1 0 0 1 fCLK 29 62 5 kHz X X X X 1 0 1 0 fCLK 210 31 25 kHz X X X X 1 0 1 1 fCLK 211 15 63 kHz X X X X 1 1 0 0 fCLK 212 7 81 kHz X X X X 1 1 0 1 fCLK 213 3 9 kHz X X X X 1 1 1 0 fCLK 214 1 95 kHz X X X X 1 1 1 1 fCLK 215 977 Hz Note When changing the clock selected ...

Page 450: ...Status Remark Reads serial data register mn SDRmn The BFFmn bit of the SSRmn register is set to 0 and channel n is enabled to receive data This is to prevent an overrun error if the next reception is completed during error processing Reads serial status register mn SSRmn Error type is identified and the read value is used to clear error flag Writes 1 to serial flag clear trigger register mn SIRmn ...

Page 451: ...by using a channel dedicated to transmission even numbered channel and a channel dedicated to reception odd numbered channel Data transmission reception Data length of 7 8 or 9 bits Select the MSB LSB first Level setting of transmit receive data selecting whether to reverse the level Parity bit appending and parity check functions Stop bit appending stop bit check function Interrupt function Trans...

Page 452: ...on UART0 1 If UART0 is selected for channels 0 and 1 of unit 0 for example these channels cannot be used for CSI00 Caution When using a serial array unit for UART both the transmitter side even numbered channel and the receiver side odd numbered channel can only be used for UART UART performs the following two types of communication operations UART transmission See 11 7 1 UART reception See 11 7 2...

Page 453: ...ransfer data length 7 8 or 9 bits Transfer rate Max fMCK 6 bps SDRmn 15 9 2 or more Min fCLK 2 215 128 bps Note Data phase Non reverse output default high level Reverse output default low level Parity bit The following selectable No parity bit Appending 0 parity Appending even parity Appending odd parity Stop bit The following selectable Appending 1 bit Appending 2 bits Data direction MSB or LSB f...

Page 454: ...ng 2 bits 01B Appending 0 parity 10B Appending Even parity 11B Appending Odd parity Selection of data transfer sequence 0 Inputs outputs data with MSB first 1 Inputs outputs data with LSB first c Serial data register mn SDRmn lower 8 bits TXDq 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn Baud rate setting 0 Note Transmit data setting d Serial output level register m SOLm Sets only the bits of the t...

Page 455: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm0 0 1 g Serial channel start register m SSm Sets only the bits of the target channel to 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSm1 SSm0 0 1 Note Before transmission is started be sure to set to 1 when the SOLmn bit of the target channel is set to 0 and set to 0 when the SOLmn bit of the target channel is set to 1 The value varies de...

Page 456: ...tus and start clock supply Set the operation clock Set an operation mode etc Set a communication format Set a transfer baud rate setting the transfer clock by dividing the operation clock fMCK Set the initial output level of the serial data SOmn Enable data output of the target channel by setting a port register and a port mode register Set the SOEmn bit to 1 and enable data output of the target c...

Page 457: ...bit to 0 and stop the output of the target channel Writing the STm register Changing setting of the SOEm register TSFmn 0 If there is any data being transferred wait for their completion If there is an urgent must stop do not wait Yes No The levels of the serial clock CKOmn and serial data SOmn on the target channel can be changed if necessitated by an emergency Reset the serial array unit by stop...

Page 458: ...cation operation setting register mn SCRmn setting Re set the register to change serial output level register m SOLm setting Clear the SOEmn bit to 0 and stop output Set the initial output level of the serial data SOmn Set the SOEmn bit to 1 and enable output Enable data output of the target channel by setting a port register and a port mode register Selective Selective Writing to the SSm register...

Page 459: ...Single Transmission Mode P Shift operation Shift operation Shift operation SP ST ST P SP ST P SP SSmn SEmn SDRmn TxDq pin Shift register mn INTSTq TSFmn STmn Data transmission Data transmission Data transmission Transmit data 1 Transmit data 2 Transmit data 3 Transmit data 1 Transmit data 2 Transmit data 3 Remark m Unit number m 0 n Channel number n 0 q UART number q 0 mn 00 ...

Page 460: ...AM by the software Clear interrupt request flag XXIF reset interrupt mask XXMK and setinterrupt enable EI Read transmit data from storage area and write it to TxDq Update transmit data pointer Communication starts by writing to SDRmn 7 0 When Transfer end interrupt is generated it moves to interrupt processing routine Read transmit data if any from storage area and write it to SIOp Update transmit...

Page 461: ...ansmission Transmit data 2 Transmit data 1 Transmit data 3 Transmit data 3 Transmit data 2 Transmit data 1 Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn SSRmn is 1 valid data is stored in serial data register mn SDRmn the transmit data is overwritten Caution The MDmn0 bit of serial mode register mn SSRmn can be rewritten even during operati...

Page 462: ... Update transmit data pointer Communication starts by writing to SDRmn 7 0 When buffer empty transfer end interrupt is generated it moves to interrupt processing routine If transmit data is left read them from storage area then write into TxDq and update transmit data pointer and number of transmit data If no more transmit data clear MDmn0 bit if it s set If not finish MDmn0 1 Sets communication c...

Page 463: ...r detection flag FEFmn Parity error detection flag PEFmn Overrun error detection flag OVFmn Transfer data length 7 8 or 9 bits Transfer rate Max fMCK 6 bps SDRmn 15 9 2 or more Min fCLK 2 215 128 bps Note Data phase Non reverse output default high level Reverse output default low level Parity bit The following selectable No parity bit no parity check No parity judgment 0 parity Even parity check O...

Page 464: ... 2 1 0 SCRmn TXEmn 0 RXEmn 1 DAPmn 0 CKPmn 0 0 EOCmn 0 1 PTCmn1 0 1 PTCmn0 0 1 DIRmn 0 1 0 SLCmn1 0 SLCmn0 1 0 1 DLSmn1 0 1 DLSmn0 0 1 Setting of parity bit 00B No parity check Selection of data transfer sequence 0 Inputs outputs data with MSB first 1 Inputs outputs data with LSB first Setting of data length 01B No parity judgment 10B Even parity check 11B Odd parity check d Serial data register m...

Page 465: ...in this mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm0 g Serial channel start register m SSm Sets only the bits of the target channel is 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSm1 0 1 SSm0 Remarks 1 m Unit number m 0 n Channel number n 1 mn 01 r Channel number r 0 q UART number q 0 2 Setting is fixed in the UART reception mode ...

Page 466: ...t must stop do not wait Yes No Reset the serial array unit by stopping the clock supply to it Setting the PER0 register Essential Selective Selective Starting initial setting Setting the PER0 register Setting the SPSm register Setting the SMRmn and SMRmr registers Setting the SCRmn register Setting the SDRmn register Writing to the SSm register Completing initial setting Release the serial array u...

Page 467: ...e target channel to 1 and set the Semn bit to 1 to enable operation Become wait for start bit detection Selective Selective Selective Selective Essential Completing resumption setting Clearing error flag If the FEF PEF and OVF flags remain set clear them using serial flag clear trigger register mn SIRmn Selective Setting port Enable data input of the target channel by setting a port register and a...

Page 468: ... operation Shift operation Shift operation ST ST P ST P SP SP SP SSmn SEmn SDRmn STmn RxDq pin Shift register mn INTSRq TSFmn Data reception Data reception Data reception Receive data 3 Receive data 2 Receive data 1 Receive data 3 Receive data 2 Receive data 1 Remark m Unit number m 0 n Channel number n 1 mn 01 r Channel number r 0 q UART number q 0 ...

Page 469: ... communication data are optionally set on the internal RAM by the software Enables interrupt Starting reception if start bit is detected Transfer end interrupt When receive complete transfer end interrupt is generated Indicating normal reception Reading receive data from the SDRmn 7 0 bits RXDq register 8 bits or the SDRmn 8 0 bits 9 bits Yes No RETI Reception completed Check the number of communi...

Page 470: ...high speed on chip oscillator clock fIH is selected for fCLK 2 The transfer rate in the SNOOZE mode is only 4800 bps 3 When SWCm 1 UARTq can be used only when the reception operation is started in the STOP mode When used simultaneously with another SNOOZE mode function or interrupt if the reception operation is started in a state other than the STOP mode such as those given below data may not be r...

Page 471: ... 0 Note fCLK 23 105 2 27 1 53 6 MHz 1 0 Note fCLK 23 79 1 60 2 19 4 MHz 1 0 Note fCLK 22 105 2 27 1 53 3 MHz 1 0 Note fCLK 22 79 1 60 2 19 2 MHz 1 0 Note fCLK 2 105 2 27 1 54 1 MHz 1 0 Note fCLK 105 2 27 1 57 Note When the accuracy of the clock frequency of the high speed on chip oscillator is 1 5 the permissible range becomes smaller as shown below In the case of fIH 1 5 perform Maximum permissib...

Page 472: ...eive data 2 Receive data 1 Shift operation Shift operation Data reception Data reception Shift register 01 Clock request signal internal signal ReadNote RxD0 pin Note Read the received data when SWCm is 1 Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes set the STm1 bit to 1 clear the SEm1 bit and stop the operation And after completion the recei...

Page 473: ... status Normal operation STOP mode SNOOZE mode Normal operation Clock request signal internal signal Shift register 01 Receive data 1 Receive data 1 Receive data 2 Receive data 2 Shift operation Shift operation Data reception Data reception EOC01 RxD0 pin Note Only read received data while SWCm 1 Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes s...

Page 474: ... status SAU default setting Clear interrupt request flag XXIF reset interrupt mask XXMK and set interrupt enable EI 1 Enable interrupt RxDq edge detected Entered the SNOOZE mode Clock supply UART receive operation Transfer end interrupt INTSRq or error interrupt INTSREq generated Normal operation Normal operation STOP mode SNOOZE mode Writing 1 to the STmn bit Clear SWCm bit to 0 Reset SNOOZE mode...

Page 475: ...data 1 Receive data 2 Receive data 2 Receive data 1 Shift operation Shift operation Data reception Data reception Shift register 01 Clock request signal internal signal ReadNote EOC01 Note Only read received data while SWCm 1 Cautions 1 Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes set the STm1 bit to 1 clear the SEm1 bit and stop the operation And af...

Page 476: ...t set Channel 1 is specified for UART reception EOCmn set to enable error interrupt SAU default setting Setting SSCm register SWCm 1 SSECm 1 Writing 1 to the SSmn bit SEmn 1 SNOOZE mode setting error interrupt generation stop Communication wait status Clear interrupt request flag XXIF reset interrupt mask XXMK and set interrupt disable EI 0 Setting interrupt Setting SSCm register SWCm 0 SSECm 0 Re...

Page 477: ...ZE mode while SSECm is set to 1 no overrun errors occur Therefore when using the SNOOZE mode read bits 7 to 0 RxDq of the SDRm1 register before switching to the STOP mode Remarks 1 1 to 9 in the figure correspond to 1 to 9 in Figure 11 117 Timing Chart of SNOOZE Mode Operation Abnormal Operation 2 2 m 0 q 0 ...

Page 478: ...frequency of target channel SDRmn 15 9 1 2 bps Caution Setting serial data register mn SDRmn SDRmn 15 9 0000000B 0000001B is prohibited Remarks 1 When UART is used the value of SDRmn 15 9 is the value of bits 15 to 9 of the SDRmn register 0000010B to 1111111B and therefore is 2 to 127 2 m Unit number m 0 n Channel number n 0 1 mn 00 01 The operation clock fMCK is determined by serial clock select ...

Page 479: ... kHz X X X X 1 1 1 0 fCLK 214 1 95 kHz X X X X 1 1 1 1 fCLK 215 977 Hz 1 0 0 0 0 X X X X fCLK 32 MHz 0 0 0 1 X X X X fCLK 2 16 MHz 0 0 1 0 X X X X fCLK 22 8 MHz 0 0 1 1 X X X X fCLK 23 4 MHz 0 1 0 0 X X X X fCLK 24 2 MHz 0 1 0 1 X X X X fCLK 25 1 MHz 0 1 1 0 X X X X fCLK 26 500 kHz 0 1 1 1 X X X X fCLK 27 250 kHz 1 0 0 0 X X X X fCLK 28 125 kHz 1 0 0 1 X X X X fCLK 29 62 5 kHz 1 0 1 0 X X X X fCLK...

Page 480: ...baud rate at fCLK 32 MHz UART Baud Rate Target Baud Rate fCLK 32 MHz Operation Clock fMCK SDRmn 15 9 Calculated Baud Rate Error from Target Baud Rate 300 bps fCLK 29 103 300 48 bps 0 16 600 bps fCLK 28 103 600 96 bps 0 16 1200 bps fCLK 27 103 1201 92 bps 0 16 2400 bps fCLK 26 103 2403 85 bps 0 16 4800 bps fCLK 25 103 4807 69 bps 0 16 9600 bps fCLK 24 103 9615 38 bps 0 16 19200 bps fCLK 23 103 1923...

Page 481: ...9 1 Nfr 1 data frame length bits Start bit Data length Parity bit Stop bit Remark m Unit number m 0 n Channel number n 1 mn 01 Figure 11 119 Permissible Baud Rate Range for Reception 1 Data Frame Length 11 Bits FL 1 data frame 11 FL 11 FL min 11 FL max Data frame length of SAU Start bit Bit 0 Bit 1 Bit 7 Parity bit Permissible minimum data frame length Permissible maximum data frame length Stop bi...

Page 482: ...ware Manipulation Hardware Status Remark Reads serial data register mn SDRmn The BFFmn bit of the SSRmn register is set to 0 and channel n is enabled to receive data This is to prevent an overrun error if the next reception is completed during error processing Reads serial status register mn SSRmn Error type is identified and the read value is used to clear error flag Writes serial flag clear trig...

Page 483: ...k SCLAn line and a serial data bus SDAAn line This mode complies with the I2 C bus format and the master device can generated start condition address transfer direction specification data and stop condition data to the slave device via the serial data bus The slave device automatically detects these received status and data by hardware This function can simplify the part of application program tha...

Page 484: ...oller IICA low level width setting register 0 IICWL0 Serial clock wait controller Counter INTIICA0 IICA shift register 0 IICA0 IICCTL00 STT0 SPT0 IICS0 MSTS0 EXC0 COI0 IICS0 MSTS0 EXC0 COI0 IICCTL01 PRS0 fCLK fCLK 2 LREL0WREL0SPIE0 WTIM0 ACKE0 STT0 SPT0 MSTS0 ALD0 EXC0 COI0 TRC0ACKD0 STD0 SPD0 Start condition detector Internal bus STCF0 IICBSY0 STCEN0 IICRSV0 IICA flag register 0 IICF0 WUP0 CLD0 D...

Page 485: ...Master CPU1 Slave CPU1 Address 2 SDA SCL Serial data bus Serial clock VDD VDD SDA SCL SDA SCL SDA SCL Slave CPU3 Address 3 Slave IC Address 4 Slave IC Address N SDAA0 SDAA1 SCLA0 SCLA1 Master CPU0 Slave CPU0 Address 0 IICA0 IICA1 Address 1 RL78 G1P Master CPU2 Slave CPU2 Address 5 SDA SCL Remark The RL78 G1P can communicate supporting two addresses as they have two units of serial interface IICA ...

Page 486: ...e used for both transmission and reception The actual transmit and receive operations can be controlled by writing and reading operations to the IICAn register Cancel the wait state and start data transfer by writing data to the IICAn register during the wait period The IICAn register can be set by an 8 bit memory manipulation instruction Reset signal generation clears IICAn to 00H Figure 12 3 For...

Page 487: ... 5 Serial clock counter This counter counts the serial clocks that are output or input during transmit receive operations and is used to verify that 8 bit data was transmitted or received 6 Interrupt request signal generator This circuit controls the generation of interrupt request signals INTIICAn An I2 C interrupt request is generated by the following two triggers Falling edge of eighth or ninth...

Page 488: ...ates a stop condition when the SPTn bit is set to 1 13 Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions However as the bus status cannot be detected immediately following operation the initial status is set by the STCENn bit Remarks 1 STTn bit Bit 1 of IICA control register n0 IICCTLn0 SPTn bit Bit 0 of IICA control regis...

Page 489: ...tion instruction Reset signal generation clears this register to 00H Figure 12 5 Format of Peripheral Enable Register 0 PER0 Address F00F0H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 PER0 0 IICA1EN ADCEN IICA0EN 0 SAU0EN 0 TAU0EN IICAnEN Control of serial interface IICAn input clock supply 0 Stops input clock supply SFR used by serial interface IICAn cannot be written Serial interface IICAn is in ...

Page 490: ... operations set wait timing and set other I2 C operations The IICCTLn0 register can be set by a 1 bit or 8 bit memory manipulation instruction However set the SPIEn WTIMn and ACKEn bits while IICEn 0 or during the wait period These bits can be set at the same time when the IICEn bit is set from 0 to 1 Reset signal generation clears this register to 00H Remark n 0 1 ...

Page 491: ... conditions are met After a stop condition is detected restart is in master mode An address match or extension code reception occurs after the start condition Condition for clearing LRELn 0 Condition for setting LRELn 1 Automatically cleared after execution Reset Set by instruction WRELnNotes 2 3 Wait cancellation 0 Do not cancel wait 1 Cancel wait This setting is automatically cleared after wait ...

Page 492: ...vice An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit The setting of this bit is valid when the address transfer is completed When in master mode a wait is inserted at the falling edge of the ninth clock during address transfers For a slave device that has received a local address a wait is inserted at the falling edg...

Page 493: ...et timing For master reception Cannot be set to 1 during transfer Can be set to 1 only in the waiting period when the ACKEn bit has been cleared to 0 and slave has been notified of final reception For master transmission A start condition cannot be generated normally during the acknowledge period Set to 1 during the wait period that follows output of the ninth clock Cannot be set to 1 at the same ...

Page 494: ...t clocks note that a stop condition will be generated during the high level period of the ninth clock The WTIMn bit should be changed from 0 to 1 during the wait period following the output of eight clocks and the SPTn bit should be set to 1 during the wait period that follows the output of the ninth clock Once SPTn is set 1 setting it again 1 before the clear condition is met is not allowed Condi...

Page 495: ...reset 00H R Symbol 7 6 5 4 3 2 1 0 IICSn MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn MSTSn Master status check flag 0 Slave device status or communication standby status 1 Master device communication status Condition for clearing MSTSn 0 Condition for setting MSTSn 1 When a stop condition is detected When ALDn 1 arbitration loss Cleared by LRELn 1 exit from communications When the IICEn bit changes ...

Page 496: ...tarting at the falling edge of the first byte s ninth clock Condition for clearing TRCn 0 Condition for setting TRCn 1 Both master and slave When a stop condition is detected Cleared by LRELn 1 exit from communications When the IICEn bit changes from 1 to 0 operation stop Cleared by WRELn 1Note wait cancel When the ALDn bit changes from 0 to 1 arbitration loss Reset When not used for communication...

Page 497: ...ition 0 Stop condition was not detected 1 Stop condition was detected The master device s communication is terminated and the bus is released Condition for clearing SPDn 0 Condition for setting SPDn 1 At the rising edge of the address transfer byte s first clock following setting of this bit and detection of a start condition When the WUPn bit changes from 1 to 0 When the IICEn bit changes from 1 ...

Page 498: ...CENn 0 Cleared by instruction Detection of start condition Reset Condition for setting STCENn 1 Set by instruction STCENn 0 1 After operation is enabled IICEn 1 enable generation of a start condition upon detection of a stop condition After operation is enabled IICEn 1 enable generation of a start condition without detecting a stop condition Initial start enable trigger Condition for clearing IICR...

Page 499: ... see Figure 12 22 Flow When Setting WUPn 1 Clear 0 the WUPn bit after the address has matched or an extension code has been received The subsequent communication can be entered by the clearing 0 WUPn bit The wait must be released and transmit data must be written after the WUPn bit has been cleared 0 The interrupt timing when the address has matched or when an extension code has been received whil...

Page 500: ...en the SDAAn pin is at high level SMCn Operation mode switching 0 Operates in standard mode fastest transfer rate 100 kbps 1 Operates in fast mode fastest transfer rate 400 kbps or fast mode plus fastest transfer rate 1 Mbps DFCn Digital filter operation control 0 Digital filter off 1 Digital filter on Digital filter can be used only in fast mode and fast mode plus In fast mode and fast mode plus ...

Page 501: ...f the time set by the IICWLn register Figure 12 10 Format of IICA Low Level Width Setting Register n IICWLn Address F0232H IICWL0 F023AH IICWL1 After reset FFH R W Symbol 7 6 5 4 3 2 1 0 IICWLn 12 3 7 IICA high level width setting register n IICWHn This register is used to set the high level width of the SCLAn pin signal that is output by serial interface IICA The IICWHn register can be set by an ...

Page 502: ...IICEn bit bit 7 of IICA control register n0 IICCTLn0 to 1 before setting the output mode because the P60 SCLA0 SCLA1 and P61 SDAA0 SDAA1 pins output a low level fixed when the IICEn bit is 0 The PM6 register can be set by a 1 bit or 8 bit memory manipulation instruction Reset signal generation sets this register to FFH Figure 12 12 Format of Port Mode Register 6 PM6 PM60 PM61 1 1 1 1 1 1 P6n pin I...

Page 503: ...e devices Input is Schmitt input 2 SDAAn This pin is used for serial data input and output This pin is an N ch open drain output for both master and slave devices Input is Schmitt input Since outputs from the serial clock line and the serial data bus line are N ch open drain outputs an external pull up resistor is required Figure 12 13 Pin Configuration Diagram Master device Clock output Clock inp...

Page 504: ...IICWLn 0 52 Transfer clock fCLK IICWHn 0 48 Transfer clock tR tF fCLK When the normal mode IICWLn 0 47 Transfer clock fCLK IICWHn 0 53 Transfer clock tR tF fCLK When the fast mode plus IICWLn 0 50 Transfer clock fCLK IICWHn 0 50 Transfer clock tR tF fCLK 2 Setting IICWLn and IICWHn registers on slave side The fractional parts of all setting values are truncated When the fast mode IICWLn 1 3 s fCLK...

Page 505: ...ration frequency of the operation clock of the serial interface IICA is 20 MHz Max If the fCLK exceeds 20 MHz set the clock to fCLK 2 by setting the PRSn bit of IICCTLn1 register to 1 Remarks 1 Calculate the rise time tR and fall time tF of the SDAAn and SCLAn signals separately because they differ depending on the pull up resistance and wire load 2 IICWLn IICA low level width setting register n I...

Page 506: ...y it is output by the device that receives 8 bit data The serial clock SCLAn is continuously output by the master device However in the slave device the SCLAn pin low level period can be extended and a wait can be inserted 12 5 1 Start conditions A start condition is met when the SCLAn pin is at high level and the SDAAn pin changes from high level to low level The start conditions for the SCLAn pi...

Page 507: ...other than a local address or extension code is received during slave device operation Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in 12 5 3 Transfer direction specification are written to the IICA shift register n IICAn The received addresses are written to the IICAn register The slave address is assigned to the higher 7 bits of...

Page 508: ...register is set by the data of the eighth bit that follows 7 bit address information Usually set the ACKEn bit to 1 for reception TRCn 0 If a slave can receive no more data during reception TRCn 0 or does not require the next data item then the slave must inform the master by clearing the ACKEn bit to 0 that it will not receive any more data When the master does not require the next data item duri...

Page 509: ...evice generates to the slave device when serial transfer has been completed When the device is used as a slave stop conditions can be detected Figure 12 19 Stop Condition SCLAn SDAAn H A stop condition is generated when bit 0 SPTn of IICA control register n0 IICCTLn0 is set to 1 When the stop condition is detected bit 0 SPDn of the IICA status register n IICSn is set to 1 and INTIICAn is generated...

Page 510: ...er and slave devices the next data transfer can begin Figure 12 20 Wait 1 2 1 When master device has a nine clock wait and slave device has an eight clock wait master transmits slave receives and ACKEn 1 Master IICAn SCLAn Slave IICAn SCLAn ACKEn Transfer lines SCLAn SDAAn 6 7 8 9 1 2 3 Master returns to high impedance but slave is in wait state low level Wait after output of ninth clock IICA0 dat...

Page 511: ...ccording to previously set ACKEn value Remark ACKEn Bit 2 of IICA control register n0 IICCTLn0 WRELn Bit 5 of IICA control register n0 IICCTLn0 A wait may be automatically generated depending on the setting of bit 3 WTIMn of IICA control register n0 IICCTLn0 Normally the receiving side cancels the wait state when bit 5 WRELn of the IICCTLn0 register is set to 1 or when FFH is written to the IICA s...

Page 512: ...er to 1 To generate a restart condition after canceling a wait state set bit 1 STTn of the IICCTLn0 register to 1 To generate a stop condition after canceling a wait state set bit n SPTn of the IICCTLn0 register to 1 Execute the canceling processing only once for one wait state If for example data is written to the IICAn register after canceling a wait state by setting the WRELn bit to 1 an incorr...

Page 513: ... and extension code is not received neither INTIICAn nor a wait occurs Remark The numbers in the table indicate the number of the serial clock s clock signals Interrupt requests and wait control are both synchronized with the falling edge of these clock signals 1 During address transmission reception Slave device operation Interrupt and wait timing are determined depending on the conditions descri...

Page 514: ...n SVAn is not affected 2 The settings below are specified if 11110xx0 is transferred from the master by using a 10 bit address transfer when the SVAn register is set to 11110xx0 Note that INTIICAn occurs at the falling edge of the eighth clock Higher four bits of data match EXCn 1 Seven bits of data match COIn 1 Remark EXCn Bit 5 of IICA status register n IICSn COIn Bit 4 of IICA status register n...

Page 515: ...set 1 via the timing by which the arbitration loss occurred and the SCLAn and SDAAn lines are both set to high impedance which releases the bus The arbitration loss is detected based on the timing of the next interrupt request the eighth or ninth clock when a stop condition is detected etc and the ALDn 1 setting that has been made by software For details of interrupt request timing see 12 5 8 Inte...

Page 516: ...level while attempting to generate a restart condition At falling edge of eighth or ninth clock following byte transferNote 1 When stop condition is detected while attempting to generate a restart condition When stop condition is generated when SPIEn 1 Note 2 When data is at low level while attempting to generate a stop condition At falling edge of eighth or ninth clock following byte transferNote...

Page 517: ...ity that an arbitration loss may change the master device which has generated a start condition to a slave device To use the wakeup function in the STOP mode set the WUPn bit to 1 Addresses can be received regardless of the operation clock An interrupt request signal INTIICAn is also generated when a local address and extension code have been received Operation returns to normal operation by using...

Page 518: ... to the operation to be executed after checking the operation state of serial interface IICA STOP mode state No Yes WUPn 0 Wait Reading IICSn INTIICAn 1 Use the following flows to perform the processing to release the STOP mode other than by an interrupt request INTIICAn generated from serial interface IICA Master device operation Flow shown in Figure 12 24 Slave device operation Same as the flow ...

Page 519: ...utes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA No Yes Releases STOP mode by an interrupt other than INTIICAn Generates a STOP condition or selects as a slave device START WUPn 1 SPIEn 1 Releasing STOP mode STOP instruction WUPn 0 Reading IICSn INTIICAn 1 STOP mode state Waits for 5 clocks Wait Remark n 0 1 ...

Page 520: ...f the IICCTLn0 register was set to 1 and it was detected by generation of an interrupt request signal INTIICAn that the bus was released detection of the stop condition then the device automatically starts communication as the master Data written to the IICAn register before the stop condition is detected is invalid When the STTn bit has been set to 1 the operation mode as start condition or as co...

Page 521: ...f IICA control register n0 IICCTLn0 STDn Bit 1 of IICA status register n IICSn SPDn Bit 0 of IICA status register n IICSn Communication reservations are accepted via the timing shown in Figure 12 26 After bit 1 STDn of the IICA status register n IICSn is set to 1 a communication reservation can be made by setting bit 1 STTn of IICA control register n0 IICCTLn0 to 1 before a stop condition is detec...

Page 522: ...te 1 by software Confirmation of communication reservation Clear user flag IICAn write operation Notes 1 The wait time is calculated as follows IICWLn setting value IICWHn setting value 4 tF 2 fCLK clocks 2 The communication reservation operation executes a write to the IICA shift register n IICAn when a stop condition interrupt request occurs Remarks 1 STTn Bit 1 of IICA control register n0 IICCT...

Page 523: ...ated The following two statuses are included in the status where bus is not used When arbitration results in neither master nor slave operation When an extension code is received and slave operation is disabled ACK is not returned and the bus was released by setting bit 6 LRELn of the IICCTLn0 register to 1 and saving communication To confirm whether the start condition was generated or request wa...

Page 524: ...w and the SCLAn pin is high the macro of I2 C recognizes that the SDAAn pin has gone low detects a start condition If the value on the bus at this time can be recognized as an extension code ACK is returned but this interferes with other I2 C communications To avoid this start I2 C in the following sequence 1 Clear bit 4 SPIEn of the IICCTLn0 register to 0 to disable generation of an interrupt req...

Page 525: ...released state This flowchart is broadly divided into the initial settings communication waiting and communication processing The processing when the RL78 G1P looses in arbitration and is specified as the slave is omitted here and only the processing as the master is shown Execute the initial settings at startup to take part in a communication Then wait for the communication request as the master ...

Page 526: ... mode register 6 PM6 Sets a transfer clock Sets a local address Sets a start condition Prepares for starting communication generates a start condition Starts communication specifies an address and transfer direction Waits for detection of acknowledge Waits for data transmission Starts transmission Communication processing Initial setting Starts reception Waits for data reception INTIICAn interrupt...

Page 527: ... generates a stop condition Waits for detection of the stop condition No Yes Yes No INTIICAn interrupt occurs INTIICAn interrupt occurs Yes No Yes No SPDn 1 Yes No Slave operation No INTIICAn interrupt occurs Yes No 1 B SPIEn 0 Yes No Waits for a communication request Waits for a communication Initial setting IICCTLn0 1XX111XXB IICEn 1 IICCTLn0 0XX111XXB ACKEn WTIMn SPIEn 1 Setting of the port use...

Page 528: ...upt occurs Yes Yes No No A C STTn 1 WaitNote Slave operation Yes IICBSYn 0 EXCn 1 or COIn 1 Prepares for starting communication generates a start condition Disables reserving communication Enables reserving communication Waits for bus release Detects a stop condition No No INTIICAn interrupt occurs Yes Yes No Yes STCFn 0 No B D C D Communication processing Communication processing Note The wait ti...

Page 529: ... Yes ACKDn 1 No Yes No C 2 Yes MSTSn 1 No Yes Transfer end No Yes ACKDn 1 No 2 Yes MSTSn 1 No 2 Waits for detection of ACK Yes No INTIICAn interrupt occurs Yes MSTSn 1 No C 2 Yes EXCn 1 or COIn 1 No 1 2 SPTn 1 STTn 1 Slave operation END Communication processing Communication processing Remarks 1 Conform to the specifications of the product that is communicating with respect to the transmission and...

Page 530: ... and passing them to the main processing instead of INTIICAn 1 Communication mode flag This flag indicates the following two communication statuses Clear mode Status in which data communication is not performed Communication mode Status in which data communication is performed from valid address detection to stop condition detection no detection of ACK from master address mismatch 2 Ready flag Thi...

Page 531: ... Yes Yes No No No No No No WRELn 1 ACKDn 1 No Yes No Yes No START Communication mode flag 1 Communication mode flag 1 Communication direction flag 1 Ready flag 1 Communication direction flag 1 Reading IICAn Clearing ready flag Clearing ready flag Communication direction flag 1 Clearing communication mode flag WRELn 1 Writing IICAn SVAn XXH Sets a local address IICWLn IICWHn XXH Selects a transfer ...

Page 532: ... flag is set Processing returns from the interrupt with the I2 C bus remaining in the wait state Remark 1 to 3 above correspond to 1 to 3 in Figure 12 31 Slave Operation Flowchart 2 Figure 12 31 Slave Operation Flowchart 2 Yes Yes Yes No No No INTIICAn generated Set ready flag Interrupt servicing completed SPDn 1 STDn 1 COIn 1 Communication direction flag TRCn Set communication mode flag Clear rea...

Page 533: ...1B Note To generate a stop condition set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 1 IICSn 1000 110B 2 IICSn 1000 100B 3 IICSn 1000 00B Sets the SPTn bit to 1 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R ...

Page 534: ... the INTIICAn interrupt request signal 2 Clear the WTIMn bit to 0 to restore the original setting 3 To generate a stop condition set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 1 IICSn 1000 110B 2 IICSn 1000 00B Sets the STTn bit to 1 3 IICSn 1000 110B 4 IICSn 1000 00B S...

Page 535: ...enerate a stop condition set the WTIMn bit to 1 and change the timing for generating the INTIICAn interrupt request signal Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 1 IICSn 1010 110B 2 IICSn 1010 100B 3 IICSn 1010 00B Sets the SPTn bit to 1 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to ...

Page 536: ...0B 2 IICSn 0001 000B 3 IICSn 0001 000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 1 IICSn 0001 110B 2 IICSn 0001 100B 3 IICSn 0001 00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1...

Page 537: ...Sn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 after restart matches with SVAn 1 IICSn 0001 110B 2 IICSn 0001 00B 3 IICSn 0001 110B 4 IICSn 0001 00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 5 2 1 ST AD6 to AD0 R W ACK D7 to D...

Page 538: ...B Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 after restart does not match address extension code 1 IICSn 0001 110B 2 IICSn 0001 00B 3 IICSn 0010 010B 4 IICSn 0010 110B 5 IICSn 0010 00B 6 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 5 2 1 ST...

Page 539: ...ICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 after restart does not match address not extension code 1 IICSn 0001 110B 2 IICSn 0001 00B 3 IICSn 00000 10B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 2 1 ST AD6 to AD0 R W ACK ...

Page 540: ...p i When WTIMn 0 1 IICSn 0010 010B 2 IICSn 0010 000B 3 IICSn 0010 000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 1 IICSn 0010 010B 2 IICSn 0010 110B 3 IICSn 0010 100B 4 IICSn 0010 00B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 ST AD6 t...

Page 541: ...B Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 after restart matches SVAn 1 IICSn 0010 010B 2 IICSn 0010 110B 3 IICSn 0010 00B 4 IICSn 0001 110B 5 IICSn 0001 00B 6 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 5 2 1 ST AD6 to AD0 R W ACK D7 to...

Page 542: ...ays generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 after restart extension code reception 1 IICSn 0010 010B 2 IICSn 0010 110B 3 IICSn 0010 00B 4 IICSn 0010 010B 5 IICSn 0010 110B 6 IICSn 0010 00B 7 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 5 2 1 ST AD6 to...

Page 543: ...1B Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 after restart does not match address not extension code ST AD6 to AD0 R W ACK D7 to D0 AD6 to AD0 ACK ACK SP ST R W D7 to D0 ACK 3 4 5 2 1 1 IICSn 0010 010B 2 IICSn 0010 110B 3 IICSn 0010 00B 4 IICSn 00000 10B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 ...

Page 544: ... slave after arbitration loss When the device is used as a master in a multi master system read the MSTSn bit each time interrupt request signal INTIICAn has occurred to check the arbitration result a When arbitration loss occurs during transmission of slave address data i When WTIMn 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICSn 0101 110B 2 IICSn 0001 000B 3 IICSn 0001 000B ...

Page 545: ...00B 3 IICSn 0001 00B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care b When arbitration loss occurs during transmission of extension code i When WTIMn 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 4 2 1 1 IICSn 0110 010B 2 IICSn 0010 000B 3 IICSn 0010 000B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ...

Page 546: ...Don t care 6 Operation when arbitration loss occurs no communication after arbitration loss When the device is used as a master in a multi master system read the MSTSn bit each time interrupt request signal INTIICAn has occurred to check the arbitration result a When arbitration loss occurs during transmission of slave address data when WTIMn 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 2 ...

Page 547: ...D0 ACK ACK SP 2 1 1 IICSn 0110 010B Sets LRELn 1 by software 2 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care c When arbitration loss occurs during transmission of data i When WTIMn 0 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 2 1 1 IICSn 10001110B 2 IICSn 01000000B 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Remark n 0 1 ...

Page 548: ...en SPIEn 1 d When loss occurs due to restart condition during data transfer i Not extension code Example unmatches with SVAn 1 IICSn 1000 110B 2 IICSn 01000110B 3 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care m 6 to 0 Remark n 0 1 ST AD6 to AD0 R W ACK D7 to Dm AD6 to AD0 ACK SP ST R W D7 to D0 ACK 3 2 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK ACK SP 3 2 1 ...

Page 549: ...00001B Remark Always generated Generated only when SPIEn 1 Don t care m 6 to 0 e When loss occurs due to stop condition during data transfer 1 IICSn 10000110B 2 IICSn 01000001B Remark Always generated Generated only when SPIEn 1 Don t care m 6 to 0 Remark n 0 1 ST AD6 to AD0 R W ACK D7 to Dm SP 2 1 ST AD6 to AD0 R W ACK D7 to Dm AD6 to AD0 ACK SP ST R W D7 to D0 ACK 3 2 1 ...

Page 550: ...00B Clears the WTIMn bit to 0 4 IICSn 01000000B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 1 IICSn 1000 110B 2 IICSn 1000 100B Sets the STTn bit to 1 3 IICSn 01000100B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK SP ACK D7 to D0 ACK STTn 1 3 4 2 1 ST AD...

Page 551: ... 1000 000B Sets the WTIMn bit to 1 3 IICSn 1000 00B Sets the STTn bit to 1 4 IICSn 01000001B Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 1 IICSn 1000 110B 2 IICSn 1000 00B Sets the STTn bit to 1 3 IICSn 01000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to D0 ACK SP STTn 1 2 3 1 ST AD6 to AD0 R W ACK D7 ...

Page 552: ...B Clears the WTIMn bit to 0 4 IICSn 01000100B 5 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care ii When WTIMn 1 1 IICSn 1000 110B 2 IICSn 1000 100B Sets the SPTn bit to 1 3 IICSn 01000100B 4 IICSn 00000001B Remark Always generated Generated only when SPIEn 1 Don t care Remark n 0 1 ST AD6 to AD0 R W ACK D7 to D0 D7 to D0 ACK SP ACK D7 to D0 ACK SPTn 1 3 4 2 1 ST AD6 ...

Page 553: ...e TRCn bit bit 3 of the IICA status register n IICSn which specifies the data transfer direction and then starts serial communication with the slave device Figures 12 32 and 12 33 show timing charts of the data communication The IICA shift register n IICAn s shift operation is synchronized with the falling edge of the serial clock SCLAn The transmit data is transferred to the SO latch and is outpu...

Page 554: ...ol MSTSn communication status TRCn transmit receive WRELn wait cancellation INTIICAn interrupt Master side Bus line Slave side Slave address L L H L H H H L AD5 AD4 AD3 AD2 AD1 AD0 WTIMn 8 or 9 clock wait Note 1 Start condition D17 AD6 Note 2 Note 3 5 1 4 3 6 Wait state by slave device Wait state by master and slave devices Notes 1 Write data to IICAn not setting the WRELn bit in order to cancel a...

Page 555: ...INTIICAn end of address transmission at the falling edge of the 9th clock The slave device whose address matched the transmitted slave address sets a wait status SCLAn 0 and issues an interrupt INTIICAn address match Note 5 The master device writes the data to transmit to the IICAn register and releases the wait status that it set by the master device 6 If the slave device releases the wait status...

Page 556: ...ata line IICAn STDn ST detection SPDn SP detection ACKDn ACK detection WTIMn 8 or 9 clock wait ACKEn ACK control MSTSn communication status TRCn transmit receive WRELn wait cancellation INTIICAn interrupt W ACK Master side Bus line Slave side H H L H L L L H H L L D16 D15 D14 D13 D12 D11 D10 D17 D27 ACK H Note 2 10 6 7 8 3 4 Note 1 Note 1 9 5 Note 2 Wait state by slave device Wait state by master ...

Page 557: ...etected by the master device ACKDn 1 at the rising edge of the 9th clock 8 The master device and slave device set a wait status SCLAn 0 at the falling edge of the 9th clock and both the master device and slave device issue an interrupt INTIICAn end of transfer 9 The master device writes the data to transmit to the IICAn register and releases the wait status that it set by the master device 10 The ...

Page 558: ...ACKEn ACK control MSTSn communication status TRCn transmit receive WRELn wait cancellation INTIICAn interrupt D150 D167 Bus line Slave side L L H H L L H H L ACK ACK Note 1 Stop condition 14 9 Note 2 8 12 7 11 15 10 13 Note 3 Note 3 Wait state by master device Wait state by slave device Wait state by master and slave devices Notes 1 Write data to IICAn not setting the WRELn bit in order to cancel ...

Page 559: ... to the master device The ACK is detected by the master device ACKDn 1 at the rising edge of the 9th clock 12 The master device and slave device set a wait status SCLAn 0 at the falling edge of the 9th clock and both the master device and slave device issue an interrupt INTIICAn end of transfer 13 The slave device reads the received data and releases the wait status WRELn 1 14 By the master device...

Page 560: ...K detection WTIMn 8 or 9 clock wait ACKEn ACK control MSTSn communication status TRCn transmit receive WRELn wait cancellation INTIICAn interrupt Master side Bus line Slave side Slave address D13 ACK i L H H L H Restart condition D12 D11 D10 AD5 AD4 AD3 AD2 AD1 ii iii 7 8 Note 2 Note 1 Wait state by master device Wait state by slave device Wait state by master and slave devices Notes 1 Make sure t...

Page 561: ...at the falling edge of the 9th clock and both the master device and slave device issue an interrupt INTIICAn end of transfer i The slave device reads the received data and releases the wait status WRELn 1 ii The start condition trigger is set again by the master device STTn 1 and a start condition i e SCLAn 1 changes SDAAn from 1 to 0 is generated once the bus clock line goes high SCLAn 1 and the ...

Page 562: ...t ACKEn ACK control MSTSn communication status TRCn transmit receive WRELn wait cancellation INTIICAn interrupt Master side Bus line Slave side Slave address L L H H H L AD5 AD4 AD3 AD2 AD1 AD0 Start condition Note 2 Note 1 Note 3 2 5 1 7 3 4 6 Wait state by master device Wait state by slave device Wait state by master and slave devices Notes 1 For releasing wait state during reception of a master...

Page 563: ...g edge of the 9th clock The slave device whose address matched the transmitted slave address sets a wait status SCLAn 0 and issues an interrupt INTIICAn address match Note 5 The timing at which the master device sets the wait status changes to the 8th clock WTIMn 0 6 The slave device writes the data to transmit to the IICAn register and releases the wait status that it set by the slave device 7 Th...

Page 564: ...TDn ST detection SPDn SP detection ACKDn ACK detection WTIMn 8 or 9 clock wait ACKEn ACK control MSTSn communication status TRCn transmit receive WRELn wait cancellation INTIICAn interrupt R ACK ACK Master side Bus line Slave side H H L H L L H L H L L D17 D16 D15 D14 D13 D12 D11 D10 D27 Note 1 Note 1 5 7 9 Note 2 Note 2 4 8 11 10 12 6 3 Wait state by master device Wait state by slave device Wait ...

Page 565: ...transfer Because of ACKEn 1 in the master device the master device then sends an ACK by hardware to the slave device 9 The master device reads the received data and releases the wait status WRELn 1 10 The ACK is detected by the slave device ACKDn 1 at the rising edge of the 9th clock 11 The slave device set a wait status SCLAn 0 at the falling edge of the 9th clock and the slave device issue an in...

Page 566: ...TIICAn interrupt D150 Master side Bus line Slave side H L H L L L ACK NACK D167 D166 D165 D164 D163 D162 D161 D160 Stop condition Note 1 Note 1 Note 3 Note2 Notes 1 4 Note 4 14 9 8 11 10 12 13 16 19 15 17 18 Wait state by master device Wait state by slave device Wait state by master and slave devices Notes 1 To cancel a wait state write FFH to IICAn or set the WRELn bit 2 Make sure that the time b...

Page 567: ...it status to the 9th clock WTIMn 1 15 If the master device releases the wait status WRELn 1 the slave device detects the NACK ACK 0 at the rising edge of the 9th clock 16 The master device and slave device set a wait status SCLAn 0 at the falling edge of the 9th clock and both the master device and slave device issue an interrupt INTIICAn end of transfer 17 When the master device issues a stop con...

Page 568: ...ol using communication timer and A D can also be realized 13 1 Functions of DMA Controller Number of DMA channels 2 channels Transfer unit 8 or 16 bits Maximum transfer unit 1024 times Transfer type 2 cycle transfer One transfer is processed in 2 clocks and the CPU stops during that processing Transfer mode Single transfer mode Transfer request Selectable from the following peripheral hardware int...

Page 569: ... address register n DSAn This is an 8 bit register that is used to set an SFR address that is the transfer source or destination of DMA channel n Set the lower 8 bits of the SFR addresses FFF00H to FFFFFH This register is not automatically incremented but fixed to a specific value In the 16 bit transfer mode the least significant bit is ignored and is treated as an even address The DSAn register c...

Page 570: ...dress has been transferred the DRAn register stops with the value of the last address 1 in the 8 bit transfer mode and the last address 2 in the 16 bit transfer mode In the 16 bit transfer mode the least significant bit is ignored and is treated as an even address The DRAn register can be read or written in 8 bit or 16 bit units However it cannot be written during DMA transfer Reset signal generat...

Page 571: ...r reset 0000H R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DBCn 0 0 0 0 0 0 n 0 1 DBCn 9 0 Number of times of transfer when DBCn is written Remaining number of times of transfer when DBCn is read 000H 1024 Completion of transfer or waiting for 1024 times of DMA transfer 001H 1 Waiting for remaining one time of DMA transfer 002H 2 Waiting for remaining two times of DMA transfer 003H 3 Waiting for rema...

Page 572: ...UH0895EJ0100 Rev 1 00 553 Nov 29 2019 13 3 Registers Controlling DMA Controller DMA controller is controlled by the following registers DMA mode control register n DMCn DMA operation control register n DRCn Remark n DMA channel number n 0 1 ...

Page 573: ...eration 1 DMA transfer is started when DMA operation is enabled DENn 1 DMA transfer is performed once by writing 1 to the STGn bit when DMA operation is enabled DENn 1 When this bit is read 0 is always read DRSn Selection of DMA transfer direction 0 SFR to internal RAM 1 Internal RAM to SFR DSn Specification of transfer data size for DMA transfer 0 8 bits 1 16 bits DWAITnNote 2 Pending of DMA tran...

Page 574: ...nversion end interrupt 0 1 0 INTTM00 End of timer channel 00 count or capture end interrupt 0 1 1 INTTM01 End of timer channel 01 count or capture end interrupt 1 0 0 INTTM02 End of timer channel 02 count or capture end interrupt 1 0 1 INTTM03 End of timer channel 03 count or capture end interrupt 1 1 0 INTSR0 INTCSI01 UART0 transmission transfer end or buffer empty interrupt CSI00 transfer end or...

Page 575: ...a DMA trigger when DSTn 1 after DMA operation is enabled DENn 1 DSTn DMA transfer mode flag 0 DMA transfer of DMA channel n is completed 1 DMA transfer of DMA channel n is not completed still under execution DMAC waits for a DMA trigger when DSTn 1 after DMA operation is enabled DENn 1 When a software trigger STGn or the start source trigger set by the IFCn2 to IFCn0 bits is input DMA transfer is ...

Page 576: ...address a RAM address the number of times of transfer and a transfer mode of DMA transfer to DMA SFR address register n DSAn DMA RAM address register n DRAn DMA byte count register n DBCn and DMA mode control register n DMCn 3 The DMA controller waits for a DMA trigger when DSTn 1 Use 81H to write with an 8 bit manipulation instruction 4 When a software trigger STGn or a start source trigger speci...

Page 577: ...ed by 2 to SFR fixed address By using these transfer modes up to 1024 bytes of data can be consecutively transferred by using the serial interface data resulting from A D conversion can be consecutively transferred and port data can be scanned at fixed time intervals by using a timer 13 4 3 Termination of DMA transfer When DBCn 00H and DMA transfer is completed the DSTn bit is automatically cleare...

Page 578: ...utive transmission is shown below Consecutive transmission of CSI00 256 bytes DMA channel 0 is used for DMA transfer DMA start source INTCSI00 software trigger STG0 only for the first start source Interrupt of CSI00 is specified by IFC02 to IFC00 0110B Transfers FFB00H to FFBFFH 256 bytes of RAM to FFF10H of the data register SIO00 of CSI Remark IFC02 to IFC00 Bits 2 to 0 of DMA mode control regis...

Page 579: ...t to 0 for details see 13 5 5 Forced termination by software The fist trigger for consecutive transmission is not started by the interrupt of CSI In this example it start by a software trigger CSI transmission of the second time and onward is automatically executed A DMA interrupt INTDMA0 occurs when the last transmit data has been written to the data register Setting for CSI transfer DEN0 1 DSA0 ...

Page 580: ...A D conversion results is shown below Consecutive capturing of A D conversion results DMA channel 1 is used for DMA transfer DMA start source INTAD Interrupt of A D is specified by IFC12 to IFC10 0001B Transfers FFF1EH and FFF1FH 2 bytes of the 12 bit A D conversion result register ADCR to 512 bytes of FFCE0H to FFEDFH of RAM Remark IFC12 to IFC10 Bits 2 to 0 of DMA mode control registers 1 DMC1 ...

Page 581: ...Writing the DEN1 flag is enabled only when DST1 0 To terminate a DMA transfer without waiting for occurrence of the interrupt of DMA1 INTDMA1 set the DST1 bit to 0 and then the DEN1 bit to 0 for details see 13 5 5 Forced termination by software Hardware operation DEN1 1 DSA1 1EH DRA1 FCE0H DBC1 0100H DMC1 21H DST1 1 Starting A D conversion DEN1 0 RETI End INTDMA1 occurs DST1 0Note INTAD occurs DMA...

Page 582: ...g for UART consecutive reception ACK transmission is shown below Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception DMA channel 0 is used for DMA transfer DMA start source Software trigger DMA transfer on occurrence of an interrupt is disabled Transfers FFF12H of UART receive data register 0 RXD0 to 64 bytes of FFE00H to FFE3FH of RAM ...

Page 583: ... ACK Transmission Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed Writing the DEN0 flag is enabled only when DST0 0 To terminate a DMA transfer without waiting for occurrence of the interrupt of DMA0 INTDMA0 set the DST0 bit to 0 and then the DEN0 bit to 0 for details see 13 5 5 Forced termination by software Remark This is an example where a software trigger is u...

Page 584: ...multiple transfer triggers occur for one channel during the pending status only one DMA transfer is executed after the pending status is canceled To output a pulse with a width of 10 clocks of the operating frequency from the P10 pin for example the clock width increases to 12 if a DMA transfer is started midway In this case the DMA transfer can be held pending by setting the DWAITn bit to 1 After...

Page 585: ...actually been cleared to 0 and then set the DENn bit to 0 use DRCn 00H to write with an 8 bit manipulation instruction Set the DSTn bit to 0 use DRCn 80H to write with an 8 bit manipulation instruction by software and then set the DENn bit to 0 use DRCn 00H to write with an 8 bit manipulation instruction two or more clocks after When using two DMA channels To forcibly terminate DMA transfer by sof...

Page 586: ...bly terminating the DMA transfer for one channel if both channels are used transfer for both channels if both channels are used Caution In example 3 the system is not required to wait two clock cycles after the DWAITn bit is set to 1 In addition the system does not have to wait two clock cycles after clearing the DSTn bit to 0 because more than two clock cycles elapse from when the DSTn bit is cle...

Page 587: ...e 3 clocks 10 clocksNote Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles Cautions 1 The above response time does not include the two clock cycles required for a DMA transfer 2 When executing a DMA pending instruction see 13 6 4 the maximum response time is extended by the execution time of that instruction to be held pending 3 Do not specify successiv...

Page 588: ...or exceeds the area of the internal RAM the following operation is performed In mode of transfer from SFR to RAM The data of that address is lost In mode of transfer from RAM to SFR Undefined data is transferred to SFR In either case malfunctioning may occur or damage may be done to the system Therefore make sure that the address is within the internal RAM area other than the general purpose regis...

Page 589: ...he CPU The ELC has the following functions Capable of directly linking event signals from 10 types of peripheral functions to specified peripheral functions Event signals can be used as activation sources for operating any one of three types of peripheral functions 14 2 Configuration of ELC Figure 14 1 shows the event link controller block diagram Figure 14 1 ELC Block Diagram Internal bus Event c...

Page 590: ...nt link output destination to the same function Set an ELSELRn register during a period when no event output peripheral functions are generating event signals Table 14 2 lists the correspondence between ELSELRn n 00 to 09 registers and peripheral functions and Table 14 3 lists the correspondence between values set to ELSELRn n 00 to 09 registers and operation of link destination peripheral functio...

Page 591: ...terrupt edge detection 4 INTP4 ELSELR05 External interrupt edge detection 5 INTP5 ELSELR06 TAU channel 00 Count end Capture end INTTM00 ELSELR07 TAU channel 01 Count end Capture end INTTM01 ELSELR08 TAU channel 02 Count end Capture end INTTM02 ELSELR09 TAU channel 03 Count end Capture end INTTM03 Table 14 3 Correspondence Between Values Set to ELSELRn n 00 to 09 Registers and Operation of Link Des...

Page 592: ...nce Between Values Set to ELSELRn n 00 to 09 Registers and Operation of Link Destination Peripheral Functions at Reception Figure 14 3 Relationship Between Interrupt Handling and ELC Peripheral function Event output side Peripheral function Event receive side ELC Interrupt request Event signal Interrupt enable controlNote Interrupt controller CPU Status flagNote Note Not available depending on the...

Page 593: ...are simultaneously generated then they are processed according to the default priority of vectored interrupt servicing Default priority see Table 15 1 A standby release signal is generated and STOP HALT and SNOOZE modes are released External interrupt requests and internal interrupt requests are provided as maskable interrupts External 6 Internal 12 2 Software interrupt This is a vectored interrup...

Page 594: ...4 INTSR0 UART0 reception transfer end 00020H 15 INTSRE0 UART0 reception communication error occurrence 00022H INTTM01H End of timer channel 01 count or capture at higher 8 bit timer operation 16 INTTM03H End of timer channel 03 count or capture at higher 8 bit timer operation 00028H 17 INTIICA1 End of IICA1 communication 0002AH 18 INTTM00 End of timer channel 00 count or capture 0002CH 19 INTTM01 ...

Page 595: ...mer TRAP Execution of illegal instructionNote 4 IAW Illegal memory access RPE RAM parity error Notes 1 The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously Zero indicates the highest priority and 21 indicates the lowest priority 2 Basic configuration types A to C correspond to A to C in Figure 15 1 3 When bit 7 LVIMD of the voltage dete...

Page 596: ...le interrupt INTPn IF MK IE PR1 ISP1 PR0 ISP0 Internal bus External interrupt edge enable register EGP EGN INTPn pin input Edge detector Priority controller Vector table address generator Standby release signal C Software interrupt Vector table address generator Internal bus Interrupt request IF Interrupt request flag IE Interrupt enable flag ISP0 In service priority flag 0 ISP1 In service priorit...

Page 597: ...PR10 INTFL FLIF FLMK FLPR0 FLPR1 INTDMA0 DMAIF0 DMAMK0 DMAPR00 DMAPR10 INTDMA1 DMAIF1 DMAMK1 DMAPR01 DMAPR11 INTST0Note 1 STIF0Note 1 STMK0Note 1 STPR00 STPR10Note 1 INTCSI00Note 1 CSIIF00Note 1 CSIMK00Note 1 CSIPR000 CSIPR100Note 1 INTSR0 SRIF0 SRMK0 SRPR00 SRPR10 INTSRE0Note 2 SREIF0Note 2 SREMK0Note 2 SREPR00 SREPR10Note 2 INTTM01HNote 2 TMIF01HNote 2 TMMK01HNote 2 TMPR001H TMPR101HNote 2 INTTM...

Page 598: ... PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF Address FFFE1H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF0H SREIF0 TMIF01H SRIF0 STIF0 CSIIF00 DMAIF1 DMAIF0 FLIF IICAIF0 ADIF Address FFFE2H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IF1L TMIF03 TMIF02 TMIF01 TMIF00 IICAIF1 TMIF03H 0 0 XXIFX Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated interrupt request st...

Page 599: ...Remark If an instruction that writes data to this register is executed the number of instruction execution clocks increases by 2 clocks Figure 15 3 Format of Interrupt Mask Flag Registers MK0L MK0H MK1L Address FFFE4H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0L PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK Address FFFE5H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 MK0H SREMK0 TMMK01H SRMK0 STMK0 C...

Page 600: ...15 4 Format of Priority Specification Flag Registers PR00L PR00H PR01L PR10L PR10H PR11L Address FFFE8H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR00L PPR05 PPR04 PPR03 PPR02 PPR01 PPR00 LVIPR0 WDTIPR0 Address FFFECH After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR10L PPR15 PPR14 PPR13 PPR12 PPR11 PPR10 LVIPR1 WDTIPR1 Address FFFE9H After reset FFH R W Symbol 7 6 5 4 3 2 1 0 PR00H SREPR00 TMPR001H ...

Page 601: ... 3 2 1 0 EGN0 0 0 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn INTPn pin valid edge selection n 0 to 5 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges Table 15 3 shows the ports corresponding to the EGPn and EGNn bits Table 15 3 Ports Corresponding to EGPn and EGNn bits Detection Enable Bit Interrupt Request Signal EGP0 EGN0 INTP0 EGP1 EGN1 INTP1 EGP2 EGN2...

Page 602: ...st if the value of the priority specification flag register of the acknowledged interrupt is not 00 its value minus 1 is transferred to the ISP0 and ISP1 flags The PSW contents are also saved into the stack with the PUSH PSW instruction They are restored from the stack with the RETI RETB and POP PSW instructions Reset signal generation sets PSW to 06H Figure 15 6 Configuration of Program Status Wo...

Page 603: ...TimeNote Servicing time 9 clocks 16 clocks Note Maximum time does not apply when an instruction from the internal RAM area is executed Remark 1 clock 1 fCLK fCLK CPU clock If two or more maskable interrupt requests are generated simultaneously the request with a higher priority level specified in the priority specification flag is acknowledged first If two or more interrupts requests have the same...

Page 604: ...nterrupt request held pending Interrupt request held pending Higher priority than other interrupt requests simultaneously generated Higher default priorityNote than other interrupt requests simultaneously generated IF Interrupt request flag MK Interrupt mask flag PR0 Priority specification flag 0 PR1 Priority specification flag 1 IE Flag that controls acknowledgment of maskable interrupt request 1...

Page 605: ...mp to interrupt servicing Interrupt servicing program Instruction Instruction Remark 1 clock 1 fCLK fCLK CPU clock Figure 15 9 Interrupt Request Acknowledgment Timing Maximum Time 16 clocks Instruction Instruction immediately CPU processing before interrupt CPU processing xxIF 6 clocks 8 clocks PSW and PC saved jump to interrupt servicing Interrupt servicing program Instruction Remark 1 clock 1 fC...

Page 606: ...necessary to set 1 the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment Moreover even if interrupts are enabled multiple interrupt servicing may not be enabled this being subject to interrupt priority control Two types of priority control are available default priority control and programmable priority control Programmable priority control is used for m...

Page 607: ... interrupt servicing enabled 2 Multiple interrupt servicing disabled 3 ISP0 ISP1 and IE are flags contained in the PSW ISP1 0 ISP0 0 An interrupt of level 1 or level 0 is being serviced ISP1 0 ISP0 1 An interrupt of level 2 is being serviced ISP1 1 ISP0 0 An interrupt of level 3 is being serviced ISP1 1 ISP0 1 Wait for An interrupt acknowledgment all interrupts enabled IE 0 Interrupt request ackno...

Page 608: ...xample 2 Multiple interrupt servicing does not occur due to priority control Main processing INTxx servicing INTyy servicing INTxx PR 10 INTyy PR 11 EI RETI IE 0 IE 0 EI 1 instruction execution RETI IE 1 IE 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx and multiple interrupt servicing does not take place Th...

Page 609: ...uring servicing of interrupt INTxx EI instruction is not issued therefore interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place The INTyy interrupt request is held pending and is acknowledged following execution of one main processing instruction PR 00 Specify level 0 with PR1 0 PR0 0 higher priority level PR 01 Specify level 1 with PR1 0 PR0 1 PR 10 Spec...

Page 610: ...PSW A MOV1 PSW bit CY SET1 PSW bit CLR1 PSW bit RETB RETI POP PSW BTCLR PSW bit addr20 EI DI SKC SKNC SKZ SKNZ SKH SKNH Write instructions for the IF0L IF0H IF1L IF2L MK0L MK0H MK1L MK2L PR00L PR00H PR01L PR02L PR10L PR10H PR11L and PR12L registers Figure 15 11 shows the timing at which interrupt requests are held pending Figure 15 11 Interrupt Request Hold Instruction N Instruction M PSW and PC s...

Page 611: ...t request generation 3 SNOOZE mode In the case of CSIp or A D conversion request by UARTq data reception the STOP mode is exited the CSIp or UARTq data is received without operating the CPU and A D conversion is performed This can only be specified when the high speed on chip oscillator is selected for the CPU peripheral hardware clock fCLK In either of these two modes all the contents of register...

Page 612: ... controlled by the following two registers Oscillation stabilization time counter status register OSTC Oscillation stabilization time select register OSTS Remark For the registers that start stop or select the clock see CHAPTER 5 CLOCK GENERATOR For registers which control the SNOOZE mode CHAPTER 9 A D CONVERTER and CHAPTER 11 SERIAL ARRAY UNIT ...

Page 613: ...ization time status fX 10 MHz fX 20 MHz 0 0 0 0 0 0 0 0 28 fX max 25 6 s max 12 8 s max 1 0 0 0 0 0 0 0 28 fX min 25 6 s min 12 8 s min 1 1 0 0 0 0 0 0 29 fX min 51 2 s min 25 6 s min 1 1 1 0 0 0 0 0 210 fX min 102 s min 51 2 s min 1 1 1 1 0 0 0 0 211 fX min 204 s min 102 s min 1 1 1 1 1 0 0 0 213 fX min 819 s min 409 s min 1 1 1 1 1 1 0 0 215 fX min 3 27 ms min 1 63 ms min 1 1 1 1 1 1 1 0 217 fX ...

Page 614: ...5 6 s 12 8 s 0 0 1 29 fX 51 2 s 25 6 s 0 1 0 210 fX 102 s 51 2 s 0 1 1 211 fX 204 s 102 s 1 0 0 213 fX 819 s 409 s 1 0 1 215 fX 3 27 ms 1 63 ms 1 1 0 217 fX 13 1 ms 6 55 ms 1 1 1 218 fX 26 2 ms 13 1 ms Cautions 1 To set the STOP mode when the X1 clock is used as the CPU clock set the OSTS register before executing the STOP instruction 2 Before changing the setting of the OSTS register confirm that...

Page 615: ...fore the setting was the high speed system clock or high speed on chip oscillator clock The operating statuses in the HALT mode are shown below Caution Because the interrupt request signal is used to clear the HALT mode if the interrupt mask flag is 0 the interrupt processing is enabled and the interrupt request flag is 1 the interrupt request signal is generated the HALT mode is not entered even ...

Page 616: ...memory RAM Port latch Status before HALT mode was set is retained Timer array unit Operable Watchdog timer See CHAPTER 8 WATCHDOG TIMER Clock output buzzer output Operable A D converter D A converter Serial array unit SAU Serial interface IICA DMA controller Event link controller ELC Operable function blocks can be linked Power on reset function Operable Voltage detection function External interru...

Page 617: ... 3 HALT Mode Release by Interrupt Request Generation HALT instruction Operating mode HALT mode Operating mode Oscillation High speed system clock or High speed on chip oscillator clock Status of CPU Standby release signal Note 1 Interrupt request Wait Note 2 Notes1 For details of the standby release signal see Figure 15 1 2 Wait time for HALT mode release When vectored interrupt servicing is carri...

Page 618: ...eed system clock Oscillation stabilization time check by using OSTC register Normal operation high speed on chip oscillator clock Oscillation stopped Note Starting X1 oscillation is specified by software 2 When high speed on chip oscillator clock is used as CPU clock HALT instruction Reset signal High speed on chip oscillator clock Normal operation high speed on chip oscillator clock HALT mode Res...

Page 619: ...the interrupt request flag is 1 the interrupt request signal is generated the STOP mode is immediately cleared if set when the STOP instruction is executed in such a situation Accordingly once the STOP instruction is executed the system returns to its normal operating mode after the elapse of release time from the STOP mode 2 When using CSIp UARTq or the A D converter in the SNOOZE mode set up ser...

Page 620: ...led only for CSIp and UARTq switching to the SNOOZE mode Operation is disabled for anything other than CSIp and UARTq Serial interface IICA Wakeup by address match operable DMA controller Operation disabled Event link controller ELC Operable function blocks can be linked Power on reset function Operable Voltage detection function External interrupt CRC operation function High speed CRC Operation s...

Page 621: ...t is enabled vectored interrupt servicing is carried out If interrupt acknowledgment is disabled the next address instruction is executed Figure 16 5 STOP Mode Release by Interrupt Request Generation 1 2 1 When high speed system clock X1 oscillation is used as CPU clock Normal operation high speed system clock Normal operation high speed system clock Oscillates Oscillates STOP instruction STOP mod...

Page 622: ...release timeNote 2 3 When high speed on chip oscillator clock is used as CPU clock Standby release signal Note 1 Status of CPU High speed on chip oscillator clock Normal operation high speed on chip oscillator clock Oscillates STOP mode Oscillation stopped Wait for oscillation accuracy stabilization Interrupt request STOP instruction Normal operation high speed on chip oscillator clock Oscillates ...

Page 623: ...ates Oscillation stopped Oscillates Status of CPU Oscillation stabilization time Check by using OSTC register Oscillation stopped Oscillation stopped Note Starting X1 oscillation is specified by software 2 When high speed on chip oscillator clock is used as CPU clock STOP instruction Reset signal High speed on chip oscillator clock Normal operation high speed on chip oscillator clock STOP mode Res...

Page 624: ...nverter mode register 2 ADM2 to 1 immediately before switching to the STOP mode For details see 9 3 Registers Controlling A D Converter Remark p 00 q 0 m 0 In SNOOZE mode transition wait status to be only following time Transition time from STOP mode to SNOOZE mode 18 s to 65 s Remark Transition time from STOP mode to SNOOZE mode varies depending on the temperature conditions and the STOP mode per...

Page 625: ... output buzzer output Operation stopped A D converter Operable D A converter Operable status before SNOOZE mode was set is retained Serial array unit SAU Operable only CSIp and UARTq Operation disabled other than CSIp and UARTq Serial interface IICA Operation disabled DMA controller Event link controller ELC Operable function blocks can be linked Power on reset function Operable Voltage detection ...

Page 626: ...de AWC 1 or SWC 1 immediately before switching to the STOP mode 5 Be sure to release the SNOOZE mode AWC 0 or SWC 0 immediately after return to the normal operation 3 Timing diagram when the interrupt request signal is not generated in the SNOOZE mode Figure 16 8 When the Interrupt Request Signal is not Generated in the SNOOZE Mode Oscillates Wait for oscillation accuracy stabilization Oscillates ...

Page 627: ...eleased and program execution starts using the high speed onchip oscillator clock see Figures 17 2 and 17 3 after reset processing Reset by POR and LVD circuit supply voltage detection is automatically released when VDD VPOR or VDD VLVD after the reset and program execution starts using the high speed on chip oscillator clock see CHAPTER 18 POWER ON RESET CIRCUIT and CHAPTER 19 VOLTAGE DETECTOR af...

Page 628: ...gister Reset signal Voltage detector reset signal Power on reset circuit reset signal RESF register read signal Reset signal by execution of illegal instruction Reset signal by RAM parity error Reset signal by illegal memory access Watchdog timer reset signal RPERF IAWRF WDTRF RESET TRAP LVIRF Caution An LVD circuit internal reset does not reset the LVD circuit Remarks 1 LVIM Voltage detection reg...

Page 629: ... software Release from the reset state is automatic in the case of a reset due to a watchdog timer overflow execution of an illegal instruction detection of a RAM parity error or detection of illegal memory access After reset processing execution of the program with the high speed on chip oscillator clock as the operating clock starts Figure 17 3 Timing of Reset Due to Execution of Illegal Instruc...

Page 630: ...wer is supplied a voltage stabilization waiting time of about 0 99 ms typ and up to 2 30 ms max is required before reset processing starts after release of the external reset 2 The state of P40 is as follows High impedance during the external reset period or reset period by the POR High level during other types of reset or after receiving a reset signal connected to the on chip pull up resistance ...

Page 631: ...R reset The port pins except for P40 become high impedance Timer array unit Operation stopped Watchdog timer Clock output buzzer output A D converter D A converter Serial array unit SAU Serial interface IICA DMA controller Event link controller ELC PWM option unit Power on reset function Detection operation possible Voltage detection function Operation is possible in the case of an LVD reset and s...

Page 632: ...gisters 0 1 NFEN0 NFEN1 00H Peripheral enable register 0 PER0 00H Peripheral enable register 1 PER1 00H High speed on chip oscillator frequency select register HOCODIV Undefined High speed on chip oscillator trimming register HIOTRM UndefinedNote 2 Timer array unit Timer data registers 00 to 03 TDR00 to TDR03 0000H Timer mode registers 00 to 03 TMR00 to TMR03 0000H Timer status registers 00 to 03 ...

Page 633: ... 01 SIR00 SIR01 0000H Serial mode registers 00 01 SMR00 SMR01 0020H Serial communication operation setting registers 00 01 SCR00 SCR01 0087H Serial channel enable status register 0 SE0 0000H Serial channel start register 0 SS0 0000H Serial channel stop register 0 ST0 0000H Serial clock select register 0 SPS0 0000H Serial output register 0 SO0 0303H Serial output enable register 0 SOE0 0000H Serial...

Page 634: ... memory CRC control register CRC0CTL 00H Flash memory CRC operation result register PGCRCL 0000H CRC input register CCRIN 00H CRC data register CRCD 0000H Invalid memory access detection control register IAWCTL 00H RAM parity error control register RPECTL 00H Flash memory Data flash control register DFLCTL 00H BCD correction circuit BCD correction result register BCDAJ Undefined Notes 1 During res...

Page 635: ...red 1 Internal reset request is generated RPERF Internal reset request by RAM parity 0 Internal reset request is not generated or the RESF register is cleared 1 Internal reset request is generated IAWRF Internal reset request by illegal memory access 0 Internal reset request is not generated or the RESF register is cleared 1 Internal reset request is generated LVIRF Internal reset request by volta...

Page 636: ... When Reset Request Is Generated Reset Source Flag RESET Input Reset by POR Reset by Execution of Illegal Instruction Reset by WDT Reset by RAM Parity Error Reset by Illegal memory Access Reset by LVD TRAP bit Cleared 0 Cleared 0 Set 1 Held Held Held Held WDTRF bit Held Set 1 RPERF bit Held Set 1 IAWRF bit Held Set 1 LVIRF bit Held Set 1 Figure 17 5 shows the procedure for checking reset source ...

Page 637: ... RESF register 1 Yes Read RESF register Power on reset external reset generated Internal reset request by the voltage detector generated Internal reset request by the illegal memory access generated Internal reset request by the RAM parity error generated Internal reset request by the watchdog timer generated Internal reset request by the execution of the illegal instruction generated Read the RES...

Page 638: ...g operation confirm that the supply voltage has returned to the operating voltage range Caution If an internal reset signal is generated in the POR circuit TRAP WDTRF RPERF IAWRF and LVIRF flags of the reset control flag register RESF is cleared Remarks 1 This product incorporates multiple hardware functions that generate an internal reset signal A flag that indicates the reset source is located i...

Page 639: ...block diagram of the power on reset circuit is shown in Figure 18 1 Figure 18 1 Block Diagram of Power on reset Circuit Reference voltage source Internal reset signal VDD VDD 18 3 Operation of Power on reset Circuit The timing of generation of the internal reset signal by the power on reset circuit and voltage detector is shown below ...

Page 640: ...e counter status register OSTC to confirm the lapse of the oscillation stabilization time 3 The time until normal operation starts includes the following reset processing time when the external reset is released release from the first external reset following release from the POR state after the RESET ____________ signal is driven high 1 as well as the voltage stabilization wait time after VPOR 1 ...

Page 641: ...abilizationNote 2 Notes 1 The high speed on chip oscillator clock and a high speed system clock can be selected as the CPU clock To use the X1 clock use the oscillation stabilization time counter status register OSTC to confirm the lapse of the oscillation stabilization time 2 The internal reset processing time includes the oscillation accuracy stabilization time of the high speed on chip oscillat...

Page 642: ...n high speed on chip oscillator clock Note 1 Notes 1 The high speed on chip oscillator clock and a high speed system clock can be selected as the CPU clock To use the X1 clock use the oscillation stabilization time counter status register OSTC to confirm the lapse of the oscillation stabilization time 2 The internal reset processing time includes the oscillation accuracy stabilization time of the ...

Page 643: ... that uses a timer and then initialize the ports Figure 18 3 Example of Software Processing After Reset Release 1 2 If supply voltage fluctuation is 50 ms or less in vicinity of POR detection voltage Check the reset source etc Note 2 Note 1 Reset Initialization processing 1 50 ms has passed TMIFmn 1 Initialization processing 2 Setting timer array unit to measure 50 ms Initial setting for port Sett...

Page 644: ...oltage detector No WDTRF of RESF register 1 Yes No Reset processing by illegal instruction execution Note TRAP of RESF register 1 Yes Reset processing by RAM parity error Yes LVIRF of RESF register 1 RPERF of RESF register 1 No Reset processing by illegal memory access Yes IAWRF of RESF register 1 Note The illegal instruction is generated when instruction code FFH is executed Reset by the illegal ...

Page 645: ...erating interrupts and ending resets and the low voltage detection level VLVDL is used for triggering resets b Reset mode option byte LVIMDS1 LVIMDS0 1 1 The detection voltage VLVD selected by the option byte 000C1H is used for triggering and ending resets c Interrupt mode option byte LVIMDS1 LVIMDS0 0 1 The detection voltage VLVD selected by the option byte 000C1H is used for generating interrupt...

Page 646: ...IF LVISEN Voltage detection level selector VLVDH VLVDL VLVD Reference voltage source Selector Option byte 000C1H VPOC2 to VPOC0 Option byte 000C1H LVIS1 LVIS0 VDD Voltage detection level register LVIS Voltage detection register LVIM INTLVI Internal reset signal Controller Internal bus 19 3 Registers Controlling Voltage Detector The voltage detector is controlled by the following registers Voltage ...

Page 647: ...LVD output is valid LVIOMSK Mask status flag of LVD output 0 Mask of LVD output is invalid 1 Mask of LVD output is valid Notes 3 4 LVIF Voltage detection flag 0 Supply voltage VDD detection voltage VLVD or when LVD operation is disabled 1 Supply voltage VDD detection voltage VLVD Notes 1 The reset value changes depending on the reset source If the LVIS register is reset by LVD it is not reset but ...

Page 648: ...e reset value changes depending on the reset source and the setting of the option byte This register is not cleared 00H by LVD reset The generation of reset signal other than an LVD reset sets as follows When option byte LVIMDS1 LVIMDS0 1 0 00H When option byte LVIMDS1 LVIMDS0 1 1 81H When option byte LVIMDS1 LVIMDS0 0 1 01H 2 Writing 0 can only be allowed when LVIMDS1 and LVIMDS0 are set to 1 and...

Page 649: ...ting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Rising edge Falling edge LVIMDS1 LVIMDS0 2 81 V 2 75 V 1 1 0 1 1 1 1 2 92 V 2 86 V 1 1 1 0 3 02 V 2 96 V 1 1 0 1 3 13 V 3 06 V 0 1 0 0 Other than above Setting prohibited LVD setting interrupt mode Detection voltage Option byte setting value VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Rising edge Falling edge LVIMDS1 LVIMDS0 2 81 V 2 75 V 0 1 0 1 1 1 1 2 92 V...

Page 650: ... to 1 the initial value of the LVIS register is set to 81H Bit 7 LVIMD is 1 reset mode Bit 0 LVILV is 1 low voltage detection level VLVDL or VLVD Operation in LVD reset mode In the reset mode option byte LVIMDS1 LVIMDS0 1 1 the state of an internal reset by LVD is retained until the supply voltage VDD exceeds the voltage detection level VLVD after power is supplied The internal reset is released w...

Page 651: ...DS0 1 1 H H Time LVIF flag LVIMD flag LVIRF flag RESF register LVILV flag Internal reset signal POR reset signal LVD reset signal Supply voltage VDD VLVD VPOR 1 51 V TYP VPDR 1 50 V TYP Lower limit of operation voltage Not cleared Not cleared Cleared Cleared by software Cleared Remark VPOR POR power supply rise detection voltage VPDR POR power supply fall detection voltage ...

Page 652: ...n internal reset by LVD is retained until the supply voltage VDD exceeds the voltage detection level VLVD after power is supplied after the first release of the POR The internal reset is released when the supply voltage VDD exceeds the voltage detection level VLVD An interrupt request signal by LVD INTLVI is generated when the supply voltage VDD falls below the voltage detection level VLVD or when...

Page 653: ...ag Note 2 Note 2 Cleared Cleared by software H Note 1 Lower limit of operation voltage Notes 1 The LVIMK flag is set to 1 by reset signal generation 2 When the voltage falls this LSI should be placed in the STOP mode or placed in the reset state by controlling the externally input reset signal before the voltage falls below the operating voltage range defined in 27 4 AC Characteristics When restar...

Page 654: ...e VDD exceeds the high voltage detection level VLVDH after power is supplied The internal reset is released when the supply voltage VDD exceeds the high voltage detection level VLVDH An interrupt request signal by LVD INTLVI is generated and arbitrary save processing is performed when the supply voltage VDD falls below the high voltage detection level VLVDH After that an internal reset by LVD is g...

Page 655: ...50 V TYP VLVDH LVIMK flag set by software LVISEN flag set by software H Note 1 Cleared by software RESET Normal operation RESET Normal operation RESET Save processing Cleared by software Note 3 Cleared Wait for stabilization by software 400 μs or 5 clocks of fIL Note 3 Cleared by software Save processing Normal operation Cleared by software Note 2 Lower limit of operation voltage Cleared If a rese...

Page 656: ... perform the processing according to Figure 19 7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode 3 After a reset is released perform the processing according to Figure 19 8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode Remark VPOR POR power supply rise detection voltage VPDR POR power supply fall detection voltage ...

Page 657: ...VLVDL VPOR 1 51 V TYP VPDR 1 50 V TYP VLVDH LVIMK flag set by software LVISEN flag set by software Save processing RESET Normal operation RESET Normal operation RESET Cleared by software Cleared by software H Note 1 Time Save processing Cleared When a condition of VDD is VDD VLVDH after releasing the mask a reset is generated because of LVIMD 1 reset mode Cleared by software Note 2 Cleared by soft...

Page 658: ...ure 19 7 Processing Procedure After an Interrupt Is Generated Perform required save processing INTLVI generated LVISEN 1 Set the LVISEN bit to 1 to mask voltage detection LVIOMSK 1 LVISEN 0 Set the LVISEN bit to 0 to enable voltage detection Save processing Yes No LVD reset generated The MCU returns to normal operation when internal reset by voltage detector LVD is not generated since a condition ...

Page 659: ...reset or interrupt generation by LVD Figure 19 8 shows the procedure for initial setting of interrupt and reset mode Figure 19 8 Initial Setting of Interrupt and Reset Mode Remark fIL Low speed on chip oscillator clock frequency Set the LVIMD bit to 0 to set interrupt mode Refer to Figure 17 5 Procedure for Checking Reset Source Power supply started LVISEN 1 Voltage detection stabilization wait ti...

Page 660: ...ch system by means of a software counter that uses a timer and then initialize the ports Figure 19 9 Example of Software Processing If Supply Voltage Fluctuation is 50 s or Less in Vicinity of LVD Detection Voltage Reset Yes No Clearing WDT Refer to Figure 17 5 Procedure for Checking Reset Source Note Timer starts TSmn 1 Source fMCK 4 04 MHz MAX 28 where comparison value 789 50 ms e g fCLK High sp...

Page 661: ...rupt mode is set enter STOP mode or enable the reset status using the external reset pin before the voltage falls below the operating voltage range shown in 27 4 AC Characteristics When restarting operation confirm that the supply voltage has returned to the operating voltage range 4 When the LVD is off it is necessary to perform an external reset For an external reset input a low level for 10 s o...

Page 662: ...g various data in addition to the code flash memory area while the CPU is running 2 RAM parity error detection function This detects parity errors when reading RAM data 3 RAM guard function This prevents RAM data from being rewritten when the CPU freezes 4 SFR guard function This prevents SFRs from being rewritten when the CPU freezes 5 Invalid memory access detection function This detects illegal...

Page 663: ...n high speed CRC 20 3 Operation of Flash memory CRC operation function high speed CRC The IEC60730 standard mandates the checking of data in the flash memory and recommends using CRC to do it The high speed CRC provided in the RL78 G1P can be used to check the entire code flash memory area during the initialization routine The high speed CRC can be executed only when the program is allocated on th...

Page 664: ...d Remark Input the expected CRC operation result value to be used for comparison in the lowest 4 bytes of the flash memory Note that the operation range will thereby be reduced by 4 bytes 20 3 2 Flash memory CRC operation result register PGCRCL This register is used to store the high speed CRC operation results The PGCRCL register can be set by a 16 bit memory manipulation instruction Reset signal...

Page 665: ...AM Execute the HALT instruction CRC operation complete Execute the RET instruction Yes No CRC operation starts by HALT instruction execution When the CRC operation is complete the HALT mode is released and control is returned from RAM Prohibits CRC operation Read CRC operation result Compare the value with the stored expected value Correctly complete Abnormal complete CRC0EN 0 Read the value of PG...

Page 666: ... of 08F6H to be obtained from the CRCD register This is the result obtained by executing a CRC operation on the bit rows shown below which consist of the data 12345678H inverted in bit order CRCIN setting data 78H 56H 34H 12H Bit representation data 0111 1000 0101 0110 0011 0100 0001 0010 Bit reverse data 0001 1110 0110 1010 0010 1100 0100 1000 Result data 0110 1111 0001 0000 CRCD data 0000 1000 1...

Page 667: ...2 11 10 9 8 7 6 5 4 3 2 1 0 CRCD Cautions 1 Read the value written to CRCD register before writing to CRCIN register 2 If conflict between writing and storing operation result to CRCD register occurs the writing is ignored 20 4 3 Operation flow Figure 20 6 shows the CRC operation function general purpose CRC Figure 20 6 CRC Operation Function General Purpose CRC START Write CRCD register to 0000H ...

Page 668: ...arity error has occurred 1 A parity error has occurred Caution The parity bit is appended when data is written and the parity is checked when the data is read Therefore while RAM parity error resets are enabled RPERDIS 0 be sure to initialize RAM areas where data access is to proceed before reading data The RL78 s CPU executes look ahead due to the pipeline operation the CPU might read an uninitia...

Page 669: ...d Check start RPERF 1 Note No RAM check Parity error has occurred Generation of internal reset Normal operation RPERDIS 1 RAM check RPEF 1 RPERDIS 0 Yes No RAM failure processing Enable parity error resets Disable parity error resets Read RAM Yes No Yes Note See CHAPTER 17 RESET FUNCTION for details on how to confirm internal resets due to RAM parity errors ...

Page 670: ...ction control register IAWCTL This register is used to control the detection of invalid memory access and RAM SFR guard function GRAM1 and GRAM0 bits are used in RAM guard function The IAWCTL register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 00H Figure 20 9 Format of Invalid Memory Access Detection Control Register IAWCTL Address F0078H...

Page 671: ...on Control Register IAWCTL Address F0078H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC GPORT Control registers of port function guard 0 Disabled Control registers of port function can be read or written to 1 Enabled Writing to control registers of port function is disabled Reading is enabled Guarded SFR PMxx PUxx PMC1Note 1 ADPCNote 2 GINT Registers of in...

Page 672: ...egisters SFR 256 bytes RAMNote General purpose registers 32 bytes Code flash memoryNote Special function registers 2nd SFR 2 Kbytes Reserved Reserved Reserved Read Write Fetching instructions execute Possibility access OK OK OK OK OK OK OK OK NG NG NG NG NG NG NG Reserved 00000H xxxxxH FFFFFH FFEFFH FFF00H FFEDFH FFEE0H yyyyyH F1000H F0FFFH F1800H F17FFH F0800H F07FFH F0000H F4000H EFFFFH F3FFFH E...

Page 673: ...ration clears this register to 00H Figure 20 12 Format of Invalid Memory Access Detection Control Register IAWCTL Address F0078H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC IAWENNote Control of invalid memory access detection 0 Disable the detection of invalid memory access 1 Enable the detection of invalid memory access Note Only writing 1 to the IAWEN ...

Page 674: ...tection Function Watchdog timer WDT Channel 1 of timer array unit 0 TAU0 X1 X2 TI01 fIL fCLK 1 High speed on chip oscillator fIH X1 oscillator fMX Low speed on chip oscillator 15 kHz TYP Selector Selector 2 Operational overview Whether the clock frequency is correct or not can be judged by measuring the pulse interval under the following conditions The internal high speed oscillation clock fIH or ...

Page 675: ...and the timer operation clock is correct The TIS0 register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 00H Figure 20 14 Format of Timer Input Select Register 0 TIS0 Address F0074H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 TIS0 0 0 0 0 0 TIS02 TIS01 TIS00 TIS02 TIS01 TIS00 Selection of timer input used with channel 1 0 0 0 Input signal of ...

Page 676: ...A D converter conversion result 2 1 5 Select the ANIx pin as the target for A D conversion by setting the ADTES register ADTES1 ADTES0 0 0 6 Perform A D conversion for the ANIx pin conversion result 1 2 7 Select the positive reference voltage of the A D converter as the target for A D conversion by setting the ADTES register ADTES1 ADTES0 1 1 8 Perform A D conversion of the positive reference volt...

Page 677: ... D Test Function TemperaturesensorNote Internal reference voltage 1 45 V Note ANI0 AVREFP ANI1 AVREFM ANIxx ANIxx VDD VSS A D convertor side referencevoltage A D convertor side referencevoltage A D convertor ADREFP1 ADREFP0 ADREFM ADTES1 ADTES0 ADISS ADS4 to ADS0 Note Selectable only in HS high speed main mode ...

Page 678: ... internal 0 V Select AVREFP as the target of A D conversion when converting AVREF The ADTES register can be set by an 8 bit memory manipulation instruction Reset signal generation clears this register to 00H Figure 20 16 Format of A D Test Register ADTES Address F0013H After reset 00H R W Symbol 7 6 5 4 3 2 1 0 ADTES 0 0 0 0 0 0 ADTES1 ADTES0 ADTES1 ADTES0 A D conversion target 0 0 ANIxx temperatu...

Page 679: ...0 1 0 ANI2 P22 ANI2 pin 0 0 0 1 1 ANI3 P23 ANI3 pin 0 0 1 0 0 ANI4Note 2 P24 ANI4 pin 0 0 1 0 1 ANI5Note 2 P25 ANI5 pin 0 0 1 1 0 ANI6Note 2 P26 ANI6 pin 0 0 1 1 1 ANI7 P27 ANI7 pin 0 1 0 0 0 ANI16Note 1 P10 ANI16 pin 1 0 0 0 0 Temperature sensor outputNote 3 1 0 0 0 1 Internal reference voltage output 1 45 V Note 3 Other than above Setting prohibited Notes 1 24 pin products only 2 32 pin products...

Page 680: ...d characteristics since it is used to stabilize internal voltage REGC VSS Caution Keep the wiring length as short as possible for the broken line part in the above figure The regulator output voltage see Table 21 1 Table 21 1 Regulator Output Voltage Conditions Mode Output Voltage Condition LS low speed main mode 1 8 V HS high speed main mode 1 8 V In STOP mode 2 1 V Other than above include durin...

Page 681: ...stopped or enabled in the HALT or STOP mode Setting of interval time of watchdog timer Setting of window open period of watchdog timer Setting of interval interrupt of watchdog timer Used or not used 2 000C1H Setting of LVD operation mode Interrupt reset mode Reset mode Interrupt mode LVD off external reset input from the RESET ___________ pin is used Setting of LVD detection level VLVDH VLVDL VLV...

Page 682: ...er operation enabled counting started after reset WDCS2 WDCS1 WDCS0 Watchdog timer overflow time fIL 17 25 kHz MAX 0 0 0 26 fIL 3 71 ms 0 0 1 27 fIL 7 42 ms 0 1 0 28 fIL 14 84 ms 0 1 1 29 fIL 29 68 ms 1 0 0 211 fIL 118 72 ms Other than above Setting prohibited WDSTBYON Operation control of watchdog timer counter HALT STOP mode 0 Counter operation stopped in HALT STOP modeNote 1 Counter operation e...

Page 683: ...VIMDS0 2 81 V 2 75 V 1 1 0 1 1 1 1 2 92 V 2 86 V 1 1 1 0 3 02 V 2 96 V 1 1 0 1 3 13 V 3 06 V 0 1 0 0 Other than above Setting prohibited LVD setting interrupt mode Detection voltage Option byte setting value VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Rising edge Falling edge LVIMDS1 LVIMDS0 2 81 V 2 75 V 0 1 0 1 1 1 1 2 92 V 2 86 V 1 1 1 0 3 02 V 2 96 V 1 1 0 1 3 13 V 3 06 V 0 1 0 0 Other tha...

Page 684: ...rating voltage range 1 0 LS low speed main mode 1 to 8 MHz 2 7 to 3 6 V 1 1 HS high speed main mode 1 to 32 MHz 2 7 to 3 6 V Other than above Setting prohibited FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 Frequency of the high speed on chip oscillator 1 0 0 0 32 MHz 0 0 0 0 24 MHz 1 0 0 1 16 MHz 0 0 0 1 12 MHz 1 0 1 0 8 MHz 0 0 1 0 6 MHz 1 0 1 1 4 MHz 0 0 1 1 3 MHz 1 1 0 0 2 MHz 1 1 0 1 1 MHz Other than above...

Page 685: ... Enables on chip debugging Erases data of flash memory in case of failures in authenticating on chip debug security ID 1 1 Enables on chip debugging Does not erases data of flash memory in case of failures in authenticating on chip debug security ID Caution Values can only be specified for bits 7 and 0 OCDENSET and OCDERSD When writing be sure to write 000010B to bits 6 to 1 Remark The value on bi...

Page 686: ...chdog timer Enables watchdog timer operation Window open period of watchdog timer is 50 Overflow time of watchdog timer is 29 fIL Stops watchdog timer operation during HALT STOP mode DB 7AH Select 2 75 V for VLVDL Select rising edge 1 77 V falling edge 2 86 V for VLVDH Select the interrupt reset mode as the LVD operation mode DB ADH Select the LS low speed main mode as the flash operation mode and...

Page 687: ...eneral purpose registers 32 bytes Code flash memory 16 KB Special function registers 2nd SFR 2 KB Reserved Reserved Mirror area Data flash memory 2 KB Reserved Reserved The following three methods for programming the flash memory are available Writing to flash memory by using flash memory programmer see 23 1 Data can be written to the flash memory on board or off board by using a dedicated flash m...

Page 688: ... Data can be written to the flash memory on board or off board by using a dedicated flash memory programmer 1 On board programming The contents of the flash memory can be rewritten after the RL78 G1P has been mounted on the target system The connectors that connect the dedicated flash memory programmer must be mounted on the target system 2 Off board programming Data can be written to the flash me...

Page 689: ...ite E20 On chip Debugging Emulator TOOL0 I O Transmit receive signal TOOL0 P40 23 1 SI RxD I O Transmit receive signal RESET Output Reset signal RESET 24 2 RESET Output VCC VDD I O VDD voltage generation power monitoring VDD 6 8 GND Ground VSS 5 7 REGCNote 4 6 FLMD1 EMVDD Driving power for TOOL pin VDD 6 8 Note Connect REGC pin to ground via a capacitor 0 47 to 1 F Remark Pins that are not indicat...

Page 690: ...nipulation such as writing and erasing via a dedicated single line UART 23 1 2 Communication mode Communication between the dedicated flash memory programmer and the RL78 G1P is established by serial communication using the TOOL0 pin via a dedicated single line UART of the RL78 G1P Transfer rate 1 M 500 k 250 k 115 2 kbps Figure 23 2 Communication with Dedicated Flash Memory Programmer VDD VSS REG...

Page 691: ...EGC pin to ground via a capacitor 0 47 to 1 F 23 2 Serial Programming Using External Device that Incorporates UART On board data writing to the internal flash memory is possible by using the RL78 G1P and an external device a microcontroller or ASIC connected to a UART On the development of flash memory programmer by user refer to the RL78 Microcontrollers RL78 Protocol A Programmer Edition Applica...

Page 692: ...SETOUT TxD RxD External device such as microcontroller and ASIC TOOLTxD TOOLRxD PORT TOOL0 RL78 G1P Note Connect REGC pin to ground via a capacitor 0 47 to 1 F The external device generates the following signals for the RL78 G1P Table 23 3 Pin Connection External Device RL78 G1P Signal Name I O Pin Function Pin Name VDD I O VDD voltage generation power monitoring VDD GND Ground VSS REGCNote RESETO...

Page 693: ... used as an output pin When this pin is used via pull down resistors use the 500 k or more resistors Remarks 1 tHD How long to keep the TOOL0 pin at the low level from when the external and internal resets end for setting of the flash memory programming mode see 27 9 Timing of Entry to Flash Memory Programming Modes 2 The SAU and IICA pins are not used for communication between the RL78 G1P and de...

Page 694: ...ze internal voltage 23 3 5 X1 and X2 pins Connect X1 and X2 in the same status as in the normal operation mode Remark In the flash memory programming mode the high speed on chip oscillator clock fIH is used 23 3 6 Power supply To use the supply voltage output of the flash memory programmer connect the VDD pin to VDD Note of the flash memory programmer and the VSS pin to GND of the flash memory pro...

Page 695: ...ister SFR 256 bytes RAM 1 5 KB General purpose register 32 bytes Code flash memory 16 KB Special function register 2nd SFR 2 KB Reserved Reserved Mirror area Data flash memory 2 KB Reserved Reserved 0 0 0 0 0 H E F F F F H F 0 0 0 0 H 0 3 F F F H F 4 0 0 0 H F 0 7 F F H F 0 8 0 0 H F F E D F H F F E E 0 H F F E F F H F F F 0 0 H F 3 F F F H F 4 0 0 0 H F 1 F F F H F 2 0 0 0 H F 1 7 F F H F 1 8 0 0...

Page 696: ...control register DFLCTL must be set up in order to use the data flash memory Manipulating the DFLCTL register is not possible while rewriting the data flash memory Transition the HALT STOP status is not possible while rewriting the data flash memory Caution The high speed on chip oscillator should be kept operating during data flash rewrite If it is kept stopping it should be operated HIOSTOP 0 Th...

Page 697: ...r rewritten to by using the data flash library Follow one of the procedures below when the DMA controller operates during access to the data flash memory A Hold DMA transfer pending or forcibly terminate it Before reading the data flash memory hold the DMA transfer pending in all the channels which are in use The data flash memory should be read 3 clocks fCLK or more after the DWAITn bit is set to...

Page 698: ...23 5 1 Controlling flash memory The following figure illustrates a flow for rewriting the code flash memory through serial programming Figure 23 7 Flash Memory Manipulation Procedure Start Manipulate flash memory End Yes Controlling TOOL0 pin and RESET pin No End Flash memory programming mode is set ...

Page 699: ...nish UART communication within 100 ms after the reset ends Figure 23 8 Setting of Flash Memory Programming Mode RESET TOOL0 1 2 3 tSUINIT 723 μs tHD processing time tSU 4 00H reception TOOLRxD TOOLTxD mode 1 The low level is input to the TOOL0 pin 2 The external reset ends POR and LVD reset must end before the external reset ends 3 The TOOL0 pin is set to the high level 4 Setting of the flash memo...

Page 700: ...e This can only be specified if the CMODE1 and CMODE0 bits of the option byte 000C2H are 1 Specify the mode that corresponds to the voltage range in which to write data When programming by using the dedicated flash memory programmer the mode is automatically selected by the voltage setting on GUI Remarks 1 Using both the wide voltage mode and full speed mode imposes no restrictions on writing dele...

Page 701: ...pecified area of the flash memory with data transmitted from the programmer Erase Block Erase Erases a specified area in the flash memory Blank check Block Blank Check Checks if a specified block in the flash memory has been correctly erased Write Programming Writes data to a specified area in the flash memory Note Getting information Silicon Signature Gets the RL78 G1P information such as the par...

Page 702: ...RL78 G1P CHAPTER 23 FLASH MEMORY R01UH0895EJ0100 Rev 1 00 683 Nov 29 2019 Table 23 8 Response Names Response Name Function ACK Acknowledges command data NAK Acknowledges illegal command data ...

Page 703: ...rea Sent from lower address Example 00000H to 0FFFFH 64 KB FFH FFH 00H 3 bytes Data flash memory area last address Last address of data flash memory area Sent from lower address Example F1000H to F1FFFH 4 KB FFH 1FH 0FH 3 bytes Firmware version Version information of firmware for programming Sent from upper address Example From Ver 1 23 01H 02H 03H 3 bytes Table 23 10 Example of Signature Data Fie...

Page 704: ...board programming However blocks can be written by means of self programming After the security settings are specified releasing the security settings by the Security Release command is enabled by a reset After the security settings are specified releasing the security settings by the Security Release command is enabled by a reset The block erase and write commands are enabled by the default setti...

Page 705: ...ogramming Valid Security Executed Command Block Erase Write Prohibition of block erase Blocks can be erased Can be performed Prohibition of writing Remark To prohibit writing and erasing during self programming use the flash sealed window function see 23 7 1 for detail Table 23 12 Setting Security in Each Programming Mode 1 On board off board programming Security Security Setting How to Disable Se...

Page 706: ...programming library refer to the RL78 Family Flash Self Programming Library Type 01 User s Manual R01US0050 2 For details of the time required to execute self programming see the notes on use that accompany the flash self programming library tool Similar to when writing data by using the flash memory programmer there are two flash memory programming modes for which the voltage range in which to wr...

Page 707: ...ing a self programming library Figure 23 10 Flow of Self programming Rewriting Flash Memory Initialize flash environment Flash memory control start Flash shield window setting Erase Write Flash information getting Close flash environment End Flash information setting Verify Inhibit access to flash memory Inhibit shifting STOP mode Inhibit clock stop ...

Page 708: ...ock 03H Block 05H Block 06H end block Block 04H start block Block 0FH Block 0EH On board off board programming Self programming On board off board programming Self programming On board off board programming Self programming Flash memory area Flash shield range Methods by which writing can be performed Window range Flash shield range 03FFFH 01C00H 01BFFH 01000H 00FFFH 00000H Caution The flash shiel...

Page 709: ...emory programmer Table 23 15 Processing Time for Each Command When PG FP6 Is in Use Reference Value PG FP6 Command Port TOOL0 UART Speed 1 Mbps 16 Kbytes Erasing 0 7 s Writing 1 0 8 s Verification 0 6 s Writing after erasing 1 2 s Remark The command processing times reference values shown in the table are typical values under the following conditions Port TOOL0 single line UART Speed 1 000 000 bps...

Page 710: ... memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used Figure 24 1 Connection Example of E1 E2 E2 Lite E20 On chip Debugging Emulator and RL78 G1P VDD TOOL0 VDD E1 E2 E2 Lite E20 target connector Reset circuit Reset signal GND GND GND GND TOOL0 Reset_o...

Page 711: ...FFFFFFFFFFFH for the ID code is not possible 24 3 Securing of User Resources To perform communication between the RL78 G1P and E1 E2 E2 Lite E20 on chip debugging emulator as well as each debug function the securing of memory space must be done beforehand If Renesas Electronics assembler or compiler is used the items can be set by using linker options 1 Securement of memory space The shaded portio...

Page 712: ...ibited SFR area 0 1 0 0 0 H 0 0 0 D 8 H 0 0 0 C E H 0 0 0 C 4 H 0 0 0 C 3 H 0 0 0 0 2 H 0 0 0 0 0 H Notes 1 Address of code flash memory is as follows Products Address of Note 1 RL78 G1P 03FFFH 2 When real time RAM monitor RRM function and dynamic memory modification DMM function are not used it is 256 bytes 3 In debugging reset vector is rewritten to address allocated to a monitor program 4 Since...

Page 713: ...D Correction Circuit The BCD correction circuit uses the following registers BCD correction result register BCDADJ 25 2 1 BCD correction result register BCDADJ The BCDADJ register stores correction values for obtaining the add subtract result as BCD code through add subtract instructions using the A register as the operand The value read from the BCDADJ register varies depending on the value of th...

Page 714: ...correction value and the correction result is stored in the A register and CY flag Caution The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags Therefore execute the instruction 3 after the instruction 2 instead of executing any other instructions To perform BCD correction in the interrupt enabled state saving and ...

Page 715: ...subtracting the value of the BCDADJ register correction value from the A register subtraction result in binary in binary and the correction result is stored in the A register and CY flag Caution The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags Therefore execute the instruction 3 after the instruction 2 instead ...

Page 716: ...100 Rev 1 00 697 Nov 29 2019 CHAPTER 26 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set For details of each operation and operation code refer to the separate document RL78 Family User s Manual Software ...

Page 717: ... or absolute names names in parentheses in the table below R0 R1 R2 etc can be used for description Table 26 1 Operand Identifiers and Specification Methods Identifier Description Method r rp sfr sfrp X R0 A R1 C R2 B R3 E R4 D R5 L R6 H R7 AX RP0 BC RP1 DE RP2 HL RP3 Special function register symbol SFR symbol FFF00H to FFFFFH Special function register symbols 16 bit manipulatable SFR symbol Even...

Page 718: ...ter pair HL HL register pair PC Program counter SP Stack pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag Memory contents indicated by address or register contents in parentheses XH XL XS XH XL 16 bit registers XH higher 8 bits XL lower 8 bits 20 bit registers XS bits 19 to 16 XH bits 15 to 8 XL bits 7 ...

Page 719: ...sible data area to the 1 MB space 00000H to FFFFFH by adding the ES register value to the 64 KB space from F0000H to FFFFFH When a PREFIX operation code is attached as a prefix to the target instruction only one instruction immediately after the PREFIX operation code is executed as the addresses with the ES register value added A interrupt and DTC transfer are not acknowledged between a PREFIX ins...

Page 720: ...t data transfer MOV r byte 2 1 r byte PSW byte 3 3 PSW byte CS byte 3 1 CS byte ES byte 2 1 ES byte addr16 byte 4 1 addr16 byte ES addr16 byte 5 2 ES addr16 byte saddr byte 3 1 saddr byte sfr byte 3 1 sfr byte DE byte byte 3 1 DE byte byte ES DE byte byte 4 2 ES DE byte byte HL byte byte 3 1 HL byte byte ES HL byte byte 4 2 ES HL byte byte SP byte byte 3 1 SP byte byte word B byte 4 1 B word byte ...

Page 721: ...Y 8 bit data transfer MOV A sfr 2 1 A sfr sfr A 2 1 sfr A A DE 1 1 4 A DE DE A 1 1 DE A A ES DE 2 2 5 A ES DE ES DE A 2 2 ES DE A A HL 1 1 4 A HL HL A 1 1 HL A A ES HL 2 2 5 A ES HL ES HL A 2 2 ES HL A A DE byte 2 1 4 A DE byte DE byte A 2 1 DE byte A A ES DE byte 3 2 5 A ES DE byte ES DE byte A 3 2 ES DE byte A A HL byte 2 1 4 A HL byte HL byte A 2 1 HL byte A A ES HL byte 3 2 5 A ES HL byte ES H...

Page 722: ...n Flag Note 1 Note 2 Z AC CY 8 bit data transfer MOV A HL B 2 1 4 A HL B HL B A 2 1 HL B A A ES HL B 3 2 5 A ES HL B ES HL B A 3 2 ES HL B A A HL C 2 1 4 A HL C HL C A 2 1 HL C A A ES HL C 3 2 5 A ES HL C ES HL C A 3 2 ES HL C A X addr16 3 1 4 X addr16 X ES addr16 4 2 5 X ES addr16 X saddr 2 1 X saddr B addr16 3 1 4 B addr16 B ES addr16 4 2 5 B ES addr16 B saddr 2 1 B saddr C addr16 3 1 4 C addr16...

Page 723: ...Flag Note 1 Note 2 Z AC CY 8 bit data transfer XCH A HL B 2 2 A HL B A ES HL B 3 3 A ES HL B A HL C 2 2 A HL C A ES HL C 3 3 A ES HL C ONEB A 1 1 A 01H X 1 1 X 01H B 1 1 B 01H C 1 1 C 01H addr16 3 1 addr16 01H ES addr16 4 2 ES addr16 01H saddr 2 1 saddr 01H CLRB A 1 1 A 00H X 1 1 X 00H B 1 1 B 00H C 1 1 C 00H addr16 3 1 addr16 00H ES addr16 4 2 ES addr16 00H saddr 2 1 saddr 00H MOVS HL byte X 3 1 ...

Page 724: ...ransfer MOVW AX DE 1 1 4 AX DE DE AX 1 1 DE AX AX ES DE 2 2 5 AX ES DE ES DE AX 2 2 ES DE AX AX HL 1 1 4 AX HL HL AX 1 1 HL AX AX ES HL 2 2 5 AX ES HL ES HL AX 2 2 ES HL AX AX DE byte 2 1 4 AX DE byte DE byte AX 2 1 DE byte AX AX ES DE byte 3 2 5 AX ES DE byte ES DE byte AX 3 2 ES DE byte AX AX HL byte 2 1 4 AX HL byte HL byte AX 2 1 HL byte AX AX ES HL byte 3 2 5 AX ES HL byte ES HL byte AX 3 2 E...

Page 725: ... AC CY 16 bit data transfer MOVW BC addr16 3 1 4 BC addr16 BC ES addr16 4 2 5 BC ES addr16 DE addr16 3 1 4 DE addr16 DE ES addr16 4 2 5 DE ES addr16 HL addr16 3 1 4 HL addr16 HL ES addr16 4 2 5 HL ES addr16 BC saddrp 2 1 BC saddrp DE saddrp 2 1 DE saddrp HL saddrp 2 1 HL saddrp XCHW AX rp Note 3 1 1 AX rp ONEW AX 1 1 AX 0001H BC 1 1 BC 0001H CLRW AX 1 1 AX 0000H BC 1 1 BC 0000H 8 bit operation ADD...

Page 726: ...saddr byte 3 2 saddr CY saddr byte CY A rv Note 3 2 1 A CY A r CY r A 2 1 r CY r A CY A addr16 3 1 4 A CY A addr16 CY A ES addr16 4 2 5 A CY A ES addr16 CY A saddr 2 1 A CY A saddr CY A HL 1 1 4 A CY A HL CY A ES HL 2 2 5 A CY A ES HL CY A HL byte 2 1 4 A CY A HL byte CY A ES HL byte 3 2 5 A CY A ES HL byte CY A HL B 2 1 4 A CY A HL B CY A ES HL B 3 2 5 A CY A ES HL B CY A HL C 2 1 4 A CY A HL C C...

Page 727: ...yte 2 1 A CY A byte CY saddr byte 3 2 saddr CY saddr byte CY A r Note 3 2 1 A CY A r CY r A 2 1 r CY r A CY A addr16 3 1 4 A CY A addr16 CY A ES addr16 4 2 5 A CY A ES addr16 CY A saddr 2 1 A CY A saddr CY A HL 1 1 4 A CY A HL CY A ES HL 2 2 5 A CY A ES HL CY A HL byte 2 1 4 A CY A HL byte CY A ES HL byte 3 2 5 A CY A ES HL byte CY A HL B 2 1 4 A CY A HL B CY A ES HL B 3 2 5 A CY A ES HL B CY A HL...

Page 728: ...Note 1 Note 2 Z AC CY 8 bit operation OR A byte 2 1 A A byte saddr byte 3 2 saddr saddr byte A r Note 3 2 1 A A r r A 2 1 r r A A addr16 3 1 4 A A addr16 A ES addr16 4 2 5 A A ES addr16 A saddr 2 1 A A saddr A HL 1 1 4 A A H A ES HL 2 2 5 A A ES HL A HL byte 2 1 4 A A HL byte A ES HL byte 3 2 5 A A ES HL byte A HL B 2 1 4 A A HL B A ES HL B 3 2 5 A A ES HL B A HL C 2 1 4 A A HL C A ES HL C 3 2 5 A...

Page 729: ...struction Group Mnemonic Operands Bytes Clocks Operation Flag Note 1 Note 2 Z AC CY 8 bit operation CMP A byte 2 1 A byte addr16 byte 4 1 4 addr16 byte ES addr16 byte 5 2 5 ES addr16 byte saddr byte 3 1 saddr byte A r Note 3 2 1 A r r A 2 1 r A A addr16 3 1 4 A addr16 A ES addr16 4 2 5 A ES addr16 A saddr 2 1 A saddr A HL 1 1 4 A HL A ES HL 2 2 5 A ES HL A HL byte 2 1 4 A HL byte A ES HL byte 3 2 ...

Page 730: ...6 bit operation ADDW AX word 3 1 AX CY AX word AX AX 1 1 AX CY AX AX AX BC 1 1 AX CY AX BC AX DE 1 1 AX CY AX DE AX HL 1 1 AX CY AX HL AX addr16 3 1 4 AX CY AX addr16 AX ES addr16 4 2 5 AX CY AX ES addr16 AX saddrp 2 1 AX CY AX saddrp AX HL byte 3 1 4 AX CY AX HL byte AX ES HL byte 4 2 5 AX CY AX ES HL byte SUBW AX word 3 1 AX CY AX word AX BC 1 1 AX CY AX BC AX DE 1 1 AX CY AX DE AX HL 1 1 AX CY ...

Page 731: ...umu late MULU X 1 1 AX A X Notes 1 Number of CPU clocks fCLK when the internal RAM area SFR area or extended SFR area is accessed or when no data is accessed 2 Number of CPU clocks fCLK when the program memory area is accessed Remark Number of clock is when program exists in the internal ROM flash memory area If fetching the instruction from the internal RAM area the number becomes double number p...

Page 732: ... HL byte 3 2 HL byte HL byte 1 ES HL byte 4 3 ES HL byte ES HL byte 1 DEC r 1 1 r r 1 addr16 3 2 addr16 addr16 1 ES addr16 4 3 ES addr16 ES addr16 1 saddr 2 2 saddr saddr 1 HL byte 3 2 HL byte HL byte 1 ES HL byte 4 3 ES HL byte ES HL byte 1 INCW rp 1 1 rp rp 1 addr16 3 2 addr16 addr16 1 ES addr16 4 3 ES addr16 ES addr16 1 saddrp 2 2 saddrp saddrp 1 HL byte 3 2 HL byte HL byte 1 ES HL byte 4 3 ES ...

Page 733: ...m 1 RORC A 1 2 1 CY A0 A7 CY Am 1 Am 1 ROLC A 1 2 1 CY A7 A0 CY Am 1 Am 1 ROLWC AX 1 2 1 CY AX15 AX0 CY AXm 1 AXm 1 BC 1 2 1 CY BC15 BC0 CY BCm 1 BCm 1 Bit manipulate MOV1 CY A bit 2 1 CY A bit A bit CY 2 1 A bit CY CY PSW bit 3 1 CY PSW bit PSW bit CY 3 4 PSW bit CY CY saddr bit 3 1 CY saddr bit saddr bit CY 3 2 saddr bit CY CY sfr bit 3 1 CY sfr bit sfr bit CY 3 2 sfr bit CY CY HL bit 2 1 4 CY H...

Page 734: ... Mnemonic Operands Bytes Clocks Operation Flag Note 1 Note 2 Z AC CY Bit manipulate XOR1 CY A bit 2 1 CY CY A bit CY PSW bit 3 1 CY CY PSW bit CY saddr bit 3 1 CY CY saddr bit CY sfr bit 3 1 CY CY sfr bit CY HL bit 2 1 4 CY CY HL bit CY ES HL bit 3 2 5 CY CY ES HL bit SET1 A bit 2 1 A bit 1 PSW bit 3 4 PSW bit 1 addr16 bit 4 2 addr16 bit 1 ES addr16 bit 5 3 ES addr16 bit 1 saddr bit 3 2 saddr bit ...

Page 735: ...ction Group Mnemonic Operands Bytes Clocks Operation Flag Note 1 Note 2 Z AC CY Call return CALL rp 2 3 SP 2 PC 2 S SP 3 PC 2 H SP 4 PC 2 L PC CS rp SP SP 4 addr20 3 3 SP 2 PC 3 S SP 3 PC 3 H SP 4 PC 3 L PC PC 3 jdisp16 SP SP 4 addr16 3 3 SP 2 PC 3 S SP 3 PC 3 H SP 4 PC 3 L PC 0000 addr16 SP SP 4 addr20 4 3 SP 2 PC 4 S SP 3 PC 4 H SP 4 PC 4 L PC addr20 SP SP 4 CALLT addr5 2 5 SP 2 PC 2 S SP 3 PC 2...

Page 736: ... SP 2 R R R rp 1 1 rpL SP rpH SP 1 SP SP 2 MOVW SP word 4 1 SP word SP AX 2 1 SP AX AX SP 2 1 AX SP HL SP 3 1 HL SP BC SP 3 1 BC SP DE SP 3 1 DE SP ADDW SP byte 2 1 SP SP byte SUBW SP byte 2 1 SP SP byte Un conditional branch BR AX 2 3 PC CS AX addr20 2 3 PC PC 2 jdisp8 addr20 3 3 PC PC 3 jdisp16 addr16 3 3 PC 0000 addr16 addr20 4 3 PC addr20 Conditional branch BC addr20 2 2 4 Note 3 PC PC 2 jdisp...

Page 737: ... 5 Note 3 PC PC 3 jdisp8 if A bit 0 PSW bit addr20 4 3 5 Note 3 PC PC 4 jdisp8 if PSW bit 0 HL bit addr20 3 3 5 Note 3 6 7 PC PC 3 jdisp8 if HL bit 0 ES HL bit addr20 4 4 6 Note 3 7 8 PC PC 4 jdisp8 if ES HL bit 0 BTCLR saddr bit addr20 4 3 5 Note 3 PC PC 4 jdisp8 if saddr bit 1 then reset saddr bit sfr bit addr20 4 3 5 Note 3 PC PC 4 jdisp8 if sfr bit 1 then reset sfr bit A bit addr20 3 3 5 Note ...

Page 738: ...t use the on chip debug function in products designated for mass production because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used and product reliability therefore cannot be guaranteed Renesas Electronics is not liable for problems occurring when the on chip debug function is used 2 The pins mounted depend on the product See 2 1 Pin Functi...

Page 739: ... 0 3Notes 2 3 V Notes 1 Connect the REGC pin to Vss via a capacitor 0 47 to 1 F This value regulates the absolute maximum rating of the REGC pin Do not use this pin with voltage applied to it 2 Must be 4 6 V or lower 3 Do not exceed AVREF 0 3 V in case of A D conversion target pin Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That ...

Page 740: ...P61 100 mA IOL2 Per pin P20 to P27 1 mA Total of all pins 5 mA Operating ambient temperature TA In normal operation mode 40 to 85 C In flash memory programming mode 0 to 40 Storage temperature Tstg 65 to 150 C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is...

Page 741: ... the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register OSTS after sufficiently evaluating the oscillation stabilization time with the resonator to be used Remark When using the X1 oscillator refer to 5 4 System Clock Oscillator 27 2 2 On chip oscillator characteristics TA 40 to 85 C 2 7 V VDD 3 6 V VSS 0 V Oscillators Parameters Conditions M...

Page 742: ...even if the current flows from the VDD pin to an output pin 2 Do not exceed the total current value 3 Specification under conditions where the duty factor 70 The output current value that has changed to the duty factor 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n Total output current of pins IOH 0 7 n 0 01 Example Where n 80 and IOH 1...

Page 743: ...e current flows from an output pin to the VSS pin 2 However do not exceed the total current value 3 Specification under conditions where the duty factor 70 The output current value that has changed to the duty factor 70 the duty ratio can be calculated with the following expression when changing the duty factor from 70 to n Total output current of pins IOL 0 7 n 0 01 Example Where n 80 and IOL 35 ...

Page 744: ...tput voltage low VOL1 P10 to P17 P30 to P35 P40 IOL1 3 0 mA 0 6 V IOL1 1 5 mA 0 4 V VOL2 P20 to P27 IOL2 400 A 0 4 V VOL3 P60 P61 IOL3 3 0 mA 0 4 V Input leakage current high ILIH1 P10 to P17 P20 to P27 P30 to P35 P40 P137 RESET VI VDD 1 A ILIH2 P121 P122 X1 X2 EXCLK VI VDD In input port or external clock input 1 A In resonator connection 10 A Input leakage current low ILIL1 P10 to P17 P20 to P27 ...

Page 745: ...LS low speed main modeNote 4 fMX 8 MHzNote 2 VDD 3 0 V Normal operation Square wave input 1 2 2 0 mA Resonator connection 1 2 2 0 Notes 1 Total current flowing into VDD including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS The values below the MAX column include the peripheral operation current However not including the current flowing into the A D conv...

Page 746: ... flowing into VDD including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS The values below the MAX column include the peripheral operation current However not including the current flowing into the A D converter D A converter LVD circuit I O port and on chip pull up pull down resistors and the current flowing during data flash rewrite 2 During HALT instru...

Page 747: ...including the operating current of the 15 kHz low speed on chip oscillator The supply current of the RL78 microcontrollers is the sum of IDD1 IDD2 or IDD3 and IWDT when the watchdog timer is in operation 4 Current flowing only to the A D converter The supply current of the RL78 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A D converter operates in an operation mode or the HALT mod...

Page 748: ...k frequency fEX 1 0 20 0 MHz External system clock input high level width low level width tEXH tEXL 24 ns TI00 to TI03 input high level width low level width tTIH tTIL 1 fMCK 10 ns TO00 to TO03 output frequency fTO HS high speed main mode 8 MHz LS low speed main mode 4 MHz PCLBUZ0 PCLBUZ1 output frequency fPCL HS high speed main mode 8 MHz LS low speed main mode 4 MHz Interrupt input high level wi...

Page 749: ...ion Execution Time during Main System Clock Operation TCY vs VDD HS high speed main mode 1 0 0 1 0 10 1 0 2 0 3 0 4 0 0 01 0 03125 0 05 Cycle time T CY μs Supply voltage VDD V During self programming When high speed system clock is selected When the high speed on chip oscillator clock is selected 2 7 3 6 ...

Page 750: ...0 0 1 0 10 1 0 2 0 3 0 4 0 0 01 Cycle time T CY μs Supply voltage VDD V 0 125 During self programming When high speed system clock is selected When the high speed on chip oscillator clock is selected 2 7 3 6 AC Timing Test Points VIH VOH VIL VOL Test points VIH VOH VIL VOL External System Clock Timing EXCLK 1 fEX tEXL tEXH ...

Page 751: ...TER 27 ELECTRICAL SPECIFICATIONS R01UH0895EJ0100 Rev 1 00 732 Nov 29 2019 TI TO Timing tTIL tTIH 1 fTO TO00 to TO03 TI00 to T03 Interrupt Request Input Timing INTP0 to INTP5 tINTL tINTH RESET Input Timing RESET tRSL ...

Page 752: ... fCLK Note 2 5 3 1 3 Mbps UART mode connection diagram during communication at same potential RL78 microcontroller TxDq RxDq Rx Tx User s device UART mode bit width during communication at same potential reference Baud rate error tolerance High Low bit width 1 Transfer rate TxDq RxDq Notes 1 Transfer rate in the SNOOZE mode is 4800 bps only 2 The maximum operating frequencies of the CPU peripheral...

Page 753: ...10 ns Delay time from SCKp to SOp output Note 2 tKSO1 C 20 pF Note 3 10 10 ns Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The SIp setup time becomes to SCKp and the SIp hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The delay time to SOp output becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn ...

Page 754: ... 2 fMCK 44 2 fMCK 110 ns SSI00 setup time tSSIK DAPmn 0 120 120 ns DAPmn 1 1 fMCK 120 1 fMCK 120 ns SSI00 hold time tKSSI DAPmn 0 1 fMCK 120 1 fMCK 120 ns DAPmn 1 120 120 ns Notes 1 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 The SIp setup time becomes to SCKp and the SIp hold time becomes from SCKp when DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 2 When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn...

Page 755: ...ication at same potential When DAPmn 0 and CKPmn 0 or DAPmn 1 and CKPmn 1 SIp SOp tKCY1 2 tKL1 2 tKH1 2 tSIK1 2 tKSI1 2 Input data tKSO1 2 Output data SCKp SSI00 tSSIK tKSSI CSI mode serial transfer timing during communication at same potential When DAPmn 0 and CKPmn 1 or DAPmn 1 and CKPmn 0 SIp Input data Output data SOp tKCY1 2 tKH1 2 tKL1 2 tSIK1 2 tKSI1 2 tKSO1 2 SCKp SSI00 tSSIK tKSSI Remarks...

Page 756: ...d time transmission Note 2 tHD DAT 0 3 45 0 0 9 0 0 45 s Setup time of stop condition tSU STO 4 0 0 6 0 26 s Bus free time tBUF 4 7 1 3 0 5 s Notes 1 The first clock pulse is generated after this period when the start restart condition is detected 2 The maximum value MAX of tHD DAT is during normal transfer and a wait state is inserted in the ACK acknowledge timing Remarks 1 The maximum value of C...

Page 757: ...EFP ANI0 ADREFP1 0 ADREFP0 1 AVREF AVREFM ANI1 ADREFM 1 target ANI pin ANI0 to ANI7 TA 40 to 85 C 2 7 V VDD 3 6 V VSS 0 V Reference voltage AVREFP Reference voltage AVREFM 0 V Parameter Symbol Conditions MIN TYP MAX Unit Resolution RES 8 12 bit Overall errorNote 1 AINL 12 bit resolution AVREFP VDD 6 0 LSB Conversion time tCONV 12 bit resolution AVREFP VDD 3 375 108 s Zero scale errorNotes 1 2 EZS ...

Page 758: ... ratio FSR to the full scale value 3 When AVREF AVREFP ANI0 ADREFP1 0 ADREFP0 1 AVREF AVREFM ANI1 ADREFM 1 target ANI pin ANI16 internal reference voltage and temperature sensor output voltage TA 40 to 85 C 2 7 V VDD 3 6 V VSS 0 V Reference voltage AVREFP Reference voltage AVREFM 0 V Parameter Symbol Conditions MIN TYP MAX Unit Resolution RES 8 12 bit Overall errorNote 1 AINL 12 bit resolution AVR...

Page 759: ...LSB Analog input voltage VAIN 0 VDD V VBGR Select internal reference voltage output 2 7 V VDD 3 6 V HS high speed main mode 1 38 1 45 1 5 V Notes 1 Excludes quantization error 1 2 LSB 2 This value is indicated as a ratio FSR to the full scale value 5 When AVREF Internal reference voltage ADREFP1 1 ADREFP0 0 AVREF AVREFM ANI1 ADREFM 1 target ANI pin ANI0 to ANI7 ANI16 TA 40 to 85 C 2 7 V VDD 3 6 V ...

Page 760: ... 45 1 5 V Temperature coefficient FVTMPS Temperature sensor that depends on the temperature 3 6 mV C Operation stabilization wait time tAMP 5 s 27 6 3 D A converter TA 40 to 85 C 2 7 V VDD 3 6 V VSS 0 V Parameter Symbol Conditions MIN TYP MAX Unit Resolution RES 10 bit Overall error AINL Load current 0 mA 0 2 V output voltage VDD 0 2 V 2 0 4 0 LSB Load 2 5 kΩ 0 2 V output voltage VDD 0 2 V 5 0 10 ...

Page 761: ...ower supply fall time 1 46 1 50 1 54 V Minimum pulse width Note TPW 300 s Note Minimum time required for a POR reset when VDD exceeds below VPDR This is also the minimum time required for a POR reset from when VDD exceeds below 0 7 V to when VDD exceeds VPOR while STOP mode is entered or the main system clock is stopped through setting bit 0 HIOSTOP and bit 7 MSTOP in the clock operation status co...

Page 762: ...m pulse width tLW 300 s Detection delay time 300 s LVD Detection Voltage of Interrupt Reset Mode TA 40 to 85 C VPDR VDD 3 6 V VSS 0 V Parameter Symbol Conditions MIN TYP MAX Unit Detection voltage VLVD5 VPOC2 VPOC1 VPOC0 0 1 1 falling reset voltage 2 70 2 75 2 81 V VLVD4 LVIS1 LVIS0 1 0 Rising release reset voltage 2 86 2 92 2 97 V Falling interrupt voltage 2 80 2 86 2 91 V VLVD3 LVIS1 LVIS0 0 1 R...

Page 763: ...40 to 85 C 2 7 V VDD 3 6 V VSS 0 V Parameter Symbol Conditions MIN TYP MAX Unit System clock frequency fCLK 2 7 V VDD 3 6 V 1 32 MHz Number of code flash rewrites Note 1 2 3 Cerwr Retained for 20 years TA 85 C 1 000 Times Number of data flash rewrites Note 1 2 3 Retained for 1 years TA 25 C 1 000 000 Retained for 5 years TA 85 C 100 000 Operating ambient temperature In flash memory programming mod...

Page 764: ...re to control the flash memory tHD POR and LVD reset must end before the external reset ends 1 ms RESET 1 2 3 4 00H reception TOOLRxD TOOLTxD mode tSUINIT tSU TOOL0 723 μs tHD processing time 1 The low level is input to the TOOL0 pin 2 The external reset ends POR and LVD reset must end before the external reset ends 3 The TOOL0 pin is set to the high level 4 Setting of the flash memory programming...

Page 765: ... C B 2X aaa C A3 A1 A eee C fff C A B fff C A B A E e 24 19 18 13 12 7 1 6 EXPOSED DIE PAD INDEX AREA D 2 X E 2 Reference Symbol Dimension in Millimeters Min Nom Max A 0 80 A1 0 00 0 02 0 05 A3 0 203 REF b 0 18 0 25 0 30 D 4 00 BSC E 4 00 BSC e 0 50 BSC L 0 35 0 40 0 45 K 0 20 D2 2 55 2 60 2 65 E2 2 55 2 60 2 65 aaa 0 15 bbb 0 10 ccc 0 10 ddd 0 05 eee 0 08 fff 0 10 JEITA Package code RENESAS code ...

Page 766: ...2 x b p e H E E D H D Z D Z E Detail F L 1 L A c A 2 A 1 Previous Code JEITA Package Code RENESAS Code PLQP0032GB A 32P6U A MASS Typ 0 2g P LQFP32 7x7 0 80 1 0 0 125 0 35 0 7 0 7 0 20 0 20 0 145 0 09 0 42 0 37 0 32 Max Nom Min Dimension in Millimeters Symbol Reference 7 1 7 0 6 9 D 7 1 7 0 6 9 E 1 4 A 2 9 2 9 0 8 8 9 2 9 0 8 8 1 7 A 0 2 0 1 0 0 7 0 5 0 3 L x 8 0 c 0 8 e 0 10 y H D H E A 1 b p b 1 ...

Page 767: ... G1P APPENDIX A REVISION HISTORY R01UH0895EJ0100 Rev 1 00 748 Nov 29 2019 APPENDIX A REVISION HISTORY A 1 Major Revisions in This Edition Edition Description Chapter Rev 1 00 First edition issued Throughout ...

Page 768: ...RL78 G1P User s Manual Hardware Publication Date Rev 1 00 Nov 29 2019 Published by Renesas Electronics Corporation ...

Page 769: ...l 86 21 2226 0888 Fax 86 21 2226 0999 Renesas Electronics Hong Kong Limited Unit 1601 1611 16 F Tower 2 Grand Century Place 193 Prince Edward Road West Mongkok Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2886 9022 Renesas Electronics Taiwan Co Ltd 13F No 363 Fu Shing North Road Taipei 10543 Taiwan Tel 886 2 8175 9600 Fax 886 2 8175 9670 Renesas Electronics Singapore Pte Ltd 80 Bendemeer Road Unit ...

Page 770: ...RL78 G1P R01UH0895EJ0100 ...

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