RL78/G1P
CHAPTER 12 SERIAL INTERFACE IICA
R01UH0895EJ0100 Rev.1.00
464
Nov 29, 2019
CHAPTER 12 SERIAL INTERFACE IICA
The RL78/G1P has two units of serial interface IICA and support two slave addresses.
When using IICA0 and IICA1 as slaves, the corresponding slave can communicate with the master when either one of
the slave addresses matches an address received from the I
2
C bus.
12.1 Functions of Serial Interface IICA
Serial interface IICA has the following three modes.
(1) Operation stop mode
This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
(2) I
2
C bus mode (multimaster supported)
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLAn) line and a serial
data bus (SDAAn) line.
This mode complies with the I
2
C bus format and the master device can generated “start condition”, “address”,
“transfer direction specification”, “data”, and “stop condition” data to the slave device, via the serial data bus. The
slave device automatically detects these received status and data by hardware. This function can simplify the part
of application program that controls the I
2
C bus.
Since the SCLAn and SDAAn pins are used for open drain outputs, serial interface IICA requires pull-up resistors
for the serial clock line and the serial data bus line.
(3) Wakeup mode
The STOP mode can be released by generating an interrupt request signal (INTIICAn) when an extension code
from the master device or a local address has been received while in STOP mode. This can be set by using the
WUPn bit of IICA control register n1 (IICCTLn1).
Figure 12-1 shows a block diagram of serial interface IICA.
Remark
n = 0, 1
Summary of Contents for RL78/G1P
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