Renesas M3A-HS64, User Manual

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M3A-HS64G01 Functions
3.2.4 SH7264 Multiplex Pins Used on the M3A-HS64G01
Rev. 1.00 Apr 30, 2009
3-10
REJ11J0034-0100
3
3.2.4 SH7264 Multiplex Pins Used on the M3A-HS64G01
Table 3.2.8 to Table 3.2.20 list SH7264 multiplex pin functions used on the M3A-HS64G01.
These multiplex pins are set as port input pins by default. Set the MD bit in the port control register to use the SH7264 peripheral
functions (except I/O ports).
Table 3.2.8 SH7264 Multiplex Pin Functions (BSC)
SH7264 Port Control Register Peripheral
Function
Pin Name
Register Name MD bit Setting
SH7264
Multiplex Pin Name
BSC CS0# PCCR0 PC0MD0 = B'1 PC0/ CS0#
(1)
CS3# PCCR2 PC8MD[1:0] = B'01 PC8/ CS3# /TIOC4D/IRQ7
RD# PCCR0 PC1MD0 = B'1 PC1/ RD#
(1)
WE0#/DQML PCCR0 PC3MD0 = B'1 PC3/ WE0#/DQML
WE1#/DQMU/WE# PCCR1 PC4MD0 = B'1 PC4/ WE1#/DQMU/WE#
RAS# PCCR1 PC5MD[1:0] = B'01 PC5/ RAS# /TIOC4A/IRQ4
CAS# PCCR1 PC6MD[1:0] = B'01 PC6/ CAS# /TIOC4B/IRQ5
CKE PCCR1 PC7MD[1:0] = B'01 PC7/ CKE /TIOC4C/IRQ6
RD/WR# PCCR0 PC2MD0 = B'1 PC2/ RD/WR#
A21 PBCR5 PB21MD0 = B'1 PB21/ A21
D15 PDCR3 PD15MD[1:0] = B'01 PD15/ D15/NAF7 /PWM2H
(1)
D14 PDCR3 PD14MD[1:0] = B'01 PD14/ D14/NAF6 /PWM2G
(1)
D13 PDCR3 PD13MD[1:0] = B'01 PD13/ D13/NAF5 /PWM2F
(1)
D12 PDCR3 PD12MD[1:0] = B'01 PD12/ D12/NAF4 /PWM2E
(1)
D11 PDCR2 PD11MD[1:0] = B'01 PD11/ D11/NAF3 /PWM2D
(1)
D10 PDCR2 PD10MD[1:0] = B'01 PD10/ D10/NAF2 /PWM2C
(1)
D9 PDCR2 PD9MD[1:0] = B'01 PD9/ D9/NAF1 /PWM2B
(1)
D8 PDCR2 PD8MD[1:0] = B'01 PD8/ D8/NAF0 /PWM2A
(1)
D7 PDCR1 PD7MD[1:0] = B'01 PD7/ D7/FWE# /PWM1H
(1)
D6 PDCR1 PD6MD[1:0] = B'01 PD6/ D6/FALE /PWM1G
(1)
D5 PDCR1 PD5MD[1:0] = B'01 PD5/ D5/FCLE /PWM1F
(1)
D4 PDCR1 PD4MD[1:0] = B'01 PD4/ D4/FRE# /PWM1E
(1)
D3 PDCR0 PD3MD[1:0] = B'01 PD3/ D3 /PWM1D
(1)
D2 PDCR0 PD2MD[1:0] = B'01 PD2/ D2 /PWM1C
(1)
D1 PDCR0 PD1MD[1:0] = B'01 PD1/ D1 /PWM1B
(1)
D0 PDCR0 PD0MD[1:0] = B'01 PD0/ D0 /PWM1A
(1)
Note 1: For boot modes 1 to 3
Table 3.2.9 SH7264 Multiplex Pin Functions (INTC)
SH7264 Port Control Register Peripheral
Function
Pin Name
Register Name MD bit Setting
SH7264
Multiplex Pin Name
INTC IRQ1 PJCR0 PJ3MD[1:0] = B'11 PJ3/CRx1/CRx0&CRx1/ IRQ1
IRQ1 PECR0 PE1MD[2:0] = B'011 PE1/SDA0/IOIS16#/ IRQ1 /TCLKA/ADTRG#
Table 3.2.10 SH7264 Multiplex Pin Functions (SCIF)
SH7264 Port Control Register Peripheral
Function
Pin Name
Register Name MD bit Setting
SH7264
Multiplex Pin Name
SCIF RTS3# PJCR2 PJ8MD[1:0] = B'10 PJ8/PWM2E/ RTS3#
CTS3# PJCR1 PJ7MD[1:0] = B'10 PJ7/TIOC1B/ CTS3#
SCK3 PJCR1 PJ6MD[1:0] = B'10 PJ6/TIOC1A/ SCK3
TxD3 PJCR1 PJ5MD[1:0] = B'10 PJ5/IERxD/ TxD3
RxD3 PJCR1 PJ4MD[1:0] = B'10 PJ4/IETxD/ RxD3
RxD0 PJCR0 PJ1MD[2:0] = B'100 PJ1/CRx0/IERxD/IRQ0/ RxD0
TxD0 PJCR0 PJ0MD[2:0] = B'100 PJ0/CTx0/IETxD/CS1#/ TxD0 /A0