Renesas M3A-HS64, User Manual

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M3A-HS64 Functions
2.3.2 NOR Flash Memory Interface
Rev. 1.00 Apr 30, 2009
2-13
REJ11J0034-0100
2
Table 2.3.2 DIP Switches Setting (SW6-1)
Function
Number
OFF (High) ON (Low)
SW6-1 NOR flash memory is write-enabled (default) NOR flash memory is write-protected
The figure below shows the write and read access timing example of the NOR flash memory. The table below lists the bus state
controller settings (write/read) when the SH7264 bus clock works at 72 MHz.
Write and read timing
Write1 Write2 Read1
DATA DATA DATA
tDF(C
tDF(OE) tDF(CE)
ta(AD)
ta(OE)
tWDH1 tWDD1 tW DH1 tWDD1
tWED1 tWED1 tWED1 tWED1
tRSD tRSD
tCSD1 tCSD1 tCSD1 tCSD1 tCSD1 tCSD1
tAD1 tAD1 tAD1 tAD1 tAD1 tAD1
tRDH1
tRDS1 tDH
tDS
tDH
tDS
tOEH
tAH
tCH
tWP
tAS
tWPH tWP
tAH
tWPH
tCH
tW P tAS
tCS
tW P
tRC tRC tWC tWC
T1 T2 Tw 4 T1 Tw 1 Tw 2 Tw 1 Tw 2 T2 T1 Tw 1 Tw 2 Tw 3 T2 Tf Tf Taw 1 Taw 1 Th Th Th Tf Tw 3 Tw 3 Tw 4 Taw 2 Taw 2 Tw 4
CKIO
A21-A1
CS0#
RD#
WE0#
D15-D0
Figure 2.3.2 NOR Flash Memory write/read Access Timing Example
Table 2.3.3 Bus State Controller Setting (Write and read the NOR flash memory)
User area Target device Setting
CS0 S29GL032N90TFI020 CS0 Space Bus Control Register (CS0BCR):
Initial value: H'36DB 0400 (MD = Low)
Recommended value: H'1240 0400
•
Idle Cycles between Write-Read Cycles and Write-Write Cycles
IWW[2:0] = B'001; 1 idle cycle inserted
•
Idle Cycles for Another Space Read-Write
IWRWD[2:0] = B'001; 1 idle cycle inserted
•
Idle Cycles for Read-Write in the Same Space
IWRWS[2:0] = B'001; 1 idle cycle inserted
•
Data bus width
BSZ[1:0] = B'10; 16-bit
CS0 Space Wait Control Register (CS0WCR):
Initial value: H'0000 0500
Recommended value: H'0000 0B41
•
Number of Delay Cycles from address, CS0# Assertion to RD#, WEn# Assertion:
SW[1:0] = B'01; 1.5 cycles
•
Number of Access Wait Cycles
WR[3:0] = B'0110; 6 cycles
•
External WAIT Mask Specification
WM = B’1; Ignore external WAIT input
•
Number of Delay Cycles from RD#, WEn# Negation to address, CS0# Negation
HW[1:0] = B'01; 1.5 cycles