Renesas M3A-HS64, User Manual

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M3A-HS64G02 Functions
4.10 PWM Interface
Rev. 1.00 Apr 30, 2009 4-23
REJ11J0034-0100
4
4.10 PWM Interface
The SH7264 includes two channels of on-chip Motor Control Pulse Width Modulator (PWM) timer with a maximum of eight
pulse outputs per channel. The SH7264 PWM output pin is connected to a 20-pin MIL-spec connector on the M3A-HS64G02 via
the voltage level shifter. The PWM output pin is also used as the SDHI pin and SSIF channel 0 pin.
The figure below shows the PWM interface block diagram. The table below lists the jumper setting (JP3).
SH7264
PK0/ PWM1A /SD_D2
PK1/ PWM1B /SD_D3
PK2/ PWM1C /SD_CMD
PK3/ PWM1D /SD_CLK
PK4/ PWM1E /SD_D0
PK5/ PWM1F /SD_D1
PK6/ PWM1G /SD_WP
PK7/ PWM1H /SD_CD
D1
S1A
S1B
D2
S2A
S2B
D3
S3A
S3B
D4
S4A
S4B
MUX
EN# IN
PWM or SD
D1
S1A
S1B
D2
S2A
S2B
D3
S3A
S3B
D4
S4A
S4B
MUX
EN# IN
PWM or SD
D1
S1A
S1B
D2
S2A
S2B
D3
S3A
S3B
D4
S4A
S4B
MUX
EN# IN
PWM or SSIF
D1
S1A
S1B
D2
S2A
S2B
D3
S3A
S3B
D4
S4A
S4B
MUX
EN# IN
PWM or PORT
PK8/ PWM2A /SSICK0
PK9/ PWM2B /SSIWS0
PK10/ PWM2C /SSIRxD0
PK11/ PWM2D /SSITxD0
PJ8/ PWM2E
PJ9/ PWM2F /TEND1
PJ10/ PWM2G /DREQ1
PJ11/ PWM2H /DACK1
HD151015
Level shifter
A0
A1
A2
A3
A4
A5
VccA
A7
A6
A8
SDHI
8
B0
B1
B2
B3
B4
B5
B7
B6
A8
SSIF
4
PORT interface
4
1A
1B
1C
1D
1E
1F
1G
1H
2A
2B
2C
2D
2E
2F
2G
2H
1A
1B
1C
1D
1E
1F
1G
1H
DIR
3.3 V
G#
VccB
5 V
20-pin
MIL-spec connector
GND
VCC
HD151015
Level shifter
A0
A1
A2
A3
A4
A5
VccA
A7
A6
A8
B0
B1
B2
B3
B4
B5
B7
B6
A8
2A
2B
2C
2D
2E
2F
2G
2H
DIR
3.3 V
G#
VccB
5 V
5 V
Expansion connector
3.3 V
JP3
3.3 V
2
3
1
3.3 V
Character LCD interface
Note: Pin names in red indicate the function used.
Figure 4.10.1 PWM Interface Block Diagram
Table 4.10.1 Jumper Setting (JP3)
Number
1-2 (Low) 2-3 (High)
JP3
Connected to the PWM interface (default) Connected to the SDHI/SSIF/PORT interface