Renesas M3A-HS64, User Manual

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M3A-HS64 Functions
2.3.3 External SDRAM Interface
Rev. 1.00 Apr 30, 2009
2-15
REJ11J0034-0100
2
Table 2.3.5 DIP Switches Setting (SW5-4)
Function
Number
OFF(High) ON (Low)
SW5-4
Connected to the SDRAM (default) Connected to the MTU2 interface
The following figure shows the single read and write timing example of the SDRAM. Table 2.3.6 lists the bus state controller
setting when the SH7264 bus clock works at 72 MHz.
SDRAM SINGLE READ SDRAM SINGLE WRITE
Data Data
tWDH2 tOHZ
tOH
tAC
tLZ
tAD1
tAD1
tAD1
tAD1 tAD1
tAD1
tAD1 tAD1
tAD1
tAD1 tAD1
tAD1
tAD1 tAD1
tAD1
tAD1 tAD1
tDQMD1 tDQMD1 tDQMD1 tDQMD1
tRWD1
tRWD1
tCASD1
tCASD1
tCASD1
tCASD1
tRASD1
tRASD1
tRASD1
tRASD1
tCSD1 tCSD1 tCSD1 tCSD1
tHI
tSI
tRDH2
tRDS2
tHI
tSI
tHI
tSI
tHI
tSI
tHI
tSI
tRP
tDAL
tRC
tRP tRAS
tDPL
tDAL
tDPL tRCD
tRAS tRP
tRC tRC
tRCD
tRP tRAS
tRCD
tRAS
tRC
tRCD
ACT READA ACT WRIT EA ACT
T r T rw T c1 T cw T d1 T de T r T rw T c1 T rw11 T rw12 T r T ap T ap
CKIO
CKE
CS3#
RASL#
CASL#
RD/WR#
DQMUU-LL
A11-A2(A9-A0)
A12(A10/AP)
A15,A14(BA1,0)
D0-31
Figure 2.3.4 SDRAM Single Read/Write Timing Example