M3A-HS64G01 Functions
3.2.4 SH7264 Multiplex Pins Used on the M3A-HS64G01
Rev. 1.00 Apr 30, 2009
3-13
REJ11J0034-0100
3
Table 3.2.19 SH7264 Multiplex Pin Functions (VDC3)
SH7264 Port Control Register
Peripheral
Function
Pin Name
Register Name
MD bit Setting
SH7264
Multiplex Pin Name
VDC3
LCD_EXTCLK
PGCR5
PG20MD[2:0] = B'001
PG20/
LCD_EXTCLK
/MISO1/TxD7
LCD_CLK
PGCR4
PG19MD[2:0] = B'001
PG19/
LCD_CLK
/TIOC2B/MOSI1/RxD7
LCD_DE
PGCR4
PG18MD[2:0] = B'001
PG18/
LCD_DE
/TIOC2A/SSL10/TxD6
LCD_HSYNC
PGCR4
PG17MD[2:0] = B'001
PG17/
LCD_HSYNC
/TIOC1B/RSPCK1/RxD6
LCD_VSYNC
PGCR4
PG16MD[2:0] = B'001
PG16/
LCD_VSYNC
/TIOC1A/TxD3/CTS1#
LCD_DATA15
PGCR3
PG15MD[2:0] = B'001
PG15/
LCD_DATA15
/TIOC0D/RxD3/RTS1#
LCD_DATA14
PGCR3
PG14MD[2:0] = B'001
PG14/
LCD_DATA14
/TIOC0C/SCK1
LCD_DATA13
PGCR3
PG13MD[2:0] = B'001
PG13/
LCD_DATA13
/TIOC0B/TxD1
LCD_DATA12
PGCR3
PG12MD[2:0] = B'001
PG12/
LCD_DATA12
/TIOC0A/RxD1
LCD_DATA11
PGCR2
PG11MD[2:0] = B'001
PG11/
LCD_DATA11
/SSITxD0/IRQ3/TxD5/SIOFTxD
LCD_DATA10
PGCR2
PG10MD[2:0] = B'001
PG10/
LCD_DATA10
/SSIRxD0/IRQ2/RxD5/SIOFRxD
LCD_DATA9
PGCR2
PG9MD[2:0] = B'001
PG9/
LCD_DATA9
/SSIWS0/TxD4/SIOFSYNC
LCD_DATA8
PGCR2
PG8MD[2:0] = B'001
PG8/
LCD_DATA8
/SSISCK0/RxD4/SIOFSCK
LCD_DATA7
PGCR1
PG7MD[1:0] = B'01
PG7/
LCD_DATA7
/SD_CD/PINT7
LCD_DATA6
PGCR1
PG6MD[1:0] = B'01
PG6/
LCD_DATA6
/SD_WP/PINT6
LCD_DATA5
PGCR1
PG5MD[1:0] = B'01
PG5/
LCD_DATA5
/SD_D1/PINT5
LCD_DATA4
PGCR1
PG4MD[1:0] = B'01
PG4/
LCD_DATA4
/SD_D0/PINT4
LCD_DATA3
PGCR0
PG3MD[1:0] = B'01
PG3/
LCD_DATA3
/SD_CLK/PINT3
LCD_DATA2
PGCR0
PG2MD[1:0] = B'01
PG2/
LCD_DATA2
/SD_CMD/PINT2
LCD_DATA1
PGCR0
PG1MD[1:0] = B'01
PG1/
LCD_DATA1
/SD_D3/PINT1
LCD_DATA0
PGCR7
PG0MD[2:0] = B'001
PG0/
LCD_DATA0
/SD_D2/PINT0/WDTOVF#
LCD_M_DISP
PJCR0
PJ2MD[2:0] = B'101
PJ2/CTx1/CTx0&CTx1/CS2#/SCK0/
LCD_M_DISP
Table 3.2.20 SH7264 Multiplex Pin Functions (PORT)
SH7264 Port Control Register
Peripheral
Function
Pin Name
Register Name
MD bit Setting
SH7264
Multiplex Pin Name
PORT
PG24
PGCR6
PG24MD[1:0] = B'00
PG24
/MISO1/TIOC0D
PJ10
PJCR2
PJ10MD[1:0] = B'00
PJ10
/PWM2G/DREQ1
PJ9
PJCR2
PJ9MD[1:0] = B'00
PJ9
/PWM2F/TEND1
PK7
PKCR1
PK7MD[1:0] = B'00
PK7
/PWM1H/SD_CD
PK6
PKCR1
PK6MD[1:0] = B'00
PK6
/PWM1G/SD_WP
PK5
PKCR1
PK5MD[1:0] = B'00
PK5
/PWM1F/SD_D1
PK4
PKCR1
PK4MD[1:0] = B'00
PK4
/PWM1E/SD_D0
PK3
PKCR0
PK3MD[1:0] = B'00
PK3
/PWM1D/SD_CLK
PK2
PKCR0
PK2MD[1:0] = B'00
PK2
/PWM1C/SD_CMD
PK1
PKCR0
PK1MD[1:0] = B'00
PK1
/PWM1B/SD_D3
PK0
PKCR0
PK0MD[1:0] = B'00
PK0
/PWM1A/SD_D2
PC10
PCCR2
PC10MD0 = B'0
PC10
/TIOC2B
PC9
PCCR2
PC9MD0 = B'0
PC9
/TIOC2A
PB22
PBCR5
PB22MD[1:0] = B'00
PB22
/A22/CS4#
Summary of Contents for M3A-HS64
Page 6: ...This page is blank for reasons of layout...
Page 11: ...1 1 Chapter 1Overview Chapter 1 Overview...
Page 39: ...2 1 Chapter 2 M3A HS64 Functions Chapter 2 M3A HS64 Functions...
Page 67: ...3 1 Chapter 3 M3A HS64G01 Functions Chapter 3 M3A HS64G01 Functions...
Page 95: ...4 1 Chapter 4 M3A HS64G02 Functions Chapter 4 M3A HS64G02 Functions...
Page 125: ...5 1 Chapter 5M3A HS64 Operating Specifications Chapter 5 M3A HS64 Operating Specifications...
Page 207: ...A 1 Appendix Schematics...
Page 208: ...A 2 This page intentionally left blank...
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Page 238: ...SH7264 CPU Board M3A HS64 User s Manual REJ11J0034 0100...