Renesas M3A-HS64, User Manual

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M3A-HS64G02 Functions
4.2.4 SH7264 Multiplex Pins Used on the M3A-HS64G02
Rev. 1.00 Apr 30, 2009 4-13
REJ11J0034-0100
4
Table 4.2.19 SH7264 Multiplex Pin Functions (VDC3)
SH7264 Port Control Register Peripheral
Function
Pin Name
Register Name MD bit Setting
SH7264
Multiplex Pin Name
VDC3 DV_CLK PFCR2 PF8MD[1:0] = B'11 PF8/CE2B#/SSIDATA3/ DV_CLK
DV_DATA7 PFCR1 PF7MD[2:0] = B'011 PF7/CE2A#/SSIWS3/ DV_DATA7 /TCLKD
DV_DATA6 PFCR1 PF6MD[2:0] = B'011 PF6/CS6#/CE1B#/SSISCK3/ DV_DATA6 /TCLKB
DV_DATA5 PFCR1 PF5MD[2:0] = B'011 PF5/CS5#/CE1A#/SSIDATA2/ DV_DATA5 /TCLKC/AUDATA3
DV_DATA4 PFCR1 PF4MD[2:0] = B'011 PF4/ICIOWR#/AH#/SSIWS2/ DV_DATA4 /TxD3/AUDATA2
DV_DATA3 PFCR0 PF3MD[2:0] = B'011 PF3/ICIORD#/SSISCK2/ DV_DATA3 /RxD3/AUDATA1
DV_DATA2 PFCR0 PF2MD[2:0] = B'011 PF2/BACK#/SSIDATA1/ DV_DATA2 /TxD2/DACK0/AUDATA0
DV_DATA1 PFCR0 PF1MD[2:0] = B'011 PF1/BREQ#/SSIWS1/ DV_DATA1 /RxD2/DREQ0/AUDSYNC#
DV_DATA0 PFCR0 PF0MD[2:0] = B'011 PF0/WAIT#/SSISCK1/ DV_DATA0 /SCK2/TEND0/AUDCK
DV_HSYNC PECR1 PE5MD[1:0] = B'11 PE5/SDA2/ DV_HSYNC
DV_VSYNC PECR1 PE4MD[1:0] = B'11 PE4/SCL2/ DV_VSYNC
LCD_EXTCLK PGCR5 PG20MD[2:0] = B'001 PG20/ LCD_EXTCLK /MISO1/TxD7
LCD_CLK PGCR4 PG19MD[2:0] = B'001 PG19/ LCD_CLK /TIOC2B/MOSI1/RxD7
LCD_DE PGCR4 PG18MD[2:0] = B'001 PG18/ LCD_DE /TIOC2A/SSL10/TxD6
LCD_HSYNC PGCR4 PG17MD[2:0] = B'001 PG17/ LCD_HSYNC /TIOC1B/RSPCK1/RxD6
LCD_VSYNC PGCR4 PG16MD[2:0] = B'001 PG16/ LCD_VSYNC /TIOC1A/TxD3/CTS1#
LCD_DATA15 PGCR3 PG15MD[2:0] = B'001 PG15/ LCD_DATA15 /TIOC0D/RxD3/RTS1#
LCD_DATA14 PGCR3 PG14MD[2:0] = B'001 PG14/ LCD_DATA14 /TIOC0C/SCK1
LCD_DATA13 PGCR3 PG13MD[2:0] = B'001 PG13/ LCD_DATA13 /TIOC0B/TxD1
LCD_DATA12 PGCR3 PG12MD[2:0] = B'001 PG12/ LCD_DATA12 /TIOC0A/RxD1
LCD_DATA11 PGCR2 PG11MD[2:0] = B'001 PG11/ LCD_DATA11 /SSITxD0/IRQ3/TxD5/SIOFTxD
LCD_DATA10 PGCR2 PG10MD[2:0] = B'001 PG10/ LCD_DATA10 /SSIRxD0/IRQ2/RxD5/SIOFRxD
LCD_DATA9 PGCR2 PG9MD[2:0] = B'001 PG9/ LCD_DATA9 /SSIWS0/TxD4/SIOFSYNC
LCD_DATA8 PGCR2 PG8MD[2:0] = B'001 PG8/ LCD_DATA8 /SSISCK0/RxD4/SIOFSCK
LCD_DATA7 PGCR1 PG7MD[1:0] = B'01 PG7/ LCD_DATA7 /SD_CD/PINT7
LCD_DATA6 PGCR1 PG6MD[1:0] = B'01 PG6/ LCD_DATA6 /SD_WP/PINT6
LCD_DATA5 PGCR1 PG5MD[1:0] = B'01 PG5/ LCD_DATA5 /SD_D1/PINT5
LCD_DATA4 PGCR1 PG4MD[1:0] = B'01 PG4/ LCD_DATA4 /SD_D0/PINT4
LCD_DATA3 PGCR0 PG3MD[1:0] = B'01 PG3/ LCD_DATA3 /SD_CLK/PINT3
LCD_DATA2 PGCR0 PG2MD[1:0] = B'01 PG2/ LCD_DATA2 /SD_CMD/PINT2
LCD_DATA1 PGCR0 PG1MD[1:0] = B'01 PG1/ LCD_DATA1 /SD_D3/PINT1
LCD_DATA0 PGCR7 PG0MD[2:0] = B'001 PG0/ LCD_DATA0 /SD_D2/PINT0/WDTOVF#
LCD_M_DISP PJCR0 PJ2MD[2:0] = B'101 PJ2/CTx1/CTx0&CTx1/CS2#/SCK0/ LCD_M_DISP
Table 4.2.20 SH7264 Multiplex Pin Functions (PWM)
SH7264 Port Control Register Peripheral
Function
Pin Name
Register Name MD bit Setting
SH7264
Multiplex Pin Name
PWM PWM2H PJCR2 PJ11MD[1:0] = B'01 PJ11/ PWM2H /DACK1
PWM2G PJCR2 PJ10MD[1:0] = B'01 PJ10/ PWM2G /DREQ1
PWM2F PJCR2 PJ9MD[1:0] = B'01 PJ9/ PWM2F /TEND1
PWM2E PJCR2 PJ8MD[1:0] = B'01 PJ8/ PWM2E /RTS3#
PWM2D PKCR2 PK11MD[1:0] = B'01 PK11/ PWM2D /SSITxD0
PWM2C PKCR2 PK10MD[1:0] = B'01 PK10/ PWM2C /SSIRxD0
PWM2B PKCR2 PK9MD[1:0] = B'01 PK9/ PWM2B /SSIWS0
PWM2A PKCR2 PK8MD[1:0] = B'01 PK8/ PWM2A /SSISCK0
PWM1H PKCR1 PK7MD[1:0] = B'01 PK7/ PWM1H /SD_CD
PWM1G PKCR1 PK6MD[1:0] = B'01 PK6/ PWM1G /SD_WP
PWM1F PKCR1 PK5MD[1:0] = B'01 PK5/ PWM1F /SD_D1
PWM1E PKCR1 PK4MD[1:0] = B'01 PK4/ PWM1E /SD_D0
PWM1D PKCR0 PK3MD[1:0] = B'01 PK3/ PWM1D /SD_CLK
PWM1C PKCR0 PK2MD[1:0] = B'01 PK2/ PWM1C /SD_CMD
PWM1B PKCR0 PK1MD[1:0] = B'01 PK1/ PWM1B /SD_D3
PWM1A PKCR0 PK0MD[1:0] = B'01 PK0/ PWM1A /SD_D2