Renesas M3A-HS64, User Manual

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M3A-HS64 Functions
2.3.3 External SDRAM Interface
Rev. 1.00 Apr 30, 2009
2-14
REJ11J0034-0100
2
2.3.3 External SDRAM Interface
The M3A-HS64 comes standard with an SDRAM listed in the table below. The SDRAM is controlled by the SH7264 on-chip Bus
State Controller (BSC). The M3A-HS64 allows 16-bit bus access only.
The figure below shows the SDRAM block diagram, and Table 2.3.5 lists the DIP switches setting (SW5-4).
Table 2.3.4 SDRAM Specifications
Item Description
Part number EDS1216AHTA-75E
Configuration 16 MB (Bus size: 16-bit) x 1
Capacity 16 MB
Access time 7.5 ns
CAS latency 2 (When the system clock works at 72 MHz)
Refresh 4096 cycles every 64 ms
Row address A11 to A0
Column address A8 to A0
Number of banks 4 (controlled by BA0, and BA1)
NAND flash memory
EDS1216AHTA-75E
16 MB
(2 M × 16-bit × 4 banks)
SH7264
PD3-PD0/ D3-D0
12
DQ3-DQ0
4
DQ15-DQ4 PD15-PD4/ D15-D4
PB14-PB13/ A14-A13
PB12-PB1/ A12-A1
PC8/ CS3# /TIOC4D/IRQ7
PC5/ RAS# /TIOC4A/IRQ4
PC6/ CAS# /TIOC4B/IRQ5
PC7/ CKE /TIOC4C/IRQ6
DIP
SW5-4
D1
S1A
S1B
D2
S2A
S2B
D3
S3A
S3B
D4
S4A
S4B
MUX
EN# IN
MTU2 output (M3A-HS64G02)
BA1-BA0
A11-A0
RAS#
CAS#
CKE
CS#
CKIO
PC2/ RD/WR#
PC3/WE0#/ DQML
PC4/WE1#/ DQMU /WE#
CLK
WE#
LDQM
UDQM
3.3 V
2
12
4
SDRAM or MTU2
3.3 V
3.3 V
Expansion connector
3.3 V
Note: Pin names in red indicate the function used.
Figure 2.3.3 External SDRAM Block Diagram