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Renesas H8S/2437, Hardware Manual

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Rev.1.00, 09/03, page xix of xxxviii 

 

Section 17   I

2

C Bus Interface 3 (IIC3) ............................................................... 475 

17.1 Features ............................................................................................................................. 475 
17.2 Input/Output 

Pins .............................................................................................................. 478 

17.3 Register 

Descriptions ........................................................................................................ 478 

17.3.1 I

2

C Bus Control Register A (ICCRA) .................................................................. 479 

17.3.2 I

2

C Bus Control Register B (ICCRB)................................................................... 480 

17.3.3 I

2

C Bus Mode Register (ICMR) ........................................................................... 482 

17.3.4 I

2

C Bus Interrupt Enable Register (ICIER) .......................................................... 483 

17.3.5 I

2

C Bus Status Register (ICSR)............................................................................ 485 

17.3.6  Slave Address Register (SAR) ............................................................................. 487 
17.3.7  Slave Address Register A (SARA) ...................................................................... 487 
17.3.8  Slave Address Register B (SARB)....................................................................... 488 
17.3.9  Slave Address Mask Register (SAMR)................................................................ 488 
17.3.10 I

2

C Bus Status Register A (ICSRA) ..................................................................... 489 

17.3.11 I

2

C Bus Transmit Data Register (ICDRT)............................................................ 489 

17.3.12 I

2

C Bus Receive Data Register (ICDRR) ............................................................. 489 

17.3.13 I

2

C Bus Shift Register (ICDRS) ........................................................................... 490 

17.4 Operation........................................................................................................................... 491 

17.4.1 I

2

C Bus Format..................................................................................................... 491 

17.4.2  Master Transmit Operation .................................................................................. 492 
17.4.3  Master Receive Operation.................................................................................... 494 
17.4.4  Slave Transmit Operation .................................................................................... 496 
17.4.5  Slave Receive Operation ...................................................................................... 498 
17.4.6 Noise 

Canceler ..................................................................................................... 500 

17.4.7  Example of Use.................................................................................................... 500 

17.5 Interrupt 

Requests ............................................................................................................. 505 

17.6  Bit Synchronous Circuit.................................................................................................... 506 

Section 18   A/D Converter................................................................................. 507 

18.1 Features ............................................................................................................................. 507 
18.2 Input/Output 

Pins .............................................................................................................. 509 

18.3 Register 

Descriptions ........................................................................................................ 510 

18.3.1  A/D Data Registers A to H (ADDRA to ADDRH).............................................. 510 
18.3.2  A/D Control/Status Register (ADCSR) ............................................................... 511 
18.3.3  A/D Control Register (ADCR) ............................................................................ 513 

18.4 Operation........................................................................................................................... 514 

18.4.1 Single 

Mode ......................................................................................................... 514 

18.4.2 Scan 

Mode ........................................................................................................... 514 

18.4.3  Input Sampling and A/D Conversion Time.......................................................... 515 
18.4.4  External Trigger Input Timing ............................................................................. 516 

18.5 Interrupt 

Source................................................................................................................. 517 

18.6  A/D Conversion Accuracy Definitions ............................................................................. 518 
18.7 Usage 

Notes ...................................................................................................................... 520 

Summary of Contents for H8S/2437

Page 1: ...2003 9 19 16 H8S 2437 Group Hardware Manual Renesas 16 Bit Single Chip Microcomputer H8S Family H8S 2600 Series H8S 2437 HD64F2437 Rev 1 00 ...

Page 2: ...Rev 1 00 09 03 page ii of xxxviii ...

Page 3: ...in The information described here may contain technical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors Please also pay attention to information published by Renesas Technology Corp by various means including the Renesas Technology Corp Semiconductor home page http www renesas com...

Page 4: ...alization Note When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin During the period where the states are undefined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of p...

Page 5: ... items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in relation to the descriptions given and usage notes are given as required as the final part of each section 7 List of Registers 8 Electrical Characteristics 9 Appendix 10 Main Revisions and Addition...

Page 6: ...I O ports as on chip peripheral modules required for system configuration A flash memory F ZTAT TM version is available for this LSI s 256 kbyte ROM The CPU and the flash memory are connected to a 16 bit bus enabling byte data and word data to be accessed in a single state This improves the instruction fetch and process speeds Note F ZTAT TM is a trademark of Renesas Technology Corp Target Users T...

Page 7: ...ft and the LSB is on the right Number notation Binary is B xxxx hexadecimal is H xxxx decimal is xxxx Signal notation An overbar is added to a low active signal xxxx Related Manuals The latest versions of all related manuals are available from our web site Please ensure you have the latest versions of all documents you require http www renesas com eng H8S 2437 Group manuals Document Title Document...

Page 8: ...Rev 1 00 09 03 page viii of xxxviii ...

Page 9: ... 3 Extended Register EXR 25 2 4 4 Condition Code Register CCR 26 2 4 5 Multiply Accumulate Register MAC 27 2 4 6 Initial Values of CPU Internal Registers 27 2 5 Data Formats 28 2 5 1 General Register Data Formats 28 2 5 2 Memory Data Formats 30 2 6 Instruction Set 31 2 6 1 Table of Instructions Classified by Function 32 2 6 2 Basic Instruction Formats 41 2 7 Addressing Modes and Effective Address ...

Page 10: ...tor Table 58 4 3 Reset 59 4 3 1 Reset exception handling 59 4 3 2 Interrupts after Reset 60 4 3 3 On Chip Peripheral Functions after Reset Release 60 4 4 Traces 61 4 5 Interrupts 61 4 6 Trap Instruction 62 4 7 Stack Status after Exception Handling 63 4 8 Usage Note 64 Section 5 Interrupt Controller 65 5 1 Features 65 5 2 Input Output Pins 67 5 3 Register Descriptions 67 5 3 1 Interrupt Control Reg...

Page 11: ... Register Descriptions 94 6 3 1 Bus Control Register BCR 94 6 3 2 Area Control Register BCRA 95 6 4 Bus Control 97 6 4 1 Bus Specifications 97 6 4 2 External Address Area 100 6 4 3 Chip Select Signals 100 6 4 4 Address Strobe Hold Signal 101 6 4 5 Address Output 101 6 5 Bus Interface 102 6 5 1 Data Size and Data Alignment 102 6 5 2 Valid Strobes 104 6 5 3 Basic Operation Timing in Normal Extended ...

Page 12: ...2 7 5 2 Port 4 Data Register P4DR 163 7 5 3 Port 4 Register PORT4 163 7 5 4 Pin Functions 164 7 6 Port 5 168 7 6 1 Port 5 Data Direction Register P5DDR 168 7 6 2 Port 5 Data Register P5DR 169 7 6 3 Port 5 Register PORT5 169 7 6 4 Pin Functions 170 7 7 Port 6 173 7 7 1 Port 6 Data Direction Register P6DDR 173 7 7 2 Port 6 Data Register P6DR 174 7 7 3 Port 6 Register PORT6 174 7 7 4 Port 6 Pull Up M...

Page 13: ...in Functions 211 7 14 Change of Peripheral Function Pins 214 7 14 1 Port Control Register 0 PTCNT0 214 7 14 2 Port Control Register 1 PTCNT1 215 7 14 3 Port Control Register 2 PTCNT2 216 Section 8 8 Bit PWM Timer PWM 217 8 1 Features 217 8 2 Input Output Pin 218 8 3 Register Descriptions 218 8 3 1 PWM Register Select PWSL 219 8 3 2 PWM Data Registers 7 to 0 PWDR7 to PWDR0 220 8 3 3 PWM Data Polari...

Page 14: ...ion Timing 252 10 5 1 FRC Increment Timing 252 10 5 2 Output Compare Output Timing 253 10 5 3 FRC Clear Timing 253 10 5 4 Input Capture Input Timing 254 10 5 5 Buffered Input Capture Input Timing 255 10 5 6 Timing of Input Capture Flag Setting 256 10 5 7 Timing of Output Compare Flag Setting 257 10 5 8 Timing of Overflow Flag Setting 257 10 5 9 Automatic Addition Timing 258 10 5 10 Mask Signal Gen...

Page 15: ... Mode 288 11 7 TMRY and TMRX Cascaded Connection 288 11 7 1 16 Bit Count Mode 288 11 7 2 Compare Match Count Mode 289 11 7 3 Input Capture Operation 289 11 8 Interrupt Sources 291 11 9 Usage Notes 292 11 9 1 Conflict between TCNT Write and Clear 292 11 9 2 Conflict between TCNT Write and Increment 293 11 9 3 Conflict between TCOR Write and Compare Match 294 11 9 4 Conflict between Compare Matches ...

Page 16: ... Timer Connection 365 13 1 Features 365 13 2 Input Output Pins 368 13 3 Register Descriptions 369 13 3 1 Timer Connection Register I TCONRI 369 13 3 2 Timer Connection Register O TCONRO 372 13 3 3 Timer Connection Register S TCONRS 375 13 3 4 Edge Sense Register SEDGR 377 13 3 5 Timer Extended Control Register TECR 379 13 4 Operation 380 13 4 1 PWM Decoding PDC Signal Generation 380 13 4 2 Clamp W...

Page 17: ... ENDF 409 14 5 7 Set Timing for Overflow Flag OVF 410 14 6 Interrupt Sources 410 14 7 Usage Notes 411 14 7 1 Conflict between TWCNT Write and Increment 411 14 7 2 Write to START Bit during Free Running Counter Operation 411 14 7 3 Switching of Internal Clock and TWCNT Operation 412 14 7 4 Switching of External Event Signal and Operation of Edge Detection Circuit 414 Section 15 Watchdog Timer WDT 4...

Page 18: ...sion Asynchronous Mode 447 16 4 6 Serial Data Reception Asynchronous Mode 449 16 5 Multiprocessor Communication Function 453 16 5 1 Multiprocessor Serial Data Transmission 455 16 5 2 Multiprocessor Serial Data Reception 456 16 6 Operation in Clocked Synchronous Mode 459 16 6 1 Clock 459 16 6 2 SCI Initialization Clocked Synchronous Mode 459 16 6 3 Serial Data Transmission Clocked Synchronous Mode ...

Page 19: ...eceive Data Register ICDRR 489 17 3 13 I 2 C Bus Shift Register ICDRS 490 17 4 Operation 491 17 4 1 I 2 C Bus Format 491 17 4 2 Master Transmit Operation 492 17 4 3 Master Receive Operation 494 17 4 4 Slave Transmit Operation 496 17 4 5 Slave Receive Operation 498 17 4 6 Noise Canceler 500 17 4 7 Example of Use 500 17 5 Interrupt Requests 505 17 6 Bit Synchronous Circuit 506 Section 18 A D Convert...

Page 20: ...ing Erasing Interface Registers 534 20 3 2 Programming Erasing Interface Parameters 541 20 4 On Board Programming Mode 551 20 4 1 Boot Mode 551 20 4 2 User Program Mode 555 20 4 3 User Boot Mode 565 20 4 4 Storable Area for Procedure Program and Program Data 568 20 5 Protection 578 20 5 1 Hardware Protection 578 20 5 2 Software Protection 579 20 5 3 Error Protection 579 20 6 Switching between User...

Page 21: ...tput Control 631 22 4 Usage Notes 633 22 4 1 I O Port State 633 22 4 2 Current Consumption during Oscillation Stabilization Standby Period 633 22 4 3 On Chip Peripheral Module Interrupts 633 22 4 4 Writing to MSTPCR EXMSTPCR 633 22 4 5 Notes on Clock Division Mode 633 Section 23 List of Registers 635 23 1 Register Addresses Address Order 636 23 2 Register Bits 647 23 3 Register States in Each Oper...

Page 22: ...Rev 1 00 09 03 page xxii of xxxviii Appendix 695 A I O Port States in Each Pin State 695 B Product Lineup 697 C Package Dimensions 698 Index 699 ...

Page 23: ... 46 Figure 2 13 State Transitions 50 Section 3 MCU Operating Modes Figure 3 1 Memory Map 56 Section 4 Exception Handling Figure 4 1 Reset Sequence 60 Figure 4 2 Stack Status after Exception Handling 63 Figure 4 3 Operation when SP Value is Odd 64 Section 5 Interrupt Controller Figure 5 1 Block Diagram of Interrupt Controller 66 Figure 5 2 Block Diagram of Interrupts IRQ7 to IRQ0 76 Figure 5 3 Flow...

Page 24: ...6 19 Bus Timing for 16 Bit 2 State Data Access Space 4 Odd Byte Access without Address Wait 119 Figure 6 20 Bus Timing for 16 Bit 2 State Data Access Space 5 Word Access with Address Wait 120 Figure 6 21 Bus Timing for 16 Bit 2 State Data Access Space 6 Word Access without Address Wait 121 Figure 6 22 Bus Timing for 16 Bit 3 State Data Access Space 1 Even Byte Access with Address Wait 122 Figure 6...

Page 25: ...FRC Write Clear Conflict 261 Figure 10 18 FRC Write Increment Conflict 262 Figure 10 19 Conflict between OCR Write and Compare Match When Automatic Addition Function is not Used 263 Figure 10 20 Conflict between OCRAR OCRAF Write and Compare Match When Automatic Addition Function is Used 264 Section 11 8 Bit Timer TMR Figure 11 1 Block Diagram of 8 Bit Timer TMR0 and TMR1 268 Figure 11 2 Block Dia...

Page 26: ...4 Figure 12 18 Example of Buffer Operation Setting Procedure 335 Figure 12 19 Example of Buffer Operation 1 335 Figure 12 20 Example of Buffer Operation 2 336 Figure 12 21 Cascaded Operation Setting Procedure 337 Figure 12 22 Example of Cascaded Operation 1 338 Figure 12 23 Example of Cascaded Operation 2 338 Figure 12 24 Example of PWM Mode Setting Procedure 340 Figure 12 25 Example of PWM Mode O...

Page 27: ...gram for Clamp Waveform Generation 383 Figure 13 6 Timing Chart for Clamp Waveform Generation CL1 and CL2 Signals 383 Figure 13 7 Timing Chart for Clamp Waveform Generation CL3 Signal 384 Figure 13 8 Block Diagram for Measurement of 8 Bit Timer Divided Waveform Period 385 Figure 13 9 Timing Chart for Measurement of IVI Signal and IHI Signal Divided Waveform Periods 386 Figure 13 10 Block Diagram f...

Page 28: ... Transmission Flowchart 448 Figure 16 8 Example of SCI Operation in Reception Example with 8 Bit Data Parity One Stop Bit 449 Figure 16 9 Sample Serial Reception Flowchart 1 451 Figure 16 9 Sample Serial Reception Flowchart 2 452 Figure 16 10 Example of Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A 454 Figure 16 11 Sample Multiprocessor Serial Transmiss...

Page 29: ...g in Slave Receive Mode 2 499 Figure 17 13 Block Diagram of Noise Canceler 500 Figure 17 14 Sample Flowchart for Master Transmit Mode 501 Figure 17 15 Sample Flowchart for Master Receive Mode 502 Figure 17 16 Sample Flowchart for Slave Transmit Mode 503 Figure 17 17 Sample Flowchart for Slave Receive Mode 504 Figure 17 18 Timing of Bit Synchronous Circuit 506 Section 18 A D Converter Figure 18 1 B...

Page 30: ...ypical Connection to Crystal Resonator 614 Figure 21 3 Equivalent Circuit of Crystal Resonator 614 Figure 21 4 Example of External Clock Input 615 Figure 21 5 External Clock Input Timing 616 Figure 21 6 Timing of Output Stabilization Delay Time for External Clock 616 Figure 21 7 Note on Board Design of Oscillation Circuit Section 617 Section 22 Power Down Modes Figure 22 1 Mode Transitions 621 Fig...

Page 31: ...ming 687 Figure 24 19 8 Bit Timer Output Timing 687 Figure 24 20 8 Bit Timer Clock Input Timing 687 Figure 24 21 8 Bit Timer Reset Input Timing 688 Figure 24 22 PWM PWMX Output Timing 688 Figure 24 23 SCK Clock Input Timing 688 Figure 24 24 SCI Input Output Timing Clock Synchronous Mode 688 Figure 24 25 A D Converter External Trigger Input Timing 689 Figure 24 26 Input Output Timing of I2 C Bus In...

Page 32: ...Rev 1 00 09 03 page xxxii of xxxviii ...

Page 33: ...tive Address Calculation 1 47 Table 2 13 Effective Address Calculation 2 48 Section 3 MCU Operating Modes Table 3 1 MCU Operating Mode Selection 51 Table 3 2 Pin Functions in Each Operating Mode 55 Section 4 Exception Handling Table 4 1 Exception Types and Priority 57 Table 4 2 Exception Handling Vector Table 58 Table 4 3 Status of CCR and EXR after Trace Exception Handling 61 Table 4 4 Status of ...

Page 34: ...ion 220 Table 8 3 Resolution PWM Conversion Period and Carrier Frequency when φ 20 MHz 220 Table 8 4 Duty Cycle of Basic Pulse 223 Table 8 5 Position of Pulses Added to Basic Pulses 224 Section 9 14 Bit PWM Timer PWMX Table 9 1 Pin Configuration 226 Table 9 2 Clock Selection of PWMX 231 Table 9 3 Access Method for Reading Writing 16 Bit Registers 232 Table 9 4 Settings and Operation Examples when ...

Page 35: ...t Pins 339 Table 12 20 Clock Input Pins for Phase Counting Mode 343 Table 12 21 Up Down Count Conditions in Phase Counting Mode 1 344 Table 12 22 Up Down Count Conditions in Phase Counting Mode 2 345 Table 12 23 Up Down Count Conditions in Phase Counting Mode 3 346 Table 12 24 Up Down Count Conditions in Phase Counting Mode 4 347 Table 12 25 TPU Interrupts 348 Section 13 Timer Connection Table 13 ...

Page 36: ...nal Clock Input Asynchronous Mode 440 Table 16 6 BRR Settings for Various Bit Rates Clocked Synchronous Mode 441 Table 16 7 Maximum Bit Rate with External Clock Input Clocked Synchronous Mode 441 Table 16 8 Serial Transfer Formats Asynchronous Mode 443 Table 16 9 SSR Status Flags and Receive Data Handling 450 Table 16 10 SCI Interrupt Sources 468 Section 17 I2 C Bus Interface 3 IIC3 Table 17 1 Pin...

Page 37: ...ameters 614 Table 21 3 External Clock Input Conditions 615 Table 21 4 Output Stabilization Delay Time for External Clock 616 Section 22 Power Down Modes Table 22 1 Operating Modes and Internal States of LSI 620 Table 22 2 Oscillation Stabilization Time Settings 628 Table 22 3 φ Pin State in Each Processing State 632 Section 24 Electrical Characteristics Table 24 1 Absolute Maximum Ratings 669 Tabl...

Page 38: ...Rev 1 00 09 03 page xxxviii of xxxviii ...

Page 39: ...PWM 14 bit PWM timer PWMX 16 bit free running timer FRT 8 bit timer TMR 16 bit timer pulse unit TPU Watchdog timer WDT Timer connection Duty measurement circuit Asynchronous or clocked synchronous serial communication interface SCI I 2 C bus interface 3 IIC3 10 bit A D converter On chip memory ROM Type Model ROM RAM Remarks Flash memory version HD64F2437 256 kbytes 16 kbytes General I O ports I O ...

Page 40: ... SCL0 TxD3 P81 SDA0 RxD3 P82 SCL1 TxD4 P83 SDA1 RxD4 P84 PWX0 P85 PWX1 P86 ExTIOCA0 P87 ExTIOCB0 Port 8 P90 ExTIOCB1 ExTCLKC P91 ExTIOCA2 P92 ExTIOCB2 ExTCLKD P93 P94 P95 P96 P97 ExTIOCD0 ExTCLKB Port 9 P10 PW0 A0 AD0 P11 PW1 A1 AD1 P12 PW2 A2 AD2 P13 PW3 A3 AD3 P14 PW4 A4 AD4 P15 PW5 A5 AD5 P16 PW6 A6 AD6 P17 PW7 A7 AD7 Port 1 P20 TIOCA0 A8 AD8 P21 TIOCB0 A9 AD9 P22 TIOCC0 TCLKA A10 AD10 P23 TIOC...

Page 41: ...0 VSYNCO P47 TMIY_0 ExPW3 P46 TMIX_0 ExPW2 P45 TMI0_0 ExPW1 P44 TMIY_1 ExPW0 AVref AVCC P07 AN15 P06 AN14 P05 AN13 P04 AN12 P03 AN11 P02 AN10 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P01 AN9 P00 AN8 P77 AN7 P76 AN6 P75 AN5 P74 AN4 P73 AN3 P72 AN2 P71 AN1 P70 AN0 AVSS VSS P43 TMIX_1 P42 TMI0_1 P41 FTIC_1 P40 FTIB_1 P57 TMO1...

Page 42: ...RxD2 NC 6 D6 P66 TxD2 P66 TxD2 NC 7 D5 P65 SCK2 P65 SCK2 NC 8 D4 P64 FTCI_1 P64 FTCI_1 NC 9 D3 P63 TMOY_1 P63 TMOY_1 NC 10 D2 P62 TMOX_1 P62 TMOX_1 NC 11 D1 P61 FTOB_1 P61 FTOB_1 NC 12 D0 P60 FTOA_1 P60 FTOA_1 NC 13 VSS VSS VSS 14 P90 LWR ExTIOCB1 ExTCLKC P90 ExTIOCB1 ExTCLKC A16 15 P91 CS2 ExTIOCA2 P91 ExTIOCA2 A17 16 VCC VCC VCC 17 P92 CS1 ExTIOCB2 ExTCLKD P92 ExTIOCB2 ExTCLKD A18 18 RD P93 NC 1...

Page 43: ...NC 39 ETRST ETRST RES 40 ETDO PC7 ETDO PC7 NC 41 P50 SCK0 P50 SCK0 NC 42 P51 TxD0 P51 TxD0 NC 43 P52 RxD0 P52 RxD0 NC 44 P53 SCK1 P53 SCK1 NC 45 P54 TxD1 P54 TxD1 NC 46 P55 RxD1 P55 RxD1 NC 47 P56 TMO0_1 ExPW4 P56 TMO0_1 ExPW4 NC 48 P57 TMO1_1 ExPW5 P57 TMO1_1 ExPW5 NC 49 P40 IRQ0 FTIB_1 P40 IRQ0 FTIB_1 VCC 50 P41 IRQ1 FTIC_1 P41 IRQ1 FTIC_1 VCC 51 P42 IRQ2 TMI0_1 P42 IRQ2 TMI0_1 VCC 52 P43 IRQ3 T...

Page 44: ...AVref VCC 73 P44 IRQ4 TMIY_1 ExPW0 P44 IRQ4 TMIY_1 ExPW0 VCC 74 P45 IRQ5 TMI0_0 ExPW1 P45 IRQ5 TMI0_0 ExPW1 VCC 75 P46 IRQ6 TMIX_0 ExPW2 P46 IRQ6 TMIX_0 ExPW2 VCC 76 P47 IRQ7 TMIY_0 ExPW3 P47 IRQ7 TMIY_0 ExPW3 VCC 77 PB0 FTOA_0 VSYNCO PB0 FTOA_0 VSYNCO NC 78 PB1 TMO1_0 HSYNCO PB1 TMO1_0 HSYNCO NC 79 PB2 FTID_1 CSYNCI_1 PB2 FTID_1 CSYNCI_1 NC 80 PB3 FTIA_1 VSYNCI_1 PB3 FTIA_1 VSYNCI_1 NC 81 PB4 TMI...

Page 45: ... SCK4 NC 98 PA0 TMOX_0 ExPW6 SCK3 PA0 TMOX_0 ExPW6 SCK3 VCC 99 P83 SDA1 RxD4 P83 SDA1 RxD4 NC 100 P82 SCL1 TxD4 P82 SCL1 TxD4 NC 101 P81 SDA0 RxD3 P81 SDA0 RxD3 NC 102 P80 SCL0 TxD3 P80 SCL0 TxD3 NC 103 PC0 SCL2 PC0 SCL2 NC 104 PC1 SDA2 PC1 SDA2 NC 105 PC2 SCL3 PC2 SCL3 NC 106 PC3 SDA3 PC3 SDA3 NC 107 P27 A15 AD15 P27 TIOCB2 TCLKD A15 108 P26 A14 AD14 P26 TIOCA2 A14 109 P25 A13 AD13 P25 TIOCB1 TCL...

Page 46: ...al Multiplex EXPE 0 Flash Memory Programmer Mode 120 P14 A4 AD4 P14 PW4 A4 121 P13 A3 AD3 P13 PW3 A3 122 P12 A2 AD2 P12 PW2 A2 123 P11 A1 AD1 P11 PW1 A1 124 P10 A0 AD0 P10 PW0 A0 125 D15 P37 P37 D7 126 D14 P36 P36 D6 127 D13 P35 P35 D5 128 D12 P34 P34 D4 Note Not supported by the on chip emulator ...

Page 47: ...plied from the EXTAL pin For an example of crystal resonator connection see section 21 Clock Pulse Generator φ 21 Output Supplies the system clock to external devices Operating mode control MD2 MD1 MD0 25 24 23 Input These pins set the operating mode Inputs at these pins should not be changed during operation System control RES 28 Input Reset pin When this pin is low the chip is reset STBY 37 Inpu...

Page 48: ... to 49 Interrupts ExIRQ7 to ExIRQ0 70 to 67 1 to 4 Input These pins request a maskable interrupt Selectable to which pin of IRQn or ExIRQn to input IRQ7 to IRQ0 interrupts ETRST 2 39 Input ETMS 35 Input ETDO 40 Output ETDI 38 Input On chip emulator ETCK 36 Input Interface pins for the on chip emulator Reset by holding the ETRST pin to low when activating the H UDI At this time the ETRST pin should...

Page 49: ...ut compare output pins 16 bit free running timer FRT FTIA_0 to FTID_0 FTIA_1 to FTID_1 84 93 94 82 80 49 50 79 Input Input capture input pins TMO0_0 TMO0_1 TMO1_0 TMO1_1 TMOX_0 TMOX_1 TMOY_0 TMOY_1 96 47 78 48 98 10 97 9 Output Waveform output pins with output compare function 8 bit timer TMR0 TMR1 TMRX TMRY TMI0_0 TMI0_1 TMI1_0 TMI1_1 TMIX_0 TMIX_1 TMIY_0 TMIY_1 74 51 85 81 75 52 76 73 Input Exte...

Page 50: ... for TGR1A to TGR1D Selectable to from which pin of TIOCn1 or ExTIOCn1 to input output input capture output compare and PWM TIOCA2 TIOCB2 ExTIOCA2 ExTIOCB2 108 107 15 17 I O Input capture input output compare output PWM output pins for TGR2A to TGR2D Selectable to from which pin of TIOCn2 or ExTIOCn2 to input output input capture output compare and PWM Timer connection VSYNCI_0 VSYNCI_1 HSYNCI_0 H...

Page 51: ...ter When the A D converter is not used this pin should be connected to the system power supply 3 3 V AVSS 54 Input Ground pin for the A D converter This pin should be connected to the system power supply 0 V I O ports P07 to P00 70 to 63 Input Eight input pins P17 to P10 116 117 119 to 124 I O Eight input output pins P27 to P20 107 to 114 I O Eight input output pins P37 to P30 125 to 4 I O Eight i...

Page 52: ... from this LSI to prevent the ETRST pin of the board tester from affecting the operation of this LSI Apart the power on reset circuit from this LSI to prevent the system reset of this LSI from affecting the ETRST pin of the board tester Figure1 3 shows an example of design in which signals for reset do not affect each other Power on reset circuit Board edge pin System reset This LSI Figure 1 3 Sam...

Page 53: ...en 8 bit registers or eight 32 bit registers Sixty nine basic instructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Multiply accumulate instruction Eight addressing modes Register direct Rn Register indirect ERn Register indirect with displacement d 16 ERn or d 32 ERn Register indirect with post increment or pre decrement...

Page 54: ...re as shown below Register configuration The MAC register is supported only by the H8S 2600 CPU Basic instructions The four instructions MAC CLRMAC LDMAC and STMAC are supported only by the H8S 2600 CPU The number of execution states of the MULXU and MULXS instructions Execution States Instruction Mnemonic H8S 2600 H8S 2000 MULXU MULXU B Rs Rd 3 12 MULXU W Rs ERd 4 20 MULXS MULXS B Rs Rd 4 13 MULX...

Page 55: ...added A multiply accumulate instruction has been added Two bit shift and rotate instructions have been added Instructions for saving and restoring multiple registers have been added A test and set instruction has been added Higher speed Basic instructions execute twice as fast Note Normal mode is not available in this LSI 2 1 3 Differences from H8 300H CPU In comparison to the H8 300H CPU the H8S ...

Page 56: ...lower 16 bits of effective addresses EA are valid Exception handling Vector Table and Memory Indirect Branch Addresses In normal mode the top area starting at H 0000 is allocated to the exception handling vector table One branch address is stored per 16 bits The exception handling vector table in normal mode is shown in figure 2 1 For details of the exception handling vector table see section 4 Ex...

Page 57: ...xception handling vector 1 Exception handling vector 2 Exception handling vector table Figure 2 1 Exception Handling Vector Table Normal Mode PC 16 bits EXR 1 Reserved 1 3 CCR CCR 3 PC 16 bits SP SP SP 2 1 When EXR is not used it is not stored on the stack 2 SP when EXR is not used 3 lgnored when returning Notes b Exception Handling a Subroutine Branch Figure 2 2 Stack Structure in Normal Mode ...

Page 58: ...n units of 32 bits In each 32 bits the upper 8 bits are ignored and a branch address is stored in the lower 24 bits figure 2 3 For details of the exception handling vector table see section 4 Exception Handling H 00000000 H 00000003 H 00000004 H 0000000B H 0000000C H 00000010 H 00000008 H 00000007 Reserved Reserved Reserved Reset exception handling vector Reserved for system use Reserved for syste...

Page 59: ... when the program counter PC is pushed onto the stack in a subroutine call and the PC condition code register CCR and extended control register EXR are pushed onto the stack in exception handling they are stored as shown in figure 2 4 EXR is not pushed onto the stack in interrupt control mode 0 For details see section 4 Exception Handling PC 24 bits EXR 1 Reserved 1 3 CCR PC 24 bits SP SP SP 2 Res...

Page 60: ... Gbyte address space in advanced mode The usable modes and address spaces differ depending on the product For details on each product refer to section 3 MCU Operating Modes H 0000 H FFFF Note Normal mode cannot be used in this LSI H 00000000 H FFFFFFFF H 00FFFFFF 64 kbyte 16 Mbyte Cannnot be used in this LSI Program area Data area b Advanced Mode a Normal Mode Figure 2 5 Memory Map Note Normal mod...

Page 61: ...1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H R0L R1L R2L R3L R4L R5L R6L R7L SP PC EXR T I2 to I0 CCR I UI Stack pointer Program counter Extended register Trace bit Interrupt mask bits Condition code register Interrupt mask bit User bit or interrupt mask bit Half carry flag User bit Negative flag Zero flag Overflow flag Carry flag Multiply accumulate register ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7...

Page 62: ... are functionally equivalent providing a maximum sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum sixteen 8 bit registers The usage of each register can be selected independently Gen...

Page 63: ...ulated by the LDC STC ANDC ORC and XORC instructions When these instructions except for the STC instruction is executed all interrupts including NMI will be masked for three states after execution is completed Bit Bit Name Initial Value R W Description 7 T 0 R W Trace Bit When this bit is set to 1 a trace exception handling is started each time an instruction is executed When this bit is cleared t...

Page 64: ...t Can be written and read by software using the LDC STC ANDC ORC and XORC instructions This bit cannot be used as an interrupt mask bit in this LSI 5 H Undefined R W Half Carry Flag When the ADD B ADDX B SUB B SUBX B CMP B or NEG B instruction is executed this flag is set to 1 if there is a carry or borrow at bit 3 and cleared to 0 otherwise When the ADD W SUB W CMP W or NEG W instruction is execu...

Page 65: ...tions 2 4 5 Multiply Accumulate Register MAC This 64 bit register stores the results of multiply accumulate operations It consists of two 32 bit registers denoted MACH and MACL The lower 10 bits of MACH are valid the upper bits are a sign extension 2 4 6 Initial Values of CPU Internal Registers When the reset exception handling loads the start address from the vector address PC is initialized the ...

Page 66: ... treat byte data as two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 9 shows the data formats in general registers 7 0 7 0 MSB LSB MSB LSB 7 0 4 3 Don t care Don t care Don t care 7 0 4 3 7 0 Don t care 6 5 4 3 2 7 1 0 7 0 Don t care 6 5 4 3 2 7 1 0 Don t care RnH RnL RnH RnL RnH RnL Data Type Register Number Data Format Byte data Byte data 4 bit BCD data 4 bit BCD data 1 ...

Page 67: ...n RnH RnL MSB LSB General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Data Type Data Format Register Number Word data Word data Rn En Longword data Legend ERn Figure 2 9 General Register Data Formats 2 ...

Page 68: ...occurs but the least significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches When ER7 is used as an address register to access the stack the operand size should be word size or longword size 7 0 7 6 5 4 3 2 1 0 MSB LSB MSB MSB LSB LSB Data Type Address 1 bit data Byte data Word data Address L Address L Address 2M Addres...

Page 69: ...ND OR XOR NOT B W L 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B W L 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14 Branch Bcc 2 JMP BSR JSR RTS 5 System control TRAPA RTE SLEEP LDC STC ANDC ORC XORC NOP 9 Block data transfer EEPMOV 1 Total 69 Notes B byte size W word size L longword size 1 POP W Rn and PUSH W Rn are identical to MOV W SP Rn and...

Page 70: ...ply accumulate register 32 bit register EAd Destination operand EAs Source operand EXR Extended register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT log...

Page 71: ...not be used in this LSI POP W L SP Rn Pops a general register from the stack POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a general register onto the stack PUSH W Rn is identical to MOV W Rn SP PUSH L ERn is identical to MOV L ERn SP LDM L SP Rn register list Pops two or more general registers from the stack STM L Rn register list SP Pushes two ...

Page 72: ... can be incremented or decremented by 1 only ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4 bit BCD data MULXU B W Rd Rs Rd Performs unsigned multiplication on data in two general registers Either ...

Page 73: ... longword size by padding with zeros on the left EXTS W L Rd sign extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register to longword size by extending the sign bit TAS 2 B ERd 0 1 bit 7 of ERd Tests memory contents and sets the most significant bit bit 7 to 1 MAC EAs EAd MAC MAC Performs signed multiplication on memory contents and adds th...

Page 74: ...d Takes the one s complement logical complement of general register contents Note Size refers to the operand size B Byte W Word L Longword Table 2 6 Shift Instructions Instruction Size Function SHAL SHAR B W L Rd shift Rd Performs an arithmetic shift on general register contents 1 bit or 2 bit shift is possible SHLL SHLR B W L Rd shift Rd Performs a logical shift on general register contents 1 bit...

Page 75: ...l register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND BIAND B B C bit No of EAd C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag C bit No of EAd C ANDs the carry flag with the inverse of a specified bit in ...

Page 76: ...ecified by 3 bit immediate data BLD BILD B B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag bit No of EAd C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag The bit number is specified by 3 bit immediate data BST BIST B B C bit No of EAd Transfers the carry flag value to a specified bit in a gene...

Page 77: ... High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified addres...

Page 78: ...n them and memory The upper 8 bits are valid STC B W CCR EAd EXR EAd Transfers CCR or EXR contents to a general register or memory Although CCR and EXR are 8 bit registers word size transfers are performed between them and memory The upper 8 bits are valid ANDC B CCR IMM CCR EXR IMM EXR Logically ANDs the CCR or EXR contents with immediate data ORC B CCR IMM CCR EXR IMM EXR Logically ORs the CCR o...

Page 79: ...from the address set in ER5 transfers data for the number of bytes set in R4L or R4 to the address location set in ER6 Execution of the next instruction begins as soon as the transfer is completed 2 6 2 Basic Instruction Formats The H8S 2600 Series instructions consist of 2 byte 1 word units An instruction consists of an operation field op a register field r an effective address extension EA and a...

Page 80: ...4 bits Some instructions have two register fields Some have no register field Effective Address Extension 8 16 or 32 bits specifying immediate data an absolute address or a displacement Condition Field Specifies the branching condition of Bcc instructions op op rn rm NOP RTS etc ADD B Rn Rm etc MOV B d 16 Rn Rm etc rn rm op EA disp op cc EA disp BRA d 16 etc 1 Operation field only 2 Operation fiel...

Page 81: ...ct with pre decrement ERn ERn 5 Absolute address aa 8 aa 16 aa 24 aa 32 6 Immediate xx 8 xx 16 xx 32 7 Program counter relative d 8 PC d 16 PC 8 Memory indirect aa 8 2 7 1 Register Direct Rn The register field of the instruction code specifies an 8 16 or 32 bit general register containing the operand R0H to R7H and R0L to R7L can be specified as 8 bit registers R0 to R7 and E0 to E7 can be specifi...

Page 82: ...ransfer instruction For word or longword transfer instruction the register value should be even 2 7 5 Absolute Address aa 8 aa 16 aa 24 or aa 32 The instruction code contains the absolute address of a memory operand The absolute address may be 8 bits long aa 8 16 bits long aa 16 24 bits long aa 24 or 32 bits long aa 32 Table 2 12 indicates the accessible absolute address ranges To access data the ...

Page 83: ...6 to 32768 bytes 16383 to 16384 words from the branch instruction The resulting value should be an even number 2 7 8 Memory Indirect aa 8 This mode can be used by the JMP and JSR instructions The instruction code contains an 8 bit absolute address specifying a memory operand This memory operand contains a branch address The upper bits of the absolute address are all assumed to be 0 so the address ...

Page 84: ...vailable in this LSI Figure 2 12 Branch Address Specification in Memory Indirect Mode 2 7 9 Effective Address Calculation Table 2 13 indicates how effective addresses EA are calculated in each addressing mode In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16 bit address Note Normal mode is not available in this LSI ...

Page 85: ...Don t care 24 24 24 24 Addressing Mode and Instruction Format Effective Address Calculation Effective Address EA Register direct Rn General register contents General register contents General register contents General register contents Sign extension Register indirect ERn Register indirect with post increment or pre decrement Register indirect with post increment ERn Register indirect with pre dec...

Page 86: ...ion Format Absolute address Immediate Effective Address Calculation Effective Address EA Sign extension Operand is immediate data 31 23 7 Program counter relative d 8 PC d 16 PC Memory indirect aa 8 Normal mode Advanced mode 31 0 Don t care 23 0 disp 0 31 23 31 0 Don t care disp op 23 op 8 abs 31 0 abs H 000000 7 8 0 15 31 23 31 0 Don t care 15 H 00 16 op abs 31 0 abs H 000000 7 8 0 31 24 24 24 No...

Page 87: ... CPU alters the normal processing flow due to an exception source such as a reset trace interrupt or trap instruction The CPU fetches a start address vector from the exception handling vector table and branches to that address For further details refer to section 4 Exception Handling Program Execution State In this state the CPU executes program instructions in sequence Bus Released State In a pro...

Page 88: ... low A transition can also be made to the reset state when the watchdog timer overflows 2 In every state when the STBY pin becomes low the hardware standby mode is entered 3 For details refer to section 22 Power Down Modes Figure 2 13 State Transitions 2 9 Usage Note 2 9 1 Usage Notes on Bit Wise Operation Instructions The BSET BCLR BNOT BST and BIST instructions are used to read data in bytes ope...

Page 89: ...Description 1 0 0 1 Boot mode Flash memory programming erasing 3 0 1 1 Emulation On chip emulation mode 5 1 0 1 User boot mode Flash memory programming erasing 7 1 1 1 Advanced Single chip mode with on chip ROM enable extended mode Modes 0 2 4 and 6 are not available with this LSI After a reset in mode 7 the operation is started in single chip mode It is possible to shift to extended mode when the...

Page 90: ...iptions 7 EXPE 0 R W Extended Mode Enable Extended Mode Set Up 0 Single chip mode 1 Extended mode 6 to 3 All 0 R Reserved 2 1 0 MDS2 MDS1 MDS0 R R R Mode Select 2 to 0 These bits indicate the input levels at pins MD2 to MD0 the current operating mode Bits MDS2 to MDS0 correspond to MD2 to MD0 MDS2 to MDS0 are read only bits and they cannot be written to The mode pin MD2 to MD0 input levels are lat...

Page 91: ...initial value should not be changed 3 XRST 1 R External Reset Indicates reset source Reset occurs as external reset input or watchdog timer overflow 0 Generated by watchdog timer overflow 1 Generated by external reset 2 FLASHE 0 R W Flash Memory Control Register Enable Controls CPU access to the flash memory control registers FCCS FPCS FECS FKEY FMATS and FTDAR 0 Flash memory control registers are...

Page 92: ... when the corresponding port data direction register DDR is set to 1 Port 3 is a data bus part of port 9 and port A become a bus control signal When the ABWn bit in BCRAn is cleared to 0 port 6 becomes the data bus n 1 to 3 Multiplex Extended Mode When using an 8 bit bus regardless of the data direction register DDR setting of port 2 it becomes an address output and data input output port Port 1 c...

Page 93: ...erating mode Table 3 2 Pin Functions in Each Operating Mode Mode 7 Port Normal Extended Mode Multiplex Extended Mode Port 1 P A P AD Port 2 P A P AD Port 3 P D P Port 6 P D P Port 9 P C P C Port A PA7 P C P C Legend P Input output port A Address bus output D Data bus input output AD Address data multiplex input output C Control signals clock input output Note After a reset ...

Page 94: ...l I O register 1 Area 3 Area 2 Area 1 H FEFFFF H FE0000 H FF9FFF H FF6000 H FF0000 H FDFFFF H FFFEFF H FFFFFF H FFC000 H FFFF7F H FFFF80 H FFFF00 Reserved Reserved Reserved On chip RAM 16384 bytes H FC0000 H FD0000 H FCFFFF H FBFFFF H FFA000 H FFBFFF H 07FFFF H 040000 Reserved H 080000 External address space H 03FFFF H 000000 On chip ROM Internal I O register 2 Internal I O register 1 H FF9FFF H F...

Page 95: ...or when the watchdog timer overflows The CPU enters the reset state when the RES pin is low Trace 1 Starts when execution of the current instruction or exception handling ends if the trace T bit in the EXR is set to 1 Direct transition 2 Starts when the direct transition occurs by execution of the SLEEP instruction Interrupt Starts when execution of the current instruction or exception handling en...

Page 96: ... to H 0017 Interrupt direct transition 3 6 H 000C to H 000D H 0018 to H 001B Interrupt NMI 7 H 000E to H 000F H 001C to H 001F Trap instruction 0 8 H 0010 to H 0011 H 0020 to H 0023 1 9 H 0012 to H 0013 H 0024 to H 0027 2 10 H 0014 to H 0015 H 0028 to H 002B 3 11 H 0016 to H 0017 H 002C to H 002F Reserved for system use 12 H 0018 to H 0019 H 0030 to H 0033 13 H 001A to H 001B H 0034 to H 0037 14 H...

Page 97: ...zes the internal state of the CPU and the registers of on chip peripheral modules The chip can also be reset by overflow of the watchdog timer For details see section 15 Watchdog Timer WDT The interrupt control mode is 0 immediately after reset 4 3 1 Reset exception handling When the RES pin goes high after being held low for the necessary time this LSI starts reset exception handling as follows 1...

Page 98: ...the stack pointer SP is initialized the PC and CCR will not be saved correctly leading to a program crash To prevent this all interrupt requests including NMI are disabled immediately after a reset Since the first instruction of a program is always executed immediately after the reset state ends make sure that this instruction initializes the stack pointer example MOV L xx 32 SP 4 3 3 On Chip Peri...

Page 99: ...d even within the trace exception handling routine Table 4 3 Status of CCR and EXR after Trace Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 Trace exception handling cannot be used 2 1 0 Legend 1 Set to 1 0 Cleared to 0 Retains value prior to execution 4 5 Interrupts Interrupts are controlled by the interrupt controller The interrupt controller has two interrupt control modes...

Page 100: ...bit is cleared to 0 3 A vector address corresponding to the interrupt source is generated the start address is loaded from the vector table to the PC and program execution starts from that address The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3 as specified in the instruction code Table 4 4 shows the status of CCR and EXR after e...

Page 101: ...n handling CCR CCR 1 PC 16 bits SP EXR Reserved 1 CCR CCR 1 PC 16 bits SP CCR PC 24 bits SP EXR Reserved 1 CCR PC 24 bits SP a Normal Modes 2 b Advanced Modes Interrupt control mode 0 Interrupt control mode 2 Interrupt control mode 0 Interrupt control mode 2 Notes 1 2 Ignored on return Normal modes are not available in this LSI Figure 4 2 Stack Status after Exception Handling ...

Page 102: ...restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 3 shows an example of operation when the SP value is odd SP CCR PC R1L SP Condition code register Program counter General register R1L Stack pointer CCR SP SP R1L H FFFEFA H FFFEFB H FFFEFC H FFFEFD H FFFEFE H FFFEFF PC PC TRAP instruction executed SP set to H FFFEFF Da...

Page 103: ...an be set for each module for all interrupts except NMI NMI is assigned the highest priority level of 8 and can be accepted at all times Independent vector addresses All interrupt sources are assigned independent vector addresses making it unnecessary for the source to be identified in the interrupt handling routine Nine external interrupts NMI is the highest priority interrupt and is accepted at ...

Page 104: ... INTM1 INTM0 NMIEG NMI input unit IRQ input unit ISR ISCR IER IPR Interrupt controller Priority determination Interrupt request Vector number I I2 to I0 CCR EXR CPU Legend ISCR IRQ sense control register IER IRQ enable register ISR IRQ status register IPR Interrupt priority register INTCR Interrupt control register Figure 5 1 Block Diagram of Interrupt Controller ...

Page 105: ... edge can be selected IRQ7 to IRQ0 Input Maskable external interrupts Rising falling or both edges or level sensing can be selected 5 3 Register Descriptions The interrupt controller has the following registers Interrupt control register INTCR IRQ sense control register H ISCR IRQ enable register IER IRQ status register ISR Software standby release IRQ enable register SSIER Interrupt priority regi...

Page 106: ...se bits select either of two interrupt control modes for the interrupt controller 00 Interrupt control mode 0 Interrupts are controlled by I bit 01 Setting prohibited 10 Interrupt control mode 2 Interrupts are controlled by bits I2 to I0 and IPR 11 Setting prohibited 3 NMIEG 0 R W NMI Edge Select Selects the input edge for the NMI pin 0 Interrupt request generated at falling edge of NMI input 1 In...

Page 107: ...ays read as 0 Write is invalid 14 13 12 IPR14 IPR13 IPR12 1 1 1 R W R W R W Sets the priority of the corresponding interrupt source 000 Priority level 0 Lowest 001 Priority level 1 010 Priority level 2 011 Priority level 3 100 Priority level 4 101 Priority level 5 110 Priority level 6 111 Priority level 7 Highest 11 0 Reserved This bit is always read as 0 Write is invalid 10 9 8 IPR10 IPR9 IPR8 1 ...

Page 108: ...riority level 3 100 Priority level 4 101 Priority level 5 110 Priority level 6 111 Priority level 7 Highest 3 0 Reserved This bit is always read as 0 Write is invalid 2 1 0 IPR2 IPR1 IPR0 1 1 1 R W R W R W Sets the priority of the corresponding interrupt source 000 Priority level 0 Lowest 001 Priority level 1 010 Priority level 2 011 Priority level 3 100 Priority level 4 101 Priority level 5 110 P...

Page 109: ...ed when this bit is 1 5 IRQ5E 0 R W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1 4 IRQ4E 0 R W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1 3 IRQ3E 0 R W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1 2 IRQ2E 0 R W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1 1 IRQ1E 0 R W IRQ1 Enable The IRQ1 interrupt r...

Page 110: ... and rising edges of IRQ7 input 13 12 IRQ6SCB IRQ6SCA 0 0 R W R W IRQ6 Sense Control B IRQ6 Sense Control A 00 Interrupt request generated at IRQ6 input low level 01 Interrupt request generated at falling edge of IRQ6 input 10 Interrupt request generated at rising edge of IRQ6 input 11 Interrupt request generated at both falling and rising edges of IRQ6 input 11 10 IRQ5SCB IRQ5SCA 0 0 R W R W IRQ5...

Page 111: ...W R W IRQ3 Sense Control B IRQ3 Sense Control A 00 Interrupt request generated at IRQ3 input low level 01 Interrupt request generated at falling edge of IRQ3 input 10 Interrupt request generated at rising edge of IRQ3 input 11 Interrupt request generated at both falling and rising edges of IRQ3 input 5 4 IRQ2SCB IRQ2SCA 0 0 R W R W IRQ2 Sense Control B IRQ2 Sense Control A 00 Interrupt request gen...

Page 112: ...f IRQ0 input 10 Interrupt request generated at rising edge of IRQ0 input 11 Interrupt request generated at both falling and rising edges of IRQ0 input 5 3 5 IRQ Status Register ISR ISR is an IRQ7 to IRQ0 interrupt request flag register Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Setting c...

Page 113: ...upt and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits The NMIEG bit in INTCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin IRQ7 to IRQ0 Interrupts Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0 Interrupts IRQ7 to IRQ0 have the following fe...

Page 114: ...ripheral modules have the following features For each on chip peripheral module there are flags that indicate the interrupt request status and enable bits that select enabling or disabling of these interrupts They can be controlled independently When the enable bit is set to 1 an interrupt request is sent to the interrupt controller The interrupt priority level can be set by means of IPR 5 5 Inter...

Page 115: ...14 to IPRB12 IRQ5 21 H 0054 IPRB10 to IPRB8 IRQ6 22 H 0058 IPRB6 to IPRB4 IRQ7 23 H 005C IPRB2 to IPRB0 24 H 0060 IPRC14 to IPRC12 25 H 0064 IPRC10 to IPRC8 26 H 0068 IPRC6 to IPRC4 27 H 006C IPRC2 to IPRC0 28 H 0070 29 H 0074 IPRD14 to IPRD12 30 H 0078 31 H 007C IPRD10 to IPRD8 Reserved for system use 32 H 0080 IPRD6 to IPRD4 WDT WOVI 33 H 0084 IPRD2 to IPRD0 34 H 0088 35 H 008C 36 H 0090 37 H 00...

Page 116: ... 00D8 TPU_1 TCI1U 55 H 00DC IPRF10 to IPRF8 TGI2A 56 H 00E0 TGI2B 57 H 00E4 TCI2V 58 H 00E8 TPU_2 TCI2U 59 H 00EC IPRF6 to IPRF4 CMIAX0 60 H 00F0 CMIBX0 61 H 00F4 OVIX0 62 H 00F8 TMRX_0 ICIX0 63 H 00FC IPRF2 to IPRF0 ICIA0 64 H 0100 ICIB0 65 H 0104 ICIC0 66 H 0108 ICID0 67 H 010C OCIA0 68 H 0110 OCIB0 69 H 0114 FRT_0 FOVI0 70 H 0118 IPRG14 to IPRG12 CMIA00 71 H 011C CMIB00 72 H 0120 TMR0_0 OVI00 7...

Page 117: ...CIB1 85 H 0154 ICIC1 86 H 0158 ICID1 87 H 015C OCIA1 88 H 0160 OCIB1 89 H 0164 FRT_1 FOVI1 90 H 0168 IPRH10 to IPRH8 CMIA01 91 H 016C CMIB01 92 H 0170 TMR0_1 OVI01 93 H 0174 IPRH6 to IPRH4 CMIA11 94 H 0178 CMIB11 95 H 017C TMR1_1 OVI11 96 H 0180 IPRH2 to IPRH0 CMIAY1 97 H 0184 CMIBY1 98 H 0188 TMRY_1 OVIY1 99 H 018C IPRI14 to IPRI12 TWOVI 100 H 0190 Duty measure ment circuit TWENDI 101 H 0194 IPRI...

Page 118: ... H 01C4 IPRJ14 to IPRJ12 ERI3 114 H 01C8 RXI3 115 H 01CC TXI3 116 H 01D0 SCI_3 TEI3 117 H 01D4 IPRJ10 to IPRJ8 ERI4 118 H 01D8 RXI4 119 H 01DC TXI4 120 H 01E0 SCI_4 TEI4 121 H 01E4 IPRJ6 to IPRJ4 IIC3_0 IICI0 122 H 01E8 IPRJ2 to IPRJ0 IIC3_1 IICI1 123 H 01EC IPRK14 to IPRK12 IIC3_2 IICI2 124 H 01F0 IPRK10 to IPRK8 IIC3_3 IICI3 125 H 01F4 IPRK6 to IPRK4 Reserved for system use 126 H 01F8 Reserved f...

Page 119: ...errupt acceptance operation in this case 1 If an interrupt source occurs when the corresponding interrupt enable bit is set to 1 an interrupt request is sent to the interrupt controller 2 If the I bit is set to 1 only an NMI interrupt is accepted and other interrupt requests are held pending If the I bit is cleared an interrupt request is accepted 3 Interrupt requests are sent to the interrupt con...

Page 120: ...terrupt generated NMI IRQ0 IRQ1 IICI3 I 0 Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5 3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 ...

Page 121: ...able 5 2 is selected 3 Next the priority of the selected interrupt request is compared with the interrupt mask level set in EXR An interrupt request with a priority no higher than the mask level set at that time is held pending and only an interrupt request with a priority higher than the interrupt mask level is accepted 4 When the CPU accepts an interrupt request it starts interrupt exception han...

Page 122: ...7 interrupt Mask level 6 or below Save PC CCR and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Hold pending Level 1 interrupt Mask level 0 Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 5 4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 ...

Page 123: ...errupt Exception Handling Sequence Figure 5 5 shows the interrupt exception handling sequence The example shown is for the case where interrupt control mode 0 is set in advanced mode and the program area and stack area are in on chip memory ...

Page 124: ...rnal read signal Internal write signal Internal data bus φ 3 1 2 4 3 5 7 Instruction prefetch address Not executed This is the contents of the saved PC the return address Instruction code Not executed Instruction prefetch address Not executed SP 2 SP 4 Saved PC and saved CCR Vector address Interrupt handling routine start address Vector address contents Interrupt handling routine start address 13 ...

Page 125: ...il executing instruction ends 2 1 to 19 2 SI 1 to 19 2 SI 1 to 19 2 SI 1 to 19 2 SI 3 PC CCR EXR stack save 2 SK 3 SK 2 SK 3 SK 4 Vector fetch SI SI 2 SI 2 SI 5 Instruction fetch 3 2 SI 2 SI 2 SI 2 SI 6 Internal processing 4 2 2 2 2 Total using on chip memory 11 to 31 12 to 32 12 to 32 13 to 33 Notes 1 Two states in case of internal interrupt 2 Refers to DIVXS instructions 3 Prefetch after interru...

Page 126: ...pletion of the instruction However if there is an interrupt request of higher priority than that interrupt interrupt exception handling will be executed for the higher priority interrupt and the lower priority interrupt will be ignored The same also applies when an interrupt source flag is cleared to 0 Figure 5 6 shows an example in which the TCIEV bit in the TPU s TIER_0 register is cleared to 0 ...

Page 127: ...ring the transfer is not accepted until the transfer is completed With the EEPMOV W instruction if an interrupt request is issued during the transfer interrupt exception handling starts at a break in the transfer cycle The PC value saved on the stack in this case is the address of the next instruction Therefore if an interrupt is generated during execution of an EEPMOV W instruction the following ...

Page 128: ... 03 page 90 of 704 5 7 6 Note on IRQ Status Register ISR Since IRQnF flags may be set to 1 depending on the pin states after a reset be sure to read from ISR after a reset and then write 0 to clear the IRQnF flags ...

Page 129: ...or common settings Area 2 and 3 bus specifications can be set independently Areas 1 2 and 3 enable chip select CS1 to CS3 output A maximum of 16 addresses can be output Area select signal address strobe hold signal polarity control It is possible to reverse the output polarity of CS1 to CS3 and AS AH by the PNCCS bit in BCRAn or the PNCASH bit in BCR Normal Extension Address output pins A15 to A0 ...

Page 130: ...d areas In the data cycle 2 state access areas or 3 state access areas are able to be selected The address cycle or data cycle can be independently inserted into the program wait state Idle cycle insert Idle cycle insert is possible during the external write cycle directly after external read cycle Bus controller External bus control signals Legend BCR BCRA1 BCRA2 BCRA3 Bus control register Basic ...

Page 131: ...t Chip select signal indicating that area 3 is accessed RD Output Strobe signal indicating that the external address area is being read HWR Output Strobe signal indicating that external address space is written to and upper half D15 to D8 AD15 to AD8 of data bus is enabled LWR Output Strobe signal indicating that basic bus interface space is written to and lower half D7 to D0 AD7 to AD0 of data bu...

Page 132: ... The initial value should not be changed 6 ICIS 1 R W Idle Cycle Insert When external read cycle and external write cycle continue it selects whether idle cycle 1 state is inserted or idle cycle is not inserted 0 Idle cycle is not inserted 1 Idle cycle 1 state is inserted 5 1 R W Reserved The initial value should not be changed 4 0 R W Reserved The initial value should not be changed 3 0 R W Reser...

Page 133: ...7 ABWn 1 R W Area Bus Width Control Selects the bus width for area n 0 16 bit 1 8 bit 6 ASTn 1 R W Area Access State Control Designates the number of access states in area n Simultaneously permits or prohibits wait state insertion Normal extension ADMXE 0 0 2 state access area wait state insertion prohibited 1 3 state access area wait state insertion permitted Multiplex extension ADMXE 1 0 Data 2 ...

Page 134: ...e address cycle 3 2 WMSn1 WMSn0 0 0 R W Area n Wait Mode Select 1 0 When the ASTn bit is set to 1 and area n is accessed wait mode is selected 00 Program wait mode 01 Wait prohibited mode 10 Pin wait mode 11 Pin auto wait mode 1 0 WCn1 WCn0 1 1 R W Area n Wait Count 1 0 Selects the number of data cycle program waits when area n is accessed 00 Program wait is not inserted 01 1 state is inserted int...

Page 135: ...3 Wait Mode and Number of Program Wait States When 3 state access space is designated by the ASTn bit in BCRAn the number of program wait states to be inserted automatically is selected with WMSn1 WMSn0 WCn1 and WCn0 in the BCRAn From 0 to 3 program wait states can be selected The external extended wait function is effective when the low speed device is connected to the external address area For d...

Page 136: ...s 2 state Data cycle state The number of access states for data access 2 state or 3 state can be selected with the ASTn bit in BCRAn When 2 state access space is designated wait state insertion is disabled 3 Wait Mode and Number of Program Wait States Address cycle wait The number of program wait states to be inserted into the address cycle are selected by the AWn bit in BCRAn 0 or 1 address cycle...

Page 137: ...000 to H FCFFFF 64 kbytes Area 1 H FD0000 to H FDFFFF 64 kbytes Area 2 H FE0000 to H FEFFFF 64 kbytes Area 3 H FF0000 to H FF9FFF 40 kbytes Integrated with basic area when RAME 0 use prohibited Table 6 5 Bus Specifications for Multiplex Extended Bus Interface Address Cycle ASTn AWn WMSn1 WMSn0 WCn1 WCn0 Number of Access States Number of Program Wait States 0 2 0 1 2 1 Legend n 1 to 3 Table 6 6 Bus...

Page 138: ...o CS3 for areas 0 to 3 respectively The CS1 to CS3 signal outputs low or high level when the corresponding external space area is accessed The chip select signal s output polarity can be controlled by the PNCCSn bit in BCRAn Figure 6 2 shows an example of CS1 to CS3 signal s output polarity and output timing Selection of CS1 to CS3 signal output and I O port input output is set by the port functio...

Page 139: ...ing or disabling of A15 to A0 signal output is set by the data direction register DDR bit for the port corresponding to the A15 to A0 pins In external extended mode the A15 to A0 pins are placed in the input state after a reset the corresponding DDR bits should be set to 1 when outputting signals A15 to A0 For details refer to section 7 I O Ports In multiplex extended mode the address output is de...

Page 140: ...dress space is accessed according to the bus specifications for the area being accessed 8 bit access space or 16 bit access space and the data size The multiplex extended address cycle is fixed to the bus specifications of the area being accessed 8 bit access space or 16 bit access space 8 Bit Access Space Figure 6 3 illustrates data alignment control for the 8 bit access space With the 8 bit acce...

Page 141: ...time is one byte or one word A longword access is executed as two word accesses In byte access whether the upper or lower data bus is used is determined by whether the address is even or odd The upper data bus is used for even addresses and the lower data bus for odd addresses D15 D8 D7 D0 Upper data bus Lower data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size Even address Byte...

Page 142: ...rea Access Size Read Write Address Valid Strobe Upper Data Bus D15 to D8 AD15 to AD8 Lower Data Bus D7 to D0 AD7 to AD0 8 bit access Byte Read RD Valid Ports or others space Write HWR Ports or others 16 bit access Byte Read Even RD Valid Invalid space Odd Invalid Valid Write Even HWR Valid Undefined Odd LWR Undefined Valid Word Read RD Valid Valid Write HWR LWR Valid Valid Note Undefined Undefined...

Page 143: ...ows the bus timing for an 8 bit 2 state access space When an 8 bit access space is accessed the upper half D15 to D8 of the data bus is used Wait states cannot be inserted Bus cycle T1 T2 Address bus D15 to D8 Valid D7 to D0 Invalid Read D15 to D8 Valid Write Note n 1 to 3 Figure 6 5 Bus Timing for 8 Bit 2 State Access Space ...

Page 144: ... bit 3 state access space When an 8 bit access space is accessed the upper half D15 to D8 of the data bus is used Wait states can be inserted Bus cycle T1 T2 Address bus D15 to D8 Valid D7 to D0 Invalid Read D15 to D8 Valid Write T3 Note n 1 to 3 Figure 6 6 Bus Timing for 8 Bit 3 State Access Space ...

Page 145: ...e is accessed the upper half D15 to D8 of the data bus is used for even addresses and the lower half D7 to D0 for odd addresses Wait states cannot be inserted Bus cycle T1 T2 Address bus D15 to D8 Valid D7 to D0 Invalid Read D15 to D8 Valid D7 to D0 Write High Note n 1 to 3 Undefined Figure 6 7 Bus Timing for 16 Bit 2 State Access Space Even Byte Access ...

Page 146: ...03 page 108 of 704 Bus cycle T1 T2 Address bus D15 to D8 Invalid D7 to D0 Valid Read D15 to D8 D7 to D0 Valid Write High Note n 1 to 3 Undefined Figure 6 8 Bus Timing for 16 Bit 2 State Access Space Odd Byte Access ...

Page 147: ... 00 09 03 page 109 of 704 Bus cycle T1 T2 Address bus D15 to D8 Valid D7 to D0 Valid Read D15 to D8 Valid D7 to D0 Valid Write Note n 1 to 3 Figure 6 9 Bus Timing for 16 Bit 2 State Access Space Word Access ...

Page 148: ...ce is accessed the upper half D15 to D8 of the data bus is used for even addresses and the lower half D7 to D0 for odd addresses Wait states can be inserted Bus cycle T1 T2 Address bus D15 to D8 Valid D7 to D0 Invalid Read D15 to D8 Valid D7 to D0 Write High T3 Note n 1 to 3 Undefined Figure 6 10 Bus Timing for 16 Bit 3 State Access Space Even Byte Access ...

Page 149: ... page 111 of 704 Bus cycle T1 T2 Address bus D15 to D8 Invalid D7 to D0 Valid Read D15 to D8 D7 to D0 Valid Write High T3 Note n 1 to 3 Undefined Figure 6 11 Bus Timing for 16 Bit 3 State Access Space Odd Byte Access ...

Page 150: ...0 09 03 page 112 of 704 Bus cycle T1 T2 Address bus D15 to D8 Valid D7 to D0 Valid Read D15 to D8 Valid D7 to D0 Valid Write T3 Note n 1 to 3 Figure 6 12 Bus Timing for 16 Bit 3 State Access Space Word Access ...

Page 151: ...t 2 state access space When an 8 bit access space is accessed the upper half AD15 to AD8 of the address bus and the data bus is used Wait states cannot be inserted T1 AD15 to AD8 TAW T2 T3 T1 TAW T2 T3 T4 T4 Read Cycle Write Cycle Address Address Data Data Note n 1 to 3 Address Address Data Data Figure 6 13 Bus Timing for 8 Bit 2 State Data Access Space With Address Wait ...

Page 152: ...ge 114 of 704 T1 AD15 to AD8 T2 T3 T1 T2 T3 T4 T4 Read Cycle Write Cycle Address Address Data Data Note n 1 to 3 Data Address Address Data Figure 6 14 Bus Timing for 8 Bit 2 State Data Access Space Without Address Wait ...

Page 153: ...cess space is accessed the upper half AD15 to AD8 of the address bus and the data bus are used Wait states can be inserted T1 AD15 to AD8 TAW T2 T3 TDSW T5 T4 Read Cycle Write Cycle Address Data Note n 1 to 3 Address Data T1 TAW T2 T3 TDSW T5 T4 Address Address Data Data Figure 6 15 Bus Timing for 8 Bit 3 State Data Access Space With Address Wait ...

Page 154: ...0 the upper half AD15 to AD8 of the data bus is used for even addresses and the lower half AD7 to AD0 for odd addresses Data cycle wait states cannot be inserted T1 AD15 to AD8 TAW T2 T3 T1 TAW T2 T3 T4 T4 Read Cycle Write Cycle Address Address Data Data Note n 1 to 3 Address Address Data Data Address Address AD7 to AD0 Figure 6 16 Bus Timing for 16 Bit 2 State Data Access Space 1 Even Byte Access...

Page 155: ...o AD8 T2 T3 T1 T2 T3 T4 T4 Read Cycle Write Cycle Address Address Data Data Note n 1 to 3 Data Address Address AD7 to AD0 Address Address Data Figure 6 17 Bus Timing for 16 Bit 2 State Data Access Space 2 Even Byte Access without Address Wait ...

Page 156: ...o AD8 TAW T2 T3 T1 TAW T2 T3 T4 T4 Read Cycle Write Cycle Address Address Data Data Note n 1 to 3 Address Address Data Data Address Address AD7 to AD0 Figure 6 18 Bus Timing for 16 Bit 2 State Access Space 3 Odd Byte Access with Address Wait ...

Page 157: ...o AD8 T2 T3 T1 T2 T3 T4 T4 Read Cycle Write Cycle Address Address Data Data Address Address AD7 to AD0 Note n 1 to 3 Address Address Data Data Figure 6 19 Bus Timing for 16 Bit 2 State Data Access Space 4 Odd Byte Access without Address Wait ...

Page 158: ... TAW T2 T3 T1 TAW T2 T3 T4 T4 Read Cycle Write Cycle Address Address Data Data Note n 1 to 3 Data AD7 to AD0 Data Address Address Data Address Address Data Figure 6 20 Bus Timing for 16 Bit 2 State Data Access Space 5 Word Access with Address Wait ...

Page 159: ...D8 AD7 to AD0 T2 T3 T1 T2 T3 T4 T4 Read Cycle Write Cycle Address Address Data Data Note n 1 to 3 Address Address Data Data Address Address Data Data Figure 6 21 Bus Timing for 16 Bit 2 State Data Access Space 6 Word Access without Address Wait ...

Page 160: ...pper half AD15 to AD8 of the data bus is used for even addresses and the lower half AD7 to AD0 for odd addresses Data cycle wait states can be inserted T1 AD15 to AD8 TAW T2 T3 TDSW T5 T4 Read Cycle Write Cycle Address Data Note n 1 to 3 Address Data Data T1 TAW T2 T3 TDSW T5 T4 Address Address Data AD7 to AD0 Address Address Figure 6 22 Bus Timing for 16 Bit 3 State Data Access Space 1 Even Byte ...

Page 161: ...T2 T3 TDSW T5 T4 Read Cycle Write Cycle Address Data Note n 1 to 3 Address Data Data T1 TAW T2 T3 TDSW T5 T4 Address Address Data AD7 to AD0 Address Address Figure 6 23 Bus Timing for 16 Bit 3 State Data Access Space 2 Odd Byte Access with Address Wait ...

Page 162: ...T3 TDSW T5 T4 Read Cycle Write Cycle Address Data Note n 1 to 3 Address Data Data T1 TAW T2 T3 TDSW T5 T4 Address Address Data AD7 to AD0 Address Data Address Data Figure 6 24 Bus Timing for 16 Bit 3 State Data Access Space 3 Word Access with Address Wait ...

Page 163: ...is low at the falling edge of φ in the last T2 or TW state another TW state is inserted If the WAIT pin is held low TW states are inserted until it goes high Pin wait mode is useful when inserting four or more TW states or when changing the number of TW states to be inserted for each external device 3 Pin Auto Wait Mode A specified number of wait states TW are inserted between the T2 state and T3 ...

Page 164: ...n 1 to 3 Figure 6 25 Example of Wait State Insertion Timing Normal Extended Pin Wait Mode In Multiplex Extended Mode 1 Program Wait Mode Program wait mode includes address wait and data wait Zero to one state of address wait TAW is inserted between T1 and T2 states Zero to three states of data wait TDSW are inserted between T4 and T5 states The address cycle always operates in program wait mode ...

Page 165: ...it states TDOW are inserted between the T4 state and T5 state when accessing the external address space if the WAIT pin is low at the falling edge of φ in the last T4 state The number of wait states TDOW is specified by the settings of the WCn1 and WCn0 bits Even if the WAIT pin is held low TDOW states are inserted only up to the specified number of states Pin auto wait mode enables the low speed ...

Page 166: ...r an external read while the ICIS bit is set to 1 in BCR an idle cycle is inserted at the start of the external cycle after the external read Figure 6 27 shows examples of idle cycle operation In these examples bus cycle A is a read cycle for ROM with a long output floating time and bus cycle B is a CPU write cycle In figure 6 27 a with no idle cycle inserted a conflict occurs in bus cycle B betwe...

Page 167: ...n Idle Cycle Pins Pin State A15 to A0 Contents of immediately following bus cycle D15 to D0 High impedance AD15 to AD0 High impedance AS AH High when PNCASH 0 Low when PNCASH 1 CSn High when PNCCSn 0 Low when PNCCSn 1 RD High HWR LWR High Legend n 1 to 3 ...

Page 168: ...Rev 1 00 09 03 page 130 of 704 ...

Page 169: ...ORT that reads a pin state DDR and DR are not provided for ports 0 7 and C Ports 1 to 3 and 6 have on chip input pull up MOSs DDR and an pull up MOS control register PCR can be used to control the on off status of the input pull up MOSs Port 6 has an on chip open drain control register ODR that can be used to control the on off status of the output buffer PMOS Ports 1 to 6 and 9 can drive a single...

Page 170: ...s data multiplex input output and PWM output P17 A7 P16 A6 P15 A5 P14 A4 P13 A3 P12 A2 P11 A1 P10 A0 AD7 1 AD6 1 AD5 1 AD4 1 AD3 1 AD2 1 AD1 1 AD0 1 P17 PW7 2 P16 PW6 2 P15 PW5 2 P14 PW4 2 P13 PW3 2 P12 PW2 2 P11 PW1 2 P10 PW0 2 On chip input pull up MOS Port 2 General I O port also functioning as an address output address data multiplex input output and TPU input output P27 A15 P26 A14 P25 A13 P2...

Page 171: ...xIRQ0 On chip input pull up MOS Port 4 General I O port also functioning as an interrupt input TMR0_0 TMR0_1 TMRX_0 TMRX_1 TMRY_0 TMRY_1 and FRT_1 input and PWM output P47 IRQ7 TMIY_0 ExPW3 P46 IRQ6 TMIX_0 ExPW2 P45 IRQ5 TMI0_0 ExPW1 P44 IRQ4 TMIY_1 ExPW0 P43 IRQ3 TMIX_1 P42 IRQ2 TMI0_1 P41 IRQ1 FTIC_1 P40 IRQ0 FTIB_1 Port 5 General I O port also functioning as a TMR0_1 and TMR1_1 output SCI_0 and...

Page 172: ...l data bus FRT_1 input output TMRX_1 and TMRY_1 output and SCI_2 input output D7 3 D6 3 D5 3 D4 3 D3 3 D2 3 D1 3 D0 3 P67 RxD2 4 P66 TxD2 4 P65 SCK2 4 P64 FTCI_1 4 P63 TMOY_1 4 P62 TMOX_1 4 P61 FTOB_1 4 P60 FTOA_1 4 On chip input pull up MOS Open drain output enabled Port 7 General input port also functioning as an A D converter analog input P77 AN7 P76 AN6 P75 AN5 P74 AN4 P73 AN3 P72 AN2 P71 AN1 ...

Page 173: ...tput and TPU input output P87 ADTRG ExTIOCB0 P86 ExTIOCA0 P85 PWX1 P84 PWX0 P83 SDA1 RxD4 P82 SCL1 TxD4 P81 SDA0 RxD3 P80 SCL0 TxD3 NMOS push pull output P80 to P83 P97 WAIT ExTIOCD0 ExTCLKB P97 ExTIOCD0 ExTCLKB P96 φ P96 P95 AS AH P95 HWR P94 RD P93 P92 CS1 ExTIOCB2 ExTCLKD P92 ExTIOCB2 ExTCLKD P91 CS2 ExTIOCA2 P91 ExTIOCA2 Port 9 General I O port also functioning as a bus control input output sy...

Page 174: ... an FRT_0 and TMR1_0 input output FRT_1 and TMR1_1 input and timer connection input output PB7 TMI1_0 HSYNCI_0 PB6 FTIA_0 VSYNCI_0 PB5 FTID_0 CSYNCI_0 PB4 TMI1_1 HSYNCI_1 PB3 FTIA_1 VSYNCI_1 PB2 FTID_1 CSYNCI_1 PB1 TMO1_0 HSYNCO PB0 FTOA_0 VSYNCO Port C General I O port also functioning as an on chip emulator input output and IIC3_2 and IIC3_3 input output PC7 5 ETDO PC6 5 ETDI PC5 5 ETCK PC4 5 ET...

Page 175: ...RT0 cannot be modified Bit Bit Name Initial Value R W Description 7 P07 R 6 P06 R 5 P05 R 4 P04 R 3 P03 R 2 P02 R 1 P01 R 0 P00 R When this register is read the pin state is always read Note Determined by the states of the P07 to P00 pins 7 1 2 Pin Functions If the corresponding bit in PTCNT1 is set to 1 the port 0 pins can be used as interrupt input pins ExIRQ7 to ExIRQ4 Pin function relationship...

Page 176: ...the ExIRQ6 input P05 AN13 ExIRQ5 P05 input pin Pin function AN13 input pin ExIRQ5 input pin Note When the IRQ5S bit in PTCNT1 is set to 1 it functions as the ExIRQ5 input P04 AN12 ExIRQ4 P04 input pin Pin function AN12 input pin ExIRQ4 input pin Note When the IRQ4S bit in PTCNT1 is set to 1 it functions as the ExIRQ4 input P03 AN11 P03 input pin Pin function AN11 input pin P02 AN10 P02 input pin P...

Page 177: ...DDR specify input or output for the pins of port 1 The read value is undefined Bit Bit Name Initial Value R W Description 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W 4 P14DDR 0 W 3 P13DDR 0 W 2 P12DDR 0 W 1 P11DDR 0 W 0 P10DDR 0 W In normal extended mode The corresponding port 1 pins are address outputs when P1DDR bits are set to 1 and input ports when cleared to 0 In multiplex extended mode 16 bit bus...

Page 178: ...output data for the port 1 pins that are used as the general output ports 7 2 3 Port 1 Register PORT1 PORT1 reflects the pin state in port 1 and cannot be modified Bit Bit Name Initial Value R W Description 7 P17 R 6 P16 R 5 P15 R 4 P14 R 3 P13 R 2 P12 R 1 P11 R 0 P10 R When this register is read the bit that is set in P1DDR is read as the value of P1DR The bit that is cleared in P1DDR is read as ...

Page 179: ...8 bit bus width operates as single chip mode 7 2 5 Pin Functions When the PWnS bit in PTCNT0 is cleared to 0 port 1 pins can be used as PWM output pins PW7 to PW0 The pin function relationships are listed below According to the combinations of operating modes and the OEn bit PWnS bit and P1nDDR bit in PWOER of the PWM pin functions change as follows Extended Mode EXPE 1 Normal Extended Mode ADMXE ...

Page 180: ...States Port 1 has an on chip input pull up MOS that can be controlled by software This input pull up MOS can be used regardless of the operating mode Table 7 2 summarizes the input pull up MOS states Table 7 2 Port 1 Input Pull Up MOS States Reset Hardware Standby Mode Software Standby Mode In Other Operations Off Off On Off On Off Legend Off Always off On Off On when P1DDR 0 and P1PCR 1 otherwise...

Page 181: ...R The individual bits in P2DDR specify input or output for the pins of port 2 The read value is undefined Bit Bit Name Initial Value R W Description 7 P27DDR 0 W 6 P26DDR 0 W 5 P25DDR 0 W 4 P24DDR 0 W 3 P23DDR 0 W 2 P22DDR 0 W 1 P21DDR 0 W 0 P20DDR 0 W In normal extended mode The corresponding port 2 pin is an address output when a P2DDR bit is set to 1 and an input port when cleared to 0 In multi...

Page 182: ...ores output data for the port 2 pins that are used as the general output ports 7 3 3 Port 2 Register PORT2 PORT2 reflects the pin state in port 2 and cannot be modified Bit Bit Name Initial Value R W Description 7 P27 R 6 P26 R 5 P25 R 4 P24 R 3 P23 R 2 P22 R 1 P21 R 0 P20 R When this register is read the bit that is set in P2DDR is read as the value of P2DR The bit that is cleared in P2DDR is rea...

Page 183: ...sponding bit in PTCNT2 is cleared to 0 port 2 pins can be used as TPU I O pins The relationship between register setting values and pin functions is as follows P27 TIOCB2 TCLKD A15 AD15 When the TIOCB2 TCLKDS bit in PTCNT2 is cleared to 0 this pin can be used as the TIOCB2 TCLKD pin According to operating modes the TPU channel 2 settings by the MD3 to MD0 bits in TMDR_2 the IOB3 to IOB0 bits in TI...

Page 184: ... 01xx and IOB3 1 this pin functions as the TIOCB2 input pin 2 When TIOCB2 TCLKDS 0 and TPSC2 to TPSC0 in TCR_0 B 111 this pin functions as the TCLKD input pin When TIOCB2 TCLKDS 0 and phase count mode is set to the TCR channel 2 this pin functions as the TCLKD input pin P26 TIOCA2 A14 AD14 When the TIOCA2S bit in PTCNT2 is cleared to 0 this pin can be used as the TIOCA2 pin According to operating ...

Page 185: ... B 01 Output function Output compare output PWM 2 mode 1 output PWM mode 2 output Legend x Don t care Notes 1 When TIOCA2S 0 MD3 to MD0 B 0000 or B 01xx and IOA3 1 this pin functions as the TIOCA2 input pin 2 Output is disabled for TIOCB2 P25 TIOCB1 TCLKC A13 AD13 When the TIOCB1 TCLKCS bit in PTCNT2 is cleared to 0 this pin can be used as the TIOCB1 TCLKC pin According to operating modes the TPU ...

Page 186: ...n P25 output pin TPU channel 1 setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 01xx B 0010 B 0011 IOB3 to IOB0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 10 B 10 Output function Output compare output PWM mode 2 output Legend x Don t care Notes 1 When TIOCB1 TCLKCS 0 MD3 to MD0 B 0000 or B 01xx and IOB3 to IOB0 B 10xx this pin functions as the T...

Page 187: ...O pin Pin function TIOCA1 input pin 1 Single Chip Mode EXPE 0 TIOCA2S 0 1 TPU channel 1 setting Table below 2 Table below 1 P24DDR 0 1 0 1 P24 input pin P24 output pin Pin function TIOCA1 input pin 1 TIOCA1 output pin P24 input pin P24 output pin TPU channel 1 setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx0...

Page 188: ... Mode EXPE 1 Normal Extended Mode ADMXE 0 Multiplex Extended Mode ADMXE 1 P23DDR 0 1 P23 input pin A11 output pin AD11 I O pin TIOCD0 input pin 1 Pin function TCLKB input pin 2 Single Chip Mode EXPE 0 TIOCD0 TCLKBS 0 1 TPU channel 0 setting Table below 2 Table below 1 P23DDR 0 1 0 1 P23 input pin P23 output pin TIOCD0 input pin 1 TIOCD0 output pin Pin function TCLKB input pin 2 P23 input pin P23 o...

Page 189: ... According to operating modes the TPU channel 0 settings by the MD3 to MD0 bits in TMDR_0 the IOC3 to IOC0 bits in TIORL_0 and the CCLR2 to CCLR0 bits in TCR_0 and the combination of the TPSC2 to TPSC0 bits in TCR_0 to TCR_2 the TIOCC0 TCLKAS bit and the P22DDR bit pin functions change as follows Extended Mode EXPE 1 Normal Extended Mode ADMXE 0 Multiplex Extended Mode ADMXE 1 P22DDR 0 1 P22 input...

Page 190: ...1 this pin functions as the TCLKA input pin 3 Output is disabled for TIOCD0 When BFA 1 or BFB 1 in TMDR0 output is disabled and the setting is the same as 2 P21 TIOCB0 A9 AD9 When the TIOCB0S bit in PTCNT2 is cleared to 0 this pin can be used as the TIOCB0 pin According to operating modes the TPU channel 0 settings by the MD3 to MD0 bits in TMDR_0 and the IOB3 to IOB0 bits in TIORH_0 and the combi...

Page 191: ... to 0 this pin can be used as the TIOCA0 pin According to operating modes the TPU channel 0 settings by the MD3 to MD0 bits in TMDR_0 the IOA3 to IOA0 bits in TIORH_0 and the CCLR2 to CCLR0 bits in TCR_0 and the combination of the TIOCA0S bit and the P20DDR bit pin functions change as follows Extended Mode EXPE 1 Normal Extended Mode ADMXE 0 Multiplex Extended Mode ADMXE 1 P20DDR 0 1 P20 input pin...

Page 192: ... TIOCA0S 0 MD3 to MD0 B 0000 and IOA3 to IOA0 B 10xx this pin functions as the TIOCA0 input pin 2 Output is disabled for TIOCB0 7 3 6 Port 2 Input Pull Up MOS States Port 2 has an on chip input pull up MOS that can be controlled by software This input pull up MOS can be used regardless of the operating mode Table 7 3 summarizes the input pull up MOS states Table 7 3 Port 2 Input Pull Up MOS States...

Page 193: ...register P3PCR 7 4 1 Port 3 Data Direction Register P3DDR The individual bits in P3DDR specify input or output for the pins of port 3 The read value is undefined Bit Bit Name Initial Value R W Description 7 P37DDR 0 W 6 P36DDR 0 W 5 P35DDR 0 W 4 P34DDR 0 W 3 P33DDR 0 W 2 P32DDR 0 W 1 P31DDR 0 W 0 P30DDR 0 W In normal extended mode Operation is not affected In multiplex extended mode Operates as si...

Page 194: ...ores output data for the port 3 pins that are used as the general output ports 7 4 3 Port 3 Register PORT3 PORT3 reflects the pin state in port 3 and cannot be modified Bit Bit Name Initial Value R W Description 7 P37 R 6 P36 R 5 P35 R 4 P34 R 3 P33 R 2 P32 R 1 P31 R 0 P30 R When this register is read the bit that is set in P3DDR is read as the value of P3DR The bit that is cleared in P3DDR is rea...

Page 195: ...turned on when a P3PCR bit is set to 1 7 4 5 Pin Functions When the corresponding bit in PTCNT1 is set to 1 port 3 pins can be used as interrupt input pins ExIRQ3 to ExIRQ0 In normal extended mode port 3 pins function as data I O pins In multiplex extended mode operation of port 3 pins is the same as that in single chip mode The relationship between register setting values and pin functions is as ...

Page 196: ...as shown below according to the operating mode and the P35DDR bit Extended Mode EXPE 1 Normal Extended Mode ADMXE 0 Multiplex Extended Mode ADMXE 1 Single Chip Mode EXPE 0 P35DDR 0 1 0 1 Pin function D13 I O pin P35 input pin P35 output pin P35 input pin P35 output pin P34 D12 The pin function is switched as shown below according to the operating mode and the P34DDR bit Extended Mode EXPE 1 Normal...

Page 197: ...n function ExIRQ3 input pin Note When the IRQ3S bit in PTCNT1 is set to 1 this pin functions as the ExIRQ3 input pin P32 D10 ExIRQ2 When the IRQ2S bit in PTCNT1 is set to 1 this pin can be used as the ExIRQ2 pin The pin function is switched as shown below according to the operating mode the IRQ2S bit and the P32DDR bit Extended Mode EXPE 1 Normal Extended Mode ADMXE 0 Multiplex Extended Mode ADMXE...

Page 198: ...n function ExIRQ1 input pin Note When the IRQ1S bit in PTCNT1 is set to 1 this pin functions as the ExIRQ1 input pin P30 D8 ExIRQ0 When the IRQ0S bit in PTCNT1 is set to 1 this pin can be used as the ExIRQ0 pin The pin function is switched as shown below according to the operating mode the IRQ0S bit and the P30DDR bit Extended Mode EXPE 1 Normal Extended Mode ADMXE 0 Multiplex Extended Mode ADMXE ...

Page 199: ...ltiplex extended modes Table 7 4 summarizes the input pull up MOS states Table 7 4 Port 3 Input Pull Up MOS States Mode Reset Hardware Standby Mode Software Standby Mode In Other Operations Normal extended mode EXPE 1 ADMXE 0 Off Off Off Off Single chip mode EXPE 0 Multiplex extended mode EXPE 1 ADMXE 1 Off Off On Off On Off Legend Off Always off On Off On when input state and P3PCR 1 otherwise of...

Page 200: ...a register P4DR Port 4 register PORT4 7 5 1 Port 4 Data Direction Register P4DDR The individual bits in P4DDR specify input or output for the pins of port 4 The read value is undefined Bit Bit Name Initial Value R W Description 7 P47DDR 0 W 6 P46DDR 0 W 5 P45DDR 0 W 4 P44DDR 0 W 3 P43DDR 0 W 2 P42DDR 0 W 1 P41DDR 0 W 0 P40DDR 0 W While a general I O port function is selected the corresponding port...

Page 201: ...ores output data for the port 4 pins that are used as the general output ports 7 5 3 Port 4 Register PORT4 PORT4 reflects the pin state in port 4 and cannot be modified Bit Bit Name Initial Value R W Description 7 P47 R 6 P46 R 5 P45 R 4 P44 R 3 P43 R 2 P42 R 1 P41 R 0 P40 R When this register is read the bit that is set in P4DDR is read as the value of P4DR The bit that is cleared in P4DDR is rea...

Page 202: ...the TMRY_0 this pin functions as a TMCIY input pin When the CCLR1 and CCLR0 bits in TCR of the TMRY_0 are both set to 1 this pin functions as a TMRIY input pin P47DDR 0 1 PW3S 0 1 OE3 0 1 P47 input pin P47 output pin P47 output pin PW3 output pin TMIY_0 TMCIY TMRIY input pin Pin function IRQ7 input pin Note When the IRQ7S bit in PTCNT1 is cleared to 0 this pin functions as the IRQ7 input pin P46 I...

Page 203: ...put pin When the CCLR1 and CCLR0 bits in TCR of the TMR0_0 are both set to 1 this pin functions as a TMRI0 input pin P45DDR 0 1 PW1S 0 1 OE1 0 1 P45 input pin P45 output pin P45 output pin PW1 output pin TMI0_0 TMCI0 TMRI0 input pin Pin function IRQ5 input pin Note When the IRQ5S bit in PTCNT1 is cleared to 0 this pin functions as the IRQ5 input pin P44 IRQ4 TMIY_1 ExPW0 When the IRQ4S bit in PTCN...

Page 204: ... to 1 this pin functions as a TMRIX input pin P43DDR 0 1 P44 input pin P44 output pin TMIX_1 TMCIX TMRIX input pin Pin function IRQ3 input pin Note When the IRQ3S bit in PTCNT1 is cleared to 0 this pin functions as the IRQ3 input pin P42 IRQ2 TMI0_1 When the IRQ2S bit in PTCNT1 is cleared to 0 this pin can be used as an IRQ2 pin The pin function is switched as shown below according to the combinat...

Page 205: ...n function IRQ1 input pin Note When the IRQ1S bit in PTCNT1 is cleared to 0 this pin functions as the IRQ1 input pin P40 IRQ0 FTIB_1 When the IRQ0S bit in PTCNT1 is cleared to 0 this pin can be used as an IRQ0 pin The pin function is switched as shown below according to the combination of the IRQ0S bit and the P40DDR bit When the ICIBE bit in TIER of the FRT_1 is set to 1 this pin functions as an ...

Page 206: ...Port 5 register PORT5 7 6 1 Port 5 Data Direction Register P5DDR The individual bits in P5DDR specify input or output for the pins of port 5 The read value is undefined Bit Bit Name Initial Value R W Description 7 P57DDR 0 W 6 P56DDR 0 W 5 P55DDR 0 W 4 P54DDR 0 W 3 P53DDR 0 W 2 P52DDR 0 W 1 P51DDR 0 W 0 P50DDR 0 W While a general I O port function is selected the corresponding port 5 pin is an out...

Page 207: ...ores output data for the port 5 pins that are used as the general output ports 7 6 3 Port 5 Register PORT5 PORT5 reflects the pin state in port 5 and cannot be modified Bit Bit Name Initial Value R W Description 7 P57 R 6 P56 R 5 P55 R 4 P54 R 3 P53 R 2 P52 R 1 P51 R 0 P50 R When this register is read the bit that is set in P5DDR is read as the value of P5DR The bit that is cleared in P5DDR is rea...

Page 208: ...it in PWOER of the PWM the PW5S bit and the P57DDR bit OS3 to OS0 All 0 At lease one bit is set to 1 P57DDR 0 1 PW5S 0 1 OE5 0 1 Pin function P57 input pin P57 output pin P57 output pin ExPW5 output pin TMO1_1 output pin P56 TMO0_1 ExPW4 When the PW4S bit in PTCNT0 is set to 1 this pin can be used as an ExPW4 pin The pin function is switched as shown below according to the combination of the OS3 t...

Page 209: ...TE 0 1 P54DDR 0 1 Pin function P54 input pin P54 output pin TxD1 output pin P53 SCK1 The pin function is switched as shown below according to the combination of the C A bit in SMR of the SCI_1 the CKE0 and CKE1 bits in SCR and the P53DDR bit CKE1 0 1 C A 0 1 CKE0 0 1 P53DDR 0 1 Pin function P53 input pin P53 output pin SCK1 output pin SCK1 output pin SCK1 input pin P52 RxD0 The pin function is swi...

Page 210: ...TE 0 1 P51DDR 0 1 Pin function P51 input pin P51 output pin TxD0 output pin P50 SCK0 The pin function is switched as shown below according to the combination of the C A bit in SMR of the SCI_0 the CKE0 and CKE1 bits in SCR and the P50DDR bit CKE1 0 1 C A 0 1 CKE0 0 1 P50DDR 0 1 Pin function P50 input pin P50 output pin SCK0 output pin SCK0 output pin SCK0 input pin ...

Page 211: ...er P6ODR 7 7 1 Port 6 Data Direction Register P6DDR The individual bits in P6DDR specify input or output for the pins of port 6 The read value is undefined Bit Bit Name Initial Value R W Description 7 P67DDR 0 W 6 P66DDR 0 W 5 P65DDR 0 W 4 P64DDR 0 W 3 P63DDR 0 W 2 P62DDR 0 W 1 P61DDR 0 W 0 P60DDR 0 W In normal extended mode 16 bit data bus Operation is not affected In normal extended mode 8 bit d...

Page 212: ...ores output data for the port 6 pins that are used as the general output ports 7 7 3 Port 6 Register PORT6 PORT6 reflects the pin state in port 6 and cannot be modified Bit Bit Name Initial Value R W Description 7 P67 R 6 P66 R 5 P65 R 4 P64 R 3 P63 R 2 P62 R 1 P61 R 0 P60 R When this register is read the bit that is set in P6DDR is read as the value of P6DR The bit that is cleared in P6DDR is rea...

Page 213: ...bit is set to 1 7 7 5 Port 6 Open Drain Control Register P6ODR P6ODR specifies the output type of port 6 Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 P67ODR P66ODR P65ODR P64ODR P63ODR P62ODR P61ODR P60ODR 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Setting a bit to 1 specifies the PMOS of the corresponding pin to the off state When a pin function is specified as an output port o...

Page 214: ...bit RE P67DDR Pin function D7 I O pin Single chip operation Single chip operation Note When the ABW3 to ABW1 bits in BCRA3 to BCRA1 are all set to 1 bus width is 8 bits if any are cleared to 0 bus width is 16 bits Single Chip Mode EXPE 0 RE 0 1 P67DDR 0 1 Pin function P67 input pin P67 output pin RxD2 input pin ...

Page 215: ... if any are cleared to 0 bus width is 16 bits Single Chip Mode EXPE 0 TE 0 1 P66DDR 0 1 Pin function P66 input pin P66 output pin TxD2 output pin P65 SCK2 D5 The pin function is switched as shown below according to the combination of the operating mode the C A bit in SMR of the SCI_2 the CKE0 and CKE1 bits in SCR and the P65DDR bit Extended Mode EXPE 1 Normal Extended Mode ADMXE 0 Multiplex Extend...

Page 216: ...CKS1 and CKS0 bits in TCR of the FRT_1 are all set to 1 this pin functions as an FTCI_1 input pin Extended Mode EXPE 1 Normal Extended Mode ADMXE 0 Multiplex Extended Mode ADMXE 1 Bus width 16 bit 8 bit P64DDR D4 I O pin Pin function FTCI_1 input pin Single chip operation Single chip operation Note When the ABW3 to ABW1 bits in BCRA3 to BCRA1 are all set to 1 bus width is 8 bits if any are cleared...

Page 217: ...OS3 to OS0 All 0 At least one bit is set to 1 P63DDR 0 1 Pin function P63 input pin P63 output pin TMOY_1 output pin P62 TMOX_1 D2 The pin function is switched as shown below according to the combination of the operating mode the OS3 to OS0 bits in TCSR of the TMRX_1 and the P62DDR bit Extended Mode EXPE 1 Normal Extended Mode ADMXE 0 Multiplex Extended Mode ADMXE 1 Bus width 16 bit 8 bit OS3 to O...

Page 218: ...EXPE 0 OEB All 0 At least one bit is set to 1 P61DDR 0 1 Pin function P61 input pin P61 output pin FTOB_1 output pin P60 FTOA_1 D0 The pin function is switched as shown below according to the combination of the operating mode the OEA bit in TOCR of the FRT_1 and the P60DDR bit Extended Mode EXPE 1 Normal Extended Mode ADMXE 0 Multiplex Extended Mode ADMXE 1 Bus width 16 bit 8 bit OEA P60DDR Pin fu...

Page 219: ...n Off On when input state and P6PCR 1 otherwise off 7 8 Port 7 Port 7 is an 8 bit input port Port 7 pins also function as A D converter analog input pins Port 7 has the following register Port 7 register PORT7 7 8 1 Port 7 Register PORT7 PORT7 is an 8 bit read only register that reflects the pin state in port 7 PORT7 cannot be modified Bit Bit Name Initial Value R W Description 7 P77 R 6 P76 R 5 P...

Page 220: ...n P76 AN6 P76 input pin Pin function AN6 input pin P75 AN5 P75 input pin Pin function AN5 input pin P74 AN4 P74 input pin Pin function AN4 input pin P73 AN3 P73 input pin Pin function AN3 input pin P72 AN2 P72 input pin Pin function AN2 input pin P71 AN1 P71 input pin Pin function AN1 input pin P70 AN0 P70 input pin Pin function AN0 input pin ...

Page 221: ...ers Port 8 data direction register P8DDR Port 8 data register P8DR Port 8 register PORT8 7 9 1 Port 8 Data Direction Register P8DDR The individual bits in P8DDR specify input or output for the pins of port 8 The read value is undefined Bit Bit Name Initial Value R W Description 7 P87DDR 0 W 6 P86DDR 0 W 5 P85DDR 0 W 4 P84DDR 0 W 3 P83DDR 0 W 2 P82DDR 0 W 1 P81DDR 0 W 0 P80DDR 0 W While a general I...

Page 222: ...ores output data for the port 8 pins that are used as the general output ports 7 9 3 Port 8 Register PORT8 PORT8 reflects the pin state in port 8 and cannot be modified Bit Bit Name Initial Value R W Description 7 P87 R 6 P86 R 5 P85 R 4 P84 R 3 P83 R 2 P82 R 1 P81 R 0 P80 R When this register is read the bit that is set in P8DDR is read as the value of P8DR The bit that is cleared in P8DDR is rea...

Page 223: ...TIORH_0 the TIOCB0S bit and the P87DDR bit When the TRGS1 and TRGS0 bits in ADCR are all set to 1 this pin functions as an ADTRG input pin TIOCB0S 0 1 TIOCB0 output Table below 2 Table below 1 P87DDR 0 1 0 1 P87 input pin P87 output pin P87 input pin P87 output pin ExTIOCB0 input pin ExTIOCB0 output pin Pin function ADTRG input pin TPU channel 0 setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 0010 B 0011 ...

Page 224: ...in ExTIOCA0 input pin 1 ExTIOCA0 output pin TPU channel 0 setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 001 B 001 Output function Output compare output PWM 2 mode 1 output PWM mode 2 output Legend x Don t care Notes 1 When TIOCA0S 1 MD3 to MD0 B 00...

Page 225: ...tput format is NMOS push pull output The output format for SDA1 is NMOS open drain output and direct bus drive is possible ICE 0 1 RE 0 1 P83DDR 0 1 Pin function P83 input pin P83 output pin RxD4 input pin SDA1 I O pin P82 SCL1 TxD4 The pin function is switched as shown below according to the combination of the TE bit in SCR of the SCI_4 the ICE bit in ICCRA of the IIC3_1 and the P82DDR bit When t...

Page 226: ...ive is possible ICE 0 1 RE 0 1 P81DDR 0 1 Pin function P81 input pin P81 output pin RxD3 input pin SDA0 I O pin P80 SCL0 TxD3 The pin function is switched as shown below according to the combination of the TE bit in SCR of the SCI_3 the ICE bit in ICCRA of the IIC3_0 and the P80DDR bit When this pin is used as the TxD3 or P80 output pin the output format is NMOS push pull output The output format ...

Page 227: ...the pins of port 9 The read value is undefined Bit Bit Name Initial Value R W Description 7 P97DDR 0 W If port 9 pins are specified for use as the general I O port the corresponding port 9 pins are output ports when the P9DDR bits are set to 1 and input ports when cleared to 0 6 P96DDR 0 W When this bit is set to 1 the corresponding port 9 pin is the system clock output pin φ and as a general inpu...

Page 228: ...ores output data for the port 9 pins that are used as the general output ports 7 10 3 Port 9 Register PORT9 PORT9 reflects the pin state in port 9 and cannot be modified Bit Bit Name Initial Value R W Description 7 P97 R 6 P96 R 5 P95 R 4 P94 R 3 P93 R 2 P92 R 1 P91 R 0 P90 R When this register is read the bit that is set in P9DDR is read as the value of P9DR The bit that is cleared in P9DDR is re...

Page 229: ...in 3 CS2E 0 R W CS2 Output Enable Selects to enable or disable the CS2 output 0 P91 is designated as I O port 1 P91 is designated as CS2 output pin 2 CS1E 0 R W CS1 Output Enable Selects to enable or disable the CS1 output 0 P92 is designated as I O port 1 P92 is designated as CS1 output pin 1 LWROE 0 R W LWR Output Enable Selects to enable or disable the LWR output 0 P90 is designated as I O port...

Page 230: ... the IOD3 to IOD0 bits in TIORL_0 and the CCLR2 to CCLR0 bits in TCR_0 and the combination of the TPSC2 to TPSC0 bits in TCR_0 to TCR_2 the TIOCD0 TCLKBS bit and the P97DDR bit the pin function is switched as shown below Extended Mode EXPE 1 WMS11 WMS21 WMS31 All 0 At least one bit is set to 1 TIOCD0 TCLKBS 0 0 1 TPU channel 0 setting Table below 2 Table below 1 P97DDR WAIT input pin ExTIOCD0 inpu...

Page 231: ...101 this pin functions as the TCLKB input pin When TIOCB1 TCLKCS 1 and phase count mode is set to the TCR channel 1 this pin functions as the TCLKB input pin P96 φ According to the setting of the P96DDR bit the pin function is switched as shown below P96DDR 0 1 Pin function P96 input pin φ output pin P95 AS AH According to the operating mode and combination of the ASOE bit and the P95DDR bit the p...

Page 232: ...P93 output pin P92 CS1 ExTIOCB2 ExTCLKD When the TIOCB2 TCLKDS bit in PTCNT2 is set to 1 this pin can be used as the ExTIOCB2 ExTCLKD2 pin According to operating modes the TPU channel 2 settings by the CS1E bit the MD3 to MD0 bits in TMDR_2 the IOB3 to IOB0 bits in TIOR_2 and the CCLR1 and CCLR0 bits in TCR_2 and the combination of the TPSC2 to TPSC0 bits in TCR_0 the TIOCB2 TCLKDS bit and the P92...

Page 233: ...tput Legend x Don t care Notes 1 When TIOCB2 TCLKDS 1 MD3 to MD0 B 0000 or B 01xx and IOB3 1 this pin functions as the TIOCB2 input pin 2 When TIOCB2 TCLKDS 1 and TPSC2 to TPSC0 in TCR_0 B 111 this pin functions as the TCLKD input pin When TIOCB2 TCLKDS 1 and phase count mode is set to the TCR channel 2 this pin functions as the TCLKD input pin P91 CS2 ExTIOCA2 When the TIOCA2S bit in PTCNT2 is se...

Page 234: ...1 B 0101 to B 0111 B xx00 Other than B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 01 B 01 Output function Output compare output PWM mode 1 output 2 PWM mode 2 output Legend x Don t care Notes 1 When TIOCA2S 1 MD3 to MD0 B 0000 or B 01xx and IOA3 1 this pin functions as the TIOCA2 input pin 2 Output is disabled for TIOCB2 P90 LWR ExTIOCB1 ExTCLKC When the TIOCB1 TCLKCS bit in PTCNT2 is set to ...

Page 235: ... pin P90 output pin ExTCLKC input pin 2 TPU channel 1 setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 01xx B 0010 B 0011 IOB3 to IOB0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 10 B 10 Output function Output compare output PWM mode 2 output Legend x Don t care Notes 1 When TIOCB1 TCLKCS 1 MD3 to MD0 B 0000 or B 01xx and IOB3 to IOB0 B 10xx this...

Page 236: ...Port A data direction register PADDR Port A data register PADR Port A register PORTA Port function control register PFCR 7 11 1 Port A Data Direction Register PADDR The individual bits in PADDR specify input or output for the pins of port A The read value is undefined Bit Bit Name Initial Value R W Description 7 PA7DDR 0 W 6 PA6DDR 0 W 5 PA5DDR 0 W 4 PA4DDR 0 W 3 PA3DDR 0 W 2 PA2DDR 0 W 1 PA1DDR 0...

Page 237: ...ores output data for the port A pins that are used as the general output ports 7 11 3 Port A Register PORTA PORTA reflects the pin state in port A and cannot be modified Bit Bit Name Initial Value R W Description 7 PA7 R 6 PA6 R 5 PA5 R 4 PA4 R 3 PA3 R 2 PA2 R 1 PA1 R 0 PA0 R When this register is read the bit that is set in PADDR is read as the value of PADR The bit that is cleared in PADDR is re...

Page 238: ...t in PFCR the MD3 to MD0 bits in TMDR_1 the IOA3 to IOA0 bits in TIOR_1 and the CCLR1 and CCLR0 bits in TCR_1 and the combination of the TIOCA1S bit and the PA7DDR bit the pin function is switched as shown below Extended Mode EXPE 1 CS3E 0 1 TIOCA1S 0 1 TPU channel 1 setting Table below 2 Table below 1 PA7DDR CS3 output pin Pin function Single chip operation CS3 output pin ExTIOCA1 input pin 1 CS3...

Page 239: ...hed as shown below When the CKS1 and CKS0 bits in TCR of the FRT_0 are all set to 1 this pin functions as the FTCI_0 input pin When the SIMOD1 and SIMOD0 bits IHI signal in TCONRI of the timer connection_0 are cleared to B 00 this pin functions as the HFBACKI input pin PA6DDR 0 1 PA6 input pin PA6 output pin FTCI_0 input pin Pin function HFBACKI input pin PA5 FTIB_0 VFBACKI According to the settin...

Page 240: ...1 Pin function PA3 input pin PA3 output pin FTOB_0 output pin CBLANK output pin PA2 TMO0_0 ExTIOCC0 ExTCLKA When the TIOCC0 TCLKAS bit in PTCNT2 is set to 1 this pin can be used as the ExTIOCC0 ExTCLKA pin According to the TPU channel 0 settings by the OS3 to OS0 bits in TCSR of the TMR0_0 the MD3 to MD0 bits in TMDR_0 the IOC3 to IOC0 bits in TIORL_0 and the CCLR2 to CCLR0 bits in TCR_0 and the c...

Page 241: ...CLKAS 1 and phase count mode is set to the TCR channel 1 this pin functions as the TCLKA input pin 3 Output is disabled for TIOCD0 When BFA 1 or BFB 1 in TMDR0 output is disabled and the setting is the same as 2 PA1 TMOY_0 ExPW7 SCK4 When the PW7S bit in PTCNT0 is set to 1 this pin can be used as the ExPW7 pin According to the combination of the C A bit in SMR of the SCI_4 the CKE0 and CKE1 bits i...

Page 242: ...nd CKE1 bits in SCR the OS3 to OS0 bits in TCSR of the TMRX_0 the OE6 bit in PWOER of the PWM the PW6S bit and the PA0DDR bit the pin function is switched as shown below CKE1 0 1 C A 0 1 CKE0 0 1 OS3 to OS0 All 0 At least one bit is set to 1 PA0DDR 0 1 PW6S 0 1 OE6 0 1 Pin function PA0 input pin PA0 output pin PA0 output pin PW6 output pin TMOX_0 output pin SCK3 output pin SCK3 output pin SCK3 inp...

Page 243: ...ta register PBDR Port B register PORTB 7 12 1 Port B Data Direction Register PBDDR The individual bits in PBDDR specify input or output for the pins of port B The read value is undefined Bit Bit Name Initial Value R W Description 7 PB7DDR 0 W 6 PB6DDR 0 W 5 PB5DDR 0 W 4 PB4DDR 0 W 3 PB3DDR 0 W 2 PB2DDR 0 W 1 PB1DDR 0 W 0 PB0DDR 0 W While a general I O port function is selected the corresponding po...

Page 244: ...ores output data for the port B pins that are used as the general output ports 7 12 3 Port B Register PORTB PORTB reflects the pin state in port B and cannot be modified Bit Bit Name Initial Value R W Description 7 PB7 R 6 PB6 R 5 PB5 R 4 PB4 R 3 PB3 R 2 PB2 R 1 PB1 R 0 PB0 R When this register is read the bit that is set in PBDDR is read as the value of PBDR The bit that is cleared in PBDDR is re...

Page 245: ...NCI_0 input pin PB6 FTIA_0 VSYNCI_0 According to the setting of the PB6DDR bit the pin function is switched as shown below When the ICIAE bit in TIER of the FRT_0 is set to 1 this pin functions as the FTIA_0 input pin When the SIMOD1 and SIMOD0 bits IVI signal in TCONRI of the timer connection_0 are all set to 1 this pin functions as the VSYNCI_0 input pin PB6DDR 0 1 PB6 input pin PB6 output pin F...

Page 246: ...e setting of the PB3DDR bit the pin function is switched as shown below When the ICIAE bit in TIER of the FRT_1 is set to 1 this pin functions as the FTIA_1 input pin When the SIMOD1 and SIMOD0 bits IVI signal in TCONRI of the timer connection_1 are all set to 1 this pin functions as the VSYNCI_1 input pin PB3DDR 0 1 PB3 input pin PB3 output pin FTIA_1 input pin Pin function VSYNCI_1 input pin PB2...

Page 247: ... 0 1 OS3 to OS0 All 0 At least one bit is set to 1 PB1DDR 0 1 Pin function PB1 input pin PB1 output pin TMO1_0 output pin HSYNCO output pin PB0 FTOA_0 VSYNCO According to the combination of the VOE bit in TCONRO of the timer connection_0 the OEA bit in TOCR of the FRT_0 and the PB0DDR bit the pin function is switched as shown below VOE 0 1 OEA 0 1 PB0DDR 0 1 Pin function PB0 input pin PB0 output p...

Page 248: ... PCDDR specify input or output for the pins of port C The read value is undefined Bit Bit Name Initial Value R W Description 7 to 4 All 0 W Reserved These bits cannot be modified 3 PC3DDR 0 W 2 PC2DDR 0 W 1 PC1DDR 0 W 0 PC0DDR 0 W While a general I O port function is selected the corresponding port C pin is an output port when a PCDDR bit is set to 1 and an input port when cleared to 0 7 13 2 Port...

Page 249: ...ons The relationship between register setting values and pin functions is as follows PC7 ETDO Pin function PC7 input pin Note When the on chip emulator is used this pin functions as the ETDO output pin When the on chip emulator is not used normal operation a high or low level signal should be input to this pin PC6 ETDI Pin function PC6 input pin Note When the on chip emulator is used this pin func...

Page 250: ...pin SDA3 I O pin PC2 SCL3 The pin function is switched as shown below according to the combination of the ICE bit in ICCRA of the IIC3_3 and the PC2DDR bit When this pin is used as the PC2 output pin the output format is NMOS push pull output The output format for SCL3 is NMOS open drain output and direct bus drive is possible ICE 0 1 PC2DDR 0 1 Pin function PC2 input pin PC2 output pin SCL3 I O p...

Page 251: ...ation of the ICE bit in ICCRA of the IIC3_2 and the PC0DDR bit When this pin is used as the PC0 output pin the output format is NMOS push pull output The output format for SCL2 is NMOS open drain output and direct bus drive is possible ICE 0 1 PC0DDR 0 1 Pin function PC0 input pin PC0 output pin SCL2 I O pin ...

Page 252: ...or the 8 bit PWM timer 0 P17 PW7 is selected 1 PA1 ExPW7 is selected 6 PW6S 0 R W Selects the PW6 output pin for the 8 bit PWM timer 0 P16 PW6 is selected 1 PA0 ExPW6 is selected 5 PW5S 0 R W Selects the PW5 output pin for the 8 bit PWM timer 0 P15 PW5 is selected 1 P57 ExPW5 is selected 4 PW4S 0 R W Selects the PW4 output pin for the 8 bit PWM timer 0 P14 PW4 is selected 1 P56 ExPW4 is selected 3...

Page 253: ... is selected 5 IRQ5S 0 R W Selects the IRQ5 input pin 0 P45 IRQ5 is selected 1 P05 ExIRQ5 is selected 4 IRQ4S 0 R W Selects the IRQ4 input pin 0 P44 IRQ4 is selected 1 P04 ExIRQ4 is selected 3 IRQ3S 0 R W Selects the IRQ3 input pin 0 P43 IRQ3 is selected 1 P33 ExIRQ3 is selected 2 IRQ2S 0 R W Selects the IRQ2 input pin 0 P42 IRQ2 is selected 1 P32 ExIRQ2 is selected 1 IRQ1S 0 R W Selects the IRQ1 ...

Page 254: ...for the TPU 0 P25 TIOCB1 TCLKC is selected 1 P90 ExTIOCB1 ExTCLKC is selected 4 TIOCA1S 0 R W Selects the TIOCA1 I O pin for the TPU 0 P24 TIOCA1 is selected 1 PA7 ExTIOCA1 is selected 3 TIOCD0 TCLKBS 0 R W Selects the TIOCD0 TCLKB I O pin for the TPU 0 P23 TIOCD0 TCLKB is selected 1 P97 ExTIOCD0 ExTCLKB is selected 2 TIOCC0 TCLKAS 0 R W Selects the TIOCC0 TCLKA I O pin for the TPU 0 P22 TIOCC0 TC...

Page 255: ...disable control Figure 8 1 shows a block diagram of the PWM timer P10 PW0 P11 PW1 P12 PW2 P13 PW3 P14 PW4 P15 PW5 P16 PW6 P17 PW7 Comparator 0 Comparator 1 Comparator 2 Comparator 3 Comparator 4 Comparator 5 Comparator 6 Comparator 7 PWDR0 PWDR1 PWDR2 PWDR3 PWDR4 PWDR5 PWDR6 PWDR7 PWSL φ φ 8 PTCNT0 PWDPR PWOER P1DDR P1DR Legend PWSL PWDR PWDPR PWOER PCSR P1DDR P1DR PTCNT0 PWM register select PWM d...

Page 256: ...Symbol I O Function PWM output pins 7 to 0 PW7 to PW0 Output PWM timer pulse output 7 to 0 8 3 Register Descriptions The PWM has the following registers PWM register select PWSL PWM data registers 7 to 0 PWDR7 to PWDR0 PWM data polarity register PWDPR PWM output enable register PWOER Peripheral clock select register PCSR ...

Page 257: ...tions Resolution minimum pulse width 1 internal clock frequency PWM conversion period resolution 256 Carrier frequency 16 PWM conversion period With the 20 MHz system clock φ the resolution PWM conversion period and carrier frequency are as shown in table 8 3 5 1 R Reserved This bit is always read as 1 and cannot be modified 4 0 R Reserved This bit is always read as 0 and cannot be modified 3 0 R ...

Page 258: ...56 3 kHz φ 16 800 ns 204 8 µs 78 13 kHz 8 3 2 PWM Data Registers 7 to 0 PWDR7 to PWDR0 PWDR are 8 bit readable writable registers The PWM has eight PWM data registers Each PWDR specifies the duty cycle of the basic pulse to be output and the number of additional pulses The value set in PWDR corresponds to the 0 1 ratio in the conversion period The upper four bits specify the duty cycle of the basi...

Page 259: ...OE4 OE3 OE2 OE1 OE0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Output Enable 7 to 0 These bits together with P1DDR specify the P1n PWn pin state Bits OE7 to OE0 correspond to outputs PW7 to PW0 P1nDDR OEn Pin state 0x Port input 10 Port output or PWM 256 256 output 11 PWM output 0 to 255 256 output Legend n 7 to 0 x Don t care To perform PWM 256 256 output when DDR 1 and OE 0 the correspondin...

Page 260: ...on 7 6 5 PWCKXC PWCKXB PWCKXA 0 0 0 R W R W R W See section 9 3 4 Peripheral Clock Select Register PCSR 4 to 2 All 0 R W Reserved The initial value should not be changed 1 0 PWCKB PWCKA 0 0 R W R W PWM Clock Select B A Together with bits PWCKE and PWCKS in PWSL these bits select the internal clock input to TCNT of the PWM For details see table 8 2 ...

Page 261: ...esolution of 1 16 Table 8 4 shows the duty cycles of the basic pulse Table 8 4 Duty Cycle of Basic Pulse 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Upper 4 Bits Basic Pulse Waveform Internal B 0 0 0 0 B 0 0 0 1 B 0 0 1 0 B 0 0 1 1 B 0 1 0 0 B 0 1 0 1 B 0 1 1 0 B 0 1 1 1 B 1 0 0 0 B 1 0 0 1 B 1 0 1 0 B 1 0 1 1 B 1 1 0 0 B 1 1 0 1 B 1 1 1 0 B 1 1 1 1 ...

Page 262: ... Pulse No Lower 4 Bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0000 0001 Yes 0010 Yes Yes 0011 Yes Yes Yes 0100 Yes Yes Yes Yes 0101 Yes Yes Yes Yes Yes 0110 Yes Yes Yes Yes Yes Yes 0111 Yes Yes Yes Yes Yes Yes Yes 1000 Yes Yes Yes Yes Yes Yes Yes Yes 1001 Yes Yes Yes Yes Yes Yes Yes Yes Yes 1010 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1011 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 1100 Yes Yes Ye...

Page 263: ...256 where T is the resolution Sixteen operating clocks by combination of eight resolution settings and two base cycle settings Figure 9 1 shows a block diagram of the PWMX D A module Select clock Bus interface Clock Internal data bus Comparator A Comparator B DADRA DADRB PWX1 Internal clock φ φ 2 φ 64 φ 128 φ 256 φ 1024 φ 4096 φ 16384 PWX0 Fine adjustment pulse addition A Fine adjustment pulse add...

Page 264: ...put pin 1 PWX1 Output PWM output of PWMX channel B 9 3 Register Descriptions The PWMX D A has the following registers PWMX D A counters H and L DACNTH and DACNTL PWMX D A data register A DADRA PWMX D A data register B DADRB PWMX D A control register DACR Peripheral clock select register PCSR Note The same addresses are shared by DADRA and DACR and by DADRB and DACNT Switching is performed by the R...

Page 265: ...its DACNT should always be accessed in 16 bit units For details see section 9 4 Bus Master Interface DACNTH Bit Bit Name Initial Value R W Description 7 to 0 UC7 to UC0 All 0 R W Lower Up Counter DACNTL Bit Bit Name Initial Value R W Description 7 to 2 UC8 to UC13 All 0 R W Upper Up Counter 1 1 R W Reserved This bit is always read as 1 and cannot be modified 0 REGS 1 R W Register Select DADRA and ...

Page 266: ...nalog value In each base cycle the DACNT value is continually compared with the DADR value to determine the duty cycle of the output waveform and to decide whether to output a fine adjustment pulse equal in width to the resolution To enable this operation this register must be set within a range that depends on the CFS bit If the DADR value is outside this range the PWM output is fixed A channel c...

Page 267: ...e this operation this register must be set within a range that depends on the CFS bit If the DADR value is outside this range the PWM output is fixed A channel can be operated with 12 bit accuracy by fixing DA0 and DA1 to 0 The lower two data bits are not compared with UC12 and UC13 in DACNT 1 CFS 1 R W Carrier Frequency Select 0 Base cycle resolution T 64 The range of DA13 to DA0 H 0100 to H 3FFF...

Page 268: ...channel B 0 PWMX D A channel B output at the PWX1 output pin is disabled 1 PWMX D A channel B output at the PWX1 output pin is enabled 2 OEA 0 R W Output Enable A Enables or disables output on PWMX D A channel A 0 PWMX D A channel A output at the PWX0 output pin is disabled 1 PWMX D A channel A output at the PWX0 output pin is enabled 1 OS 0 R W Output Select Selects the phase of the PWMX D A outp...

Page 269: ...stem clock cycle tcyc x 128 0 1 1 Operates on the system clock cycle tcyc x 256 1 0 0 Operates on the system clock cycle tcyc x 1024 1 0 1 Operates on the system clock cycle tcyc x 4096 1 1 0 Operates on the system clock cycle tcyc x 16384 1 1 1 Setting prohibited 9 4 Bus Master Interface DACNT DADRA and DADRB are 16 bit registers The data bus linking the bus master and the on chip peripheral modu...

Page 270: ...ower byte Correct data will not be transferred if only the upper byte or only the lower byte is accessed Also note that a bit manipulation instruction cannot be used to access these registers Example 1 Write to DACNT MOV W R0 DACNT Write R0 contents to DACNT Example 2 Read DADRA MOV W DADRA R0 Copy contents of DADRA to R0 Table 9 3 Access Method for Reading Writing 16 Bit Registers Read Write Regi...

Page 271: ...nds to the total width TH of the high 1 output pulses Figures 9 3 and 9 4 show the types of output waveform tf tL T Resolution TL Σ tLn OS 0 When CFS 0 m 256 When CFS 1 m 64 m n 1 1 conversion cycle T 214 16384 Base cycle T 64 or T 256 Figure 9 2 PWMX D A Operation Table 9 4 summarizes the relationships between the CKS and CFS bit settings and the resolution base cycle and conversion cycle The PWM...

Page 272: ...00 to H 3FFF 10 0 0 0 0 51 2 1 12 8 819 2 14 819 2 12 0 0 204 8 Always low high output DA13 to DA0 H 0000 to H 003F Data value T DA13 to DA0 H 0040 to H 3FFF 10 0 0 0 0 51 2 1 0 1 0 6 4 1638 4 14 1638 4 12 0 0 409 6 Always low high output DA13 to DA0 H 0000 to H 00FF Data value T DA13 to DA0 H 0100 to H 3FFF 10 0 0 0 0 102 4 1 25 6 1638 4 14 1638 4 12 0 0 409 6 Always low high output DA13 to DA0 H...

Page 273: ... tf1 tf2 tf3 tf255 tf256 T 64 tL1 tL2 tL3 tL255 tL256 TL tf1 tf2 tf63 tf64 tL1 tL2 tL3 tL63 tL64 1 conversion cycle tf1 tf2 tf3 tf63 tf64 T 256 tL1 tL2 tL3 tL63 tL64 TL a CFS 0 base cycle resolution T 64 b CFS 1 base cycle resolution T 256 Figure 9 3 Output Waveform OS 0 DADR Corresponds to TL ...

Page 274: ... the base pulse while the subsequent six bits DA5 to DA0 determine the locations of the additional pulses as shown in figure 9 5 Table 9 5 lists the locations of the additional pulses DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS 1 1 Duty cycle of base pulse Location of additional pulses Figure 9 5 D A Data Register Configuration when CFS 1 In this example DADR H 0207 B 0000 0010...

Page 275: ...se cycle Base cycle No 1 No 0 No 63 Additional pulse output location Figure 9 6 Output Waveform when DADR H 0207 OS 1 However when CFS 0 base cycle resolution T 64 the duty cycle of the base pulse is determined by the upper six bits and the locations of the additional pulses by the subsequent eight bits with a method similar to as above ...

Page 276: ...1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 1...

Page 277: ...ms can be output Four independent input captures The rising or falling edge can be selected Buffer modes can be specified Counter clearing The free running counters can be cleared on compare match A Fourteen independent interrupts Two compare match interrupts four input capture interrupts and one overflow interrupt can be requested independently for each channel Special functions provided by autom...

Page 278: ...egend OCRA OCRB OCRAR OCRAF OCRDM FRC ICRA to ICRD TCSR TIER TCR TOCR Output compare registers A B 16 bit Output compare registers AR AF 16 bit Output compare register DM 16 bit Free running counter 16 bit Input capture registers A to D 16 bit Timer control status register 8 bit Timer interrupt enable register 8 bit Timer control register 8 bit Timer output compare control register 8 bit OCIA OCIB...

Page 279: ...ompare A output pin FTOA_1 Output Output compare A output Output compare B output pin FTOB_1 Output Output compare B output Input capture A input pin FTIA_1 Input Input capture A input Input capture B input pin FTIB_1 Input Input capture B input Input capture C input pin FTIC_1 Input Input capture C input Input capture D input pin FTID_1 Input Input capture D input Note Channels 0 and 1 are omitte...

Page 280: ... the OCR and FRC values match the output level selected by the OLVLA or OLVLB bit in TOCR is output at the output compare output pin FTOA or FTOB Following a reset the FTOA and FTOB output levels are 0 until the first compare match OCR should always be accessed in 16 bit units cannot be accessed in 8 bit units OCR is initialized to H FFFF 10 3 3 Input Capture Registers A to D ICRA to ICRD The FRT ...

Page 281: ...are match A following addition of OCRAF while 0 is output on a compare match A following addition of OCRAR When using the OCRA automatic addition function do not select internal clock φ 2 as the FRC input clock together with a set value of H 0001 or less for OCRAR or OCRAF OCRAR and OCRAF should always be accessed in 16 bit units cannot be accessed in 8 bit units OCRAR and OCRAF are initialized to...

Page 282: ...B requested by ICFB is disabled 1 ICIB requested by ICFB is enabled 5 ICICE 0 R W Input Capture Interrupt C Enable Selects whether to enable an interrupt request ICIC by the ICFC flag when the ICFC flag in TCSR is set to 1 0 ICIC requested by ICFC is disabled 1 ICIC requested by ICFC is enabled 4 ICIDE 0 R W Input Capture Interrupt D Enable Selects whether to enable an interrupt request ICID by th...

Page 283: ... OVF is enabled 0 0 R Reserved This bit is always read as 1 and cannot be modified 10 3 7 Timer Control Status Register TCSR TCSR selects whether the counter operates or not and controls interrupt request signals Bit Bit Name Initial Value R W Description 7 ICFA 0 R W Input Capture Flag A This status flag indicates that the FRC value has been transferred to ICRA by means of an input capture signal...

Page 284: ...When BUFEA 1 on occurrence of an input capture signal specified by the IEDGC bit at the FTIC input pin ICFC is set but data is not transferred to ICRC In buffer operation ICFC can be used as an external interrupt signal by setting the ICICE bit to 1 Setting condition When an input capture signal occurs Clearing condition Read ICFC when ICFC 1 then write 0 to ICFC 4 ICFD 0 R W Input Capture Flag D ...

Page 285: ... matches the OCRB value Setting condition When FRC OCRB Clearing condition Read OCFB when OCFB 1 then write 0 to OCFB 1 OVF 0 R W Overflow Flag This status flag indicates that the FRC has overflowed Setting condition When FRC overflows changes from H FFFF to H 0000 Clearing condition Read OVF when OVF 1 then write 0 to OVF 0 CCLRA 0 R W Counter Clear A Selects whether FRC is to be cleared at compa...

Page 286: ...ture on the rising edge of FTIB 5 IEDGC 0 R W Input Edge Select C Selects the rising or falling edge of the input capture C signal FTIC 0 Capture on the falling edge of FTIC 1 Capture on the rising edge of FTIC 4 IEDGD 0 R W Input Edge Select D Selects the rising or falling edge of the input capture D signal FTID 0 Capture on the falling edge of FTID 1 Capture on the rising edge of FTID 3 BUFEA 0 ...

Page 287: ...S 0 R W Input Capture D Mode Select Specifies whether ICRD is used in normal operating mode or in operating mode using OCRDM 0 Normal operating mode is specified for ICRD 1 Operating mode using OCRDM is specified for ICRD 6 OCRAMS 0 R W Output Compare A Mode Select Specifies whether OCRA is used in normal operating mode or in operating mode using OCRAR and OCRAF 0 Normal operating mode is specifie...

Page 288: ... Enable B Enables or disables output of the output compare B output pin FTOB 0 Output compare B output is disabled 1 Output compare B output is enabled 1 OLVLA 0 R W Output Level A Selects the level to be output at the output compare A output pin FTOA in response to compare match A signal indicating a match between the FRC and OCRA values When the OCRAMS bit is 1 this bit is ignored 0 0 is output ...

Page 289: ...hows an example of 50 duty pulses output with an arbitrary phase difference When a compare match occurs while the CCLRA bit in TCSR is set to 1 the OLVLA and OLVLB bits are inverted by software H FFFF OCRA OCRB H 0000 FTOA FTOB Counter clear FRC Figure 10 2 Example of Pulse Output ...

Page 290: ...rnal clock source The pulse width of the external clock signal must be at least 1 5 system clocks φ The counter will not increment correctly if the pulse width is shorter than 1 5 system clocks φ φ Internal clock FRC input clock FRC N 1 N 1 N Figure 10 3 Increment Timing with Internal Clock Source φ External clock input pin FRC input clock FRC N 1 N Figure 10 4 Increment Timing with External Clock...

Page 291: ...put compare output pin FTOA or FTOB Figure 10 5 shows the timing of this operation for compare match A φ FRC OCRA N N N 1 N 1 N N Compare match A signal OLVLA Output compare A output pin FTOA Clear Note Indicates instruction execution by software Figure 10 5 Timing of Output Compare A Output 10 5 3 FRC Clear Timing FRC can be cleared when compare match A occurs Figure 10 6 shows the timing of this...

Page 292: ... selected φ Input capture input pin Input capture signal Figure 10 7 Timing of Input Capture Input Signal Usual Case If the corresponding input capture signal is input when ICRA to ICRD are read the input capture signal is delayed by one system clock φ Figure 10 8 shows the timing for this case T1 T2 Read cycle of ICRA to ICRD φ Input capture input pin Input capture signal Figure 10 8 Timing of In...

Page 293: ...e Timing Even when ICRC or ICRD is used as a buffer register its input capture flag is set according to the selected edge of its input capture signal For example if ICRC is used as the ICRA buffer register when the edge transition selected by the IEDGC bit occurs on the FTIC input capture line the ICFC flag will be set and if the ICICE bit is set at this time an interrupt will be requested The FRC...

Page 294: ...tting The input capture flag ICFA ICFB ICFC or ICFD is set to 1 by the input capture signal The FRC value is simultaneously transferred to the corresponding input capture register ICRA ICRB ICRC or ICRD Figure 10 11 shows the timing of setting the ICFA to ICFD flags Input capture signal φ ICFA to ICFD ICRA to ICRD FRC N N Figure 10 11 Timing of Input Capture Flags ICFA to ICFD Setting ...

Page 295: ...he FRC and OCRA or OCRB values match the compare match signal is not generated until the next cycle of the clock source Figure 10 12 shows the timing of setting the OCFA or OCFB flag Compare match signal OCFA OCFB OCRA OCRB N FRC N N 1 φ Figure 10 12 Timing of Output Compare Flag OCFA or OCFB Setting 10 5 8 Timing of Overflow Flag Setting The OVF flag is set to 1 when FRC overflows changes from H ...

Page 296: ...n Timing 10 5 10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H 0000 a signal that masks the ICRD input capture signal is generated The mask signal is set by the input capture signal The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents and an FRC compare match Figure 10 15 shows the timing of setti...

Page 297: ...Rev 1 00 09 03 page 259 of 704 Compare match signal Input capture mask signal ICRD OCRDM 2 N FRC N N 1 φ Figure 10 16 Timing of Input Capture Mask Signal Clearing ...

Page 298: ...FRT Interrupt Sources Channel Interrupt Interrupt Source Interrupt Flag Priority 0 ICIA_0 Input capture of ICRA ICFA High ICIB_0 Input capture of ICRB ICFB ICIC_0 Input capture of ICRC ICFC ICID_0 Input capture of ICRD ICFD OCIA_0 Compare match of OCRA OCFA OCIB_0 Compare match of OCRB OCFB FOV_0 Overflow of FRC OVF 1 ICIA_1 Input capture of ICRA ICFA ICIB_1 Input capture of ICRB ICFB ICIC_1 Input...

Page 299: ... signal is generated during the state after an FRC write cycle the clear signal takes priority and the write is not performed Figure 10 17 shows the timing for this type of conflict φ Address FRC address Internal write signal Counter clear signal FRC N H 0000 T1 T2 Write cycle of FRC Figure 10 17 FRC Write Clear Conflict ...

Page 300: ...s generated during the state after an FRC write cycle the write takes priority and FRC is not incremented Figure 10 18 shows the timing for this type of conflict φ Address FRC address Internal write signal FRC input clock Write data FRC N M T1 T2 Write cycle of FRC Figure 10 18 FRC Write Increment Conflict ...

Page 301: ...ected and a compare match occurs in the cycle following the OCRA OCRAR and OCRAF write cycle the OCRA OCRAR and OCRAF write takes priority and the compare match signal is disabled Consequently the result of the automatic addition is not written to OCRA Figure 10 20 shows the timing for this type of conflict φ Address OCR address Internal write signal Compare match signal FRC Write data Disabled OC...

Page 302: ...eover may cause FRC to be incremented This depends on the timing at which the clock is switched bits CKS1 and CKS0 are rewritten Table 10 3 shows the relationship between the timing and the FRC operation When an internal clock is used the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock φ If the clock is changed when the old source is high ...

Page 303: ...eration 1 Switching from low to low Clock before switchover Clock after switchover FRC clock FRC CKS bit rewrite N N 1 2 Switching from low to high Clock before switchover Clock after switchover FRC clock FRC N N 1 N 2 CKS bit rewrite 3 Switching from high to low Clock before switchover Clock after switchover FRC clock FRC CKS bit rewrite N N 2 N 1 ...

Page 304: ...er by Means of CKS1 and CKS0 Bits FRC Operation 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N 1 CKS bit rewrite N 2 Note Generated on the assumption that the switchover is a falling edge FRC is incremented ...

Page 305: ...ays to clear the counters The counters can be cleared on compare match A or compare match B or by an external reset signal Timer output controlled by two compare match signals The timer output signal in each channel is controlled by two independent compare match signals enabling the timer to be used for various applications such as the generation of pulse output or PWM output with an arbitrary dut...

Page 306: ...A1 Comparator A1 TCNT1 Comparator B1 TCORB1 TCSR1 TCR1 TMCI0 TMCI1 TCNT0 Overflow 1 Overflow 0 Compare match B1 Compare match B0 TMO1 TMRI1 Select clock Control logic Internal bus Legend Interrupt signals Clear 0 TMR1 φ 2 φ 8 φ 64 TCORA0 Time constant register A0 TCORB0 Time constant register B0 TCNT0 Timer counter 0 TCSR0 Timer control status register 0 TCR0 Timer control register 0 TCORA1 Time c...

Page 307: ...l bus Legend Interrupt signals Clear Y TMRX φ φ 2 φ 4 TMRY φ 4 φ 256 φ 2048 CMIAX CMIBX OVIX CMIAY CMIBY OVIY ICIX TCORAY Time constant register AY TCORBY Time constant register BY TCNTY Timer counter Y TCSRY Timer control status register Y TCRY Timer control register Y TISR Timer input select register TCORAX Time constant register AX TCORBX Time constant register BX TCNTX Timer counter X TCSRX Ti...

Page 308: ...e counter TMR1 Timer output TMO1_0 Output Output controlled by compare match Timer clock reset input TMI1_0 ExTMI1_0 Input External clock input TMCI1 external reset input TMRI1 for the counter TMRY Timer output TMOY_0 Output Output controlled by compare match Timer clock reset input TMIY_0 ExTMIY_0 Input External clock input TMCIY external reset input TMRIY for the counter TMRX Timer output TMOX_0...

Page 309: ...put TMCIY external reset input TMRIY for the counter TMRX Timer output TMOX_1 Output Output controlled by compare match Timer clock reset input TMIX_1 ExTMIX_1 Input External clock input TMCIX external reset input TMRIX for the counter 11 3 Register Descriptions The TMR has the following registers For details on the timer extended control register see section 13 3 5 Timer Extended Control Register...

Page 310: ...trol status register X_0 TCSRX_0 Input capture register_0 TICR_0 Time constant register_0 TCORC_0 Input capture register R_0 TICRR_0 Input capture register F_0 TICRF_0 TMR0_1 Timer counter 0_1 TCNT0_1 Time constant register A0_1 TCORA0_1 Time constant register B0_1 TCORB0_1 Timer control register 0_1 TCR0_1 Timer control status register 0_1 TCSR0_1 TMR1_1 Timer counter 1_1 TCNT1_1 Time constant re...

Page 311: ... signal The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR When TCNT overflows changes from H FF to H 00 the OVF bit in TCSR is set to 1 TCNT is initialized to H 00 11 3 2 Time Constant Register A TCORA TCORA is an 8 bit readable writable register TCORA0 and TCORA1 or TCORAY and TCORAX comprise a single 16 bit register so they can be accessed together in word units TCORA is ...

Page 312: ...CMIEA 0 R W Compare Match Interrupt Enable A Selects whether the CMFA interrupt request CMIA is enabled or disabled when the CMFA flag in TCSR is set to 1 0 CMFA interrupt request CMIA is disabled 1 CMFA interrupt request CMIA is enabled 5 OVIE 0 R W Timer Overflow Interrupt Enable Selects whether the OVF interrupt request OVI is enabled or disabled when the OVF flag in TCSR is set to 1 0 OVF inte...

Page 313: ...ents at falling edge of internal clock φ 256 TMR0 1 0 0 Increments at overflow signal from TCNT1 0 0 0 Disables clock input 0 0 1 0 Increments at falling edge of internal clock φ 8 0 0 1 1 Increments at falling edge of internal clock φ 2 0 1 0 0 Increments at falling edge of internal clock φ 64 0 1 0 1 Increments at falling edge of internal clock φ 128 0 1 1 0 Increments at falling edge of interna...

Page 314: ...rom TCNTY Common 1 0 1 Increments at rising edge of external clock 1 1 0 Increments at falling edge of external clock 1 1 1 Increments at both rising and falling edges of external clock Note If the TMR0 clock input is set as the TCNT1 overflow signal and the TMR1 clock input is set as the TCNT0 compare match signal simultaneously a count up clock cannot be generated Similarly If the TMRY clock inp...

Page 315: ...ing condition Read CMFA when CMFA 1 then write 0 to CMFA 5 OVF 0 R W 1 Timer Overflow Flag Setting condition When TCNT0 overflows from H FF to H 00 Clearing condition Read OVF when OVF 1 then write 0 to OVF 4 ADTE 0 R W A D Trigger Enable 2 Enables or disables A D conversion start requests by compare match A 0 A D converter start requests by compare match A are disabled 1 A D converter start reque...

Page 316: ...TCSR1 Bit Bit Name Initial Value R W Description 7 CMFB 0 R W Compare Match Flag B Setting condition When the values of TCNT1 and TCORB1 match Clearing condition Read CMFB when CMFB 1 then write 0 to CMFB 6 CMFA 0 R W Compare Match Flag A Setting condition When the values of TCNT1 and TCORA1 match Clearing condition Read CMFA when CMFA 1 then write 0 to CMFA 5 OVF 0 R W Timer Overflow Flag Setting...

Page 317: ...n output level is to be changed by compare match A of TCORA1 and TCNT1 00 No change 01 0 is output 10 1 is output 11 Output is inverted toggle output Note Only 0 can be written to clear the flag TCSRY Bit Bit Name Initial Value R W Description 7 CMFB 0 R W Compare Match Flag B Setting condition When the values of TCNTY and TCORBY match Clearing condition Read CMFB when CMFB 1 then write 0 to CMFB ...

Page 318: ... 0 ICF interrupt request ICIX is disabled 1 ICF interrupt request ICIX is enabled 3 2 OS3 OS2 0 0 R W R W Output Select 3 2 Specify how the TMOY pin output level is to be changed by compare match B of TCORBY and TCNTY 00 No change 01 0 is output 10 1 is output 11 Output is inverted toggle output 1 0 OS1 OS0 0 0 R W R W Output Select 1 0 Specify how the TMOY pin output level is to be changed by com...

Page 319: ...write 0 to CMFA 5 OVF 0 R W Timer Overflow Flag Setting condition When TCNTX overflows from H FF to H 00 Clearing condition Read OVF when OVF 1 then write 0 to OVF 4 ICF 0 R W Input Capture Flag Setting condition When a rising edge and falling edge is detected in the external reset signal in that order Clearing condition Read ICF when ICF 1 then write 0 to ICF 3 2 OS3 OS2 0 0 R W R W Output Select...

Page 320: ... directly accessed by the CPU 11 3 7 Time Constant Register TCORC TCORC is an 8 bit readable writable register The sum of contents of TCORC and TICR is always compared with TCNT When a match is detected a compare match C signal is generated However comparison at the T2 state of the TCORC write cycle and at the input capture cycle of TICR is disabled TCORC is initialized to H FF 11 3 8 Input Captur...

Page 321: ...r 0 IVG signal is selected 1 TMIY is selected 11 4 Operation 11 4 1 Pulse Output Figure 11 3 shows an example for outputting an arbitrary duty pulse 1 Clear the CCLR1 bit in TCR to 0 and then set the CCLR0 bit to 1 so that TCNT is cleared according to the compare match of TCORA 2 Set the OS3 to OS0 bits in TCSR to B 0110 so that 1 is output according to the compare match of TCORA and 0 is output a...

Page 322: ...e pulse width of the external clock signal must be at least 1 5 states for a single edge and at least 2 5 states for both edges The counter will not increment correctly if the pulse width is less than these values φ Internal clock TCNT input clock TCNT N 1 N N 1 Figure 11 4 Count Timing for Internal Clock Input φ External clock input pin TCNT input clock TCNT N 1 N N 1 Figure 11 5 Count Timing for...

Page 323: ...are match signal is not generated until the next TCNT input clock Figure 11 6 shows the timing of CMF flag setting φ TCNT N N 1 TCOR N Compare match signal CMF Figure 11 6 Timing of CMF Setting at Compare Match 11 5 3 Timing of Timer Output at Compare Match When a compare match signal occurs the timer output changes as specified by the OS3 to OS0 bits in TCSR Figure 11 7 shows the timing of timer ...

Page 324: ...Timing TCNT is cleared at the rising edge of an external reset input depending on the settings of the CCLR1 and CCLR0 bits in TCR The width of the clearing pulse must be at least 1 5 states Figure 11 9 shows the timing of clearing the counter by an external reset input φ Clear signal External reset input pin TCNT N H 00 N 1 Figure 11 9 Timing of Counter Clear by External Reset Input 11 5 6 Timing ...

Page 325: ...bits Setting of Compare Match Flags The CMF flag in TCSR0 is set to 1 when a 16 bit compare match occurs The CMF flag in TCSR1 is set to 1 when a lower 8 bit compare match occurs Counter Clear Specification If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare match the 16 bit counter TCNT0 and TCNT1 together is cleared when a 16 bit compare match occurs The 16 bit counter...

Page 326: ...n bits CKS2 to CKS0 in TCRY are set to B 100 the timer functions as a single 16 bit timer with TMRY occupying the upper eight bits and TMRX occupying the lower 8 bits Setting of Compare Match Flags The CMF flag in TCSRY is set to 1 when an upper 8 bit compare match occurs The CMF flag in TCSRX is set to 1 when a lower 8 bit compare match occurs Counter Clear Specification If the CCLR1 and CCLR0 bi...

Page 327: ... A narrow pulse width can be measured with TICRR and TICRF using a single capture If the falling edge of TMRIX TMRX input capture input signal is detected after its rising edge has been detected the value of TCNTX at that time is transferred to both TICRR and TICRF Input Timing of Input Capture Signal Figure 11 11 shows the timing of the input capture operation φ TMRIX Input capture signal TCNTX n...

Page 328: ...Rev 1 00 09 03 page 290 of 704 φ TMRIX TICRR TICRF read cycle T1 T2 Input capture signal Figure 11 12 Timing of Input Capture Signal When Input Capture Signal is Input during TICRR and TICRF Read ...

Page 329: ...are match CMFA High CMIBX0 TCORBX compare match CMFB OVIX0 TCNTX overflow OVF ICIX0 Input capture ICF TMR0 CMIA00 TCORA0 compare match CMFA CMIB00 TCORB0 compare match CMFB OVI00 TCNT0 overflow OVF TMR1 CMIA10 TCORA1 compare match CMFA CMIB10 TCORB1 compare match CMFB OVI10 TCNT1 overflow OVF TMRY CMIAY0 TCORAY compare match CMFA CMIBY0 TCORBY compare match CMFB OVIY0 TCNTY overflow OVF 1 TMRX CMI...

Page 330: ... If TCNT is cleared during the T2 state of a TCNT write cycle as shown in figure 11 13 the clear takes priority and TCNT is not written φ Address TCNT address Internal write signal Counter clear signal TCNT N H 00 T1 T2 TCNT write cycle by CPU Figure 11 13 Conflict between TCNT Write and Clear ...

Page 331: ...nerated during the T2 state of a TCNT write cycle as shown in figure 11 14 the write takes priority and the counter is not incremented φ Address TCNT address Internal write signal TCNT input clock TCNT N M T1 T2 TCNT write cycle by CPU Counter write data Figure 11 14 Conflict between TCNT Write and Increment ...

Page 332: ... to TCORC In this case also the input capture takes priority and the compare match signal is disabled φ Address TCOR address Internal write signal TCNT TCOR N M T1 T2 TCOR write cycle by CPU TCOR write data N N 1 Compare match signal Disabled Figure 11 15 Conflict between TCOR Write and Compare Match 11 9 4 Conflict between Compare Matches A and B If compare matches A and B occur at the same time ...

Page 333: ...is generated from an internal clock the falling edge of the internal clock pulse is detected If clock switching causes a change from high to low level as shown in no 3 in table 11 5 a TCNT clock pulse is generated on the assumption that the switchover is a falling edge and TCNT is incremented Erroneous incrementation can also happen when switching between internal and external clocks Table 11 5 Sw...

Page 334: ... N 2 3 Clock switching from high to low level 3 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit rewrite N N 1 N 2 4 4 Clock switching from high to high level Clock before switchover Clock after switchover TCNT clock TCNT CKS bit rewrite N N 1 N 2 Notes 1 Includes switching from low to stop and from stop to low 2 Includes switching from stop to high 3 Includes switching from ...

Page 335: ...nection If 16 bit count mode and compare match count mode are set simultaneously the input clock pulses for TCNT0 and TCNT1 or TCNTY and TCNTX are not generated and thus the counters will stop operating Simultaneous setting of these two modes should therefore be avoided ...

Page 336: ...Rev 1 00 09 03 page 298 of 704 ...

Page 337: ...put at compare match Input capture function Counter clear operation Synchronous operation Multiple timer counters TCNT can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input output possible by counter synchronous operation Maximum of 7 phase PWM output possible by combination with synchronous operation Buffer operation settabl...

Page 338: ...ster Timer mode register Timer I O control registers H L Timer interrupt enable register Timer status register Timer general registers A B C D TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 0 Channel 1 Channel 2 Internal data bus A D conversion start request signal Module data bus TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1B TCI1V TCI1U TGI2A TGI2B TCI2V TCI...

Page 339: ..._0 TGRA_1 TGRB_1 TGRA_2 TGRB_2 General registers buffer registers TGRC_0 TGRD_0 I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture 0 output O O O 1 output O O O Compare match output Toggle output O O O Input capture function O O O Synchronous operation O O O...

Page 340: ...apture Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4 sources Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow 4 sources Compare match or input capture 2A Compare match or input capture 2B Overflow Underflow Legend O Possible Not poss...

Page 341: ...ng mode B phase input TIOCA0 I O TGRA_0 input capture input output compare output PWM output pin TIOCB0 I O TGRB_0 input capture input output compare output PWM output pin TIOCC0 I O TGRC_0 input capture input output compare output PWM output pin 0 TIOCD0 I O TGRD_0 input capture input output compare output PWM output pin TIOCA1 I O TGRA_1 input capture input output compare output PWM output pin 1...

Page 342: ...0 TGRB_0 Timer general register C_0 TGRC_0 Timer general register D_0 TGRD_0 Channel 1 Timer control register_1 TCR_1 Timer mode register_1 TMDR_1 Timer I O control register _1 TIOR_1 Timer interrupt enable register_1 TIER_1 Timer status register_1 TSR_1 Timer counter_1 TCNT_1 Timer general register A_1 TGRA_1 Timer general register B_1 TGRB_1 Channel 2 Timer control register_2 TCR_2 Timer mode re...

Page 343: ...Clock Edge 1 0 Select the input clock edge When the internal clock is counted using both edges the input clock cycle is 1 2 example φ 4 both edges φ 2 rising edge If phase counting mode is used on channels 1 and 2 this setting is ignored and the phase counting mode setting has priority Internal clock edge selection is valid when the input clock is φ 4 or slower This setting is ignored if the input...

Page 344: ...hronous operation 1 Notes 1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1 2 When TGRC or TGRD is used as a buffer register TCNT is not cleared because the buffer register setting has priority and compare match input capture dose not occur Table 12 4 CCLR2 to CCLR0 Channels 1 and 2 Channel Bit 7 Reserved 2 Bit 6 CCLR1 Bit 5 CCLR0 Description 0 TCNT clearing disable...

Page 345: ...External clock counts on TCLKC pin input 0 1 1 1 External clock counts on TCLKD pin input Table 12 6 TPSC2 to TPSC0 Channel 1 Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 Internal clock counts on φ 1 0 1 Internal clock counts on φ 4 0 Internal clock counts on φ 16 0 1 1 Internal clock counts on φ 64 0 External clock counts on TCLKA pin input 0 1 External clock counts on TCLKB pin inpu...

Page 346: ...ster TMDR TMDR sets the operating mode for each channel The TPU has a total of three TMDR registers one for each channel TMDR settings should be made only when TCNT operation is stopped Bit Bit Name Initial Value R W Description 7 6 All 1 Reserved These bits are always read as 1 and cannot be modified 5 BFB 0 R W Buffer Operation B Specifies whether TGRB is to operate in the normal way or TGRB and...

Page 347: ...d TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R W R W R W R W Modes 3 to 0 Set the timer operating mode MD3 is a reserved bit The write value should always be 0 See table 12 8 for details Table 12 8 MD3 to MD0 Bit 3 MD3 1 Bit 2 MD2 2 Bit 1 MD1 Bit 0 MD0 Description 0 Normal operation 0 1 Reserved 0 PWM mode 1 0 1 1 PWM mode 2 0 Phase counting mode 1 0 1 Phase counting m...

Page 348: ...pecified When TGRC or TGRD is designated for buffer operation this setting is invalid and TIOR operates as a buffer register TIORH_0 TIOR_1 TIOR_2 Bit Bit Name Initial Value R W Description 7 6 5 4 IOB3 IOB2 IOB1 IOB0 0 0 0 0 R W R W R W R W I O Control B3 to B0 Specify the function of TGRB 3 2 1 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 R W R W R W R W I O Control A3 to A0 Specify the function of TGRA TIORL_...

Page 349: ... output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 0 Capture input source is TIOCB0 pin Input capture at rising edge 0 1 Capture input source is TIOCB0 pin Input capture at falling edge 0 1 Capture input source is TIOCB0 pin Input capture at both edges 1 1 Input capture register Capture input source is channel 1 c...

Page 350: ...put disabled 0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 0 Capture input source is TIOCA0 pin Input capture at rising edge 0 1 Capture input source is TIOCA0 pin Input capture at falling edge 0 1 Capture input source is TIOCA0 pin Input captu...

Page 351: ...nitial output is 1 output Toggle output at compare match 0 Capture input source is TIOCD0 pin Input capture at rising edge 0 1 Capture input source is TIOCD0 pin Input capture at falling edge 0 1 Capture input source is TIOCD0 pin Input capture at both edges 1 1 Input capture register 2 Capture input source is channel 1 count clock Input capture at TCNT_1 count up count down 1 Legend x Don t care ...

Page 352: ... output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 0 Capture input source is TIOCC0 pin Input capture at rising edge 0 1 Capture input source is TIOCC0 pin Input capture at falling edge 0 1 Capture input source is TIOCC0 pin Input capture at both edges 1 1 Input capture register Capture input source is channel 1 c...

Page 353: ...l output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 0 Capture input source is TIOCB1 pin Input capture at rising edge 0 1 Capture input source is TIOCB1 pin Input capture at falling edge 0 1 Capture input source is TIOCB1 pin Input capture at both edges 1 1 In...

Page 354: ...l output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 0 Capture input source is TIOCA1 pin Input capture at rising edge 0 1 Capture input source is TIOCA1 pin Input capture at falling edge 0 1 Capture input source is TIOCA1 pin Input capture at both edges 1 1 In...

Page 355: ...s 0 output Toggle output at compare match 0 Output disabled 0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 0 Capture input source is TIOCB2 pin Input capture at rising edge 0 1 Capture input source is TIOCB2 pin Input capture at falling edge 1 1...

Page 356: ...s 0 output Toggle output at compare match 0 Output disabled 0 1 Initial output is 1 output 0 output at compare match 0 Initial output is 1 output 1 output at compare match 0 1 1 1 Output compare register Initial output is 1 output Toggle output at compare match 0 Capture input source is TIOCA2 pin Input capture at rising edge 0 1 Capture input source is TIOCA2 pin Input capture at falling edge 1 1...

Page 357: ...ays read as 0 and cannot be modified 0 Interrupt requests TCIU by TCFU disabled 1 Interrupt requests TCIU by TCFU enabled 4 TCIEV 0 R W Overflow Interrupt Enable Enables or disables interrupt requests TCIV by the TCFV flag when the TCFV flag in TSR is set to 1 0 Interrupt requests TCIV by TCFV disabled 1 Interrupt requests TCIV by TCFV enabled 3 TGIED 0 R W TGR Interrupt Enable D Enables or disabl...

Page 358: ...each channel The TPU has a total of three TSR registers one for each channel Bit Bit Name Initial Value R W Description 7 TCFD 1 R Count Direction Flag Status flag that indicates the direction in which TCNT counts in channels 1 and 2 In channel 0 bit 7 is reserved It is always read as 1 and cannot be modified 0 TCNT counts down 1 TCNT counts up 6 1 R Reserved This bit is always read as 1 and canno...

Page 359: ...ons When TCNT TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Clearing condition When 0 is written to TGFD after reading TGFD 1 2 TGFC 0 R W Input Capture Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channel 0 In c...

Page 360: ...le TGRB is functioning as input capture register Clearing condition When 0 is written to TGFB after reading TGFB 1 0 TGFA 0 R W Input Capture Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match Setting conditions When TCNT TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while...

Page 361: ... units it must always be accessed in 16 bit units TGR and buffer register combinations are TGRA TGRC and TGRB TGRD 12 3 8 Timer Start Register TSTR TSTR selects TCNT operation stop for channels 0 to 2 If the corresponding bit is set to 1 TCNT starts counting for the channel When setting the operating mode in TMDR or setting the count clock in TCR first stop the TCNT counter Bit Bit Name Initial Va...

Page 362: ...n is independent of or synchronized with other channels When synchronous operation is selected synchronous presetting of multiple channels and synchronous clearing due to counter clearing on another channel are possible To set synchronous operation the SYNC bits for at least two channels must be set to 1 To set synchronous clearing in addition to the SYNC bit the TCNT clearing source must also be ...

Page 363: ...H L TCNTH TCNTL Internal data bus Bus interface Module data bus Bus master Figure 12 2 16 Bit Register Access Operation Bus Master TCNT 16 Bits 12 4 2 8 Bit Registers Registers other than TCNT and TGR are 8 bits As the data bus to the bus master is 16 bits wide these registers can be read from or written to in 16 bit units They can also be read from or written to in 8 bit units Examples of 8 bit r...

Page 364: ...us interface Module data bus Bus master Figure 12 4 8 Bit Register Access Operation Bus Master TMDR Lower 8 Bits H L TCR TMDR Internal data bus Bus interface Module data bus Bus master Figure 12 5 8 Bit Register Access Operation Bus Master TCR and TMDR 16 Bits ...

Page 365: ...n setting procedure Operation selection Select counter clock Periodic counter Select counter clearing source Select output compare register Set period Free running counter Start count operation Free running counter Periodic counter Start count operation Select the counter clock with bits TPSC2 to TPSC0 in TCR At the same time select the input clock edge with bits CKEG1 and CKEG0 in TCR For periodi...

Page 366: ...FFF H 0000 CST bit TCFV Time Figure 12 7 Free Running Counter Operation When compare match is selected as the TCNT clearing source TCNT for the relevant channel performs periodic count operation TGR for setting the period is designated as an output compare register and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR After the settings have been made TCNT starts...

Page 367: ...ws an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode Set output timing Start count operation Waveform output Select 0 output or 1 output for the initial value and 0 output 1 output or toggle output for the compare match output value by means of TIOR The set initial value is output at the TIOC pin until the first compare match occu...

Page 368: ...ter clearing performed by compare match B and settings have been made so that output is toggled by both compare match A and compare match B TCNT value H FFFF H 0000 TIOCB TIOCA Time TGRB TGRA Toggle output Toggle output Counter cleared by TGRB compare match Figure 12 11 Example of Toggle Output Operation Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin i...

Page 369: ...to start the count operation 1 2 1 2 Figure 12 12 Example of Setting Procedure for Input Capture Operation Example of Input Capture Operation Figure 12 13 shows an example of input capture operation In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge falling edge has been selected as the TIOCB pin input capture input edge and counter clearing ...

Page 370: ...Synchronous presetting Set TCNT Synchronous presetting Counter clearing Synchronous clearing Synchronous clearing Clearing source generation channel Select counter clearing source Start counting Set synchronous counter clearing Start counting Set 1 to the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation When TCNT of any of the channels designated for synch...

Page 371: ...el 1 and 2 counter clearing source Three phase PWM waveforms are output from pins TIOCA0 TIOCA1 and TIOCA2 At this time synchronous presetting and synchronous clearing by TGRB_0 compare match are performed for the TCNT counters in channels 0 to 2 and the data set in TGRB_0 is used as the PWM cycle For details on PWM modes see section 12 5 5 PWM Modes TCNT0 to TCNT2 values H 0000 TIOCA0 TIOCA1 TGRB...

Page 372: ...e value in the buffer register for the corresponding channel is transferred to the timer general register This operation is illustrated in figure 12 16 Buffer register Timer general register TCNT Comparator Compare match signal Figure 12 16 Compare Match Buffer Operation When TGR is an input capture register When input capture occurs the value in TCNT is transferred to TGR and the value previously...

Page 373: ...ple in which PWM mode 1 has been designated for channel 0 and buffer operation has been designated for TGRA and TGRC The settings used in this example are TCNT clearing by compare match B 1 output at compare match A and 0 output at compare match B As buffer operation has been set when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to t...

Page 374: ...RA input capture has been set for TCNT and both rising and falling edges have been selected as the TIOCA pin input capture input edge As buffer operation has been set when the TCNT value is stored in TGRA upon occurrence of input capture A the value previously stored in TGRA is simultaneously transferred to TGRC TCNT value H 09FB H 0000 TGRC Time H 0532 TIOCA TGRA H 0F07 H 0532 H 0F07 H 0532 H 0F0...

Page 375: ...2 TCNT_1 TCNT_2 Example of Cascaded Operation Setting Procedure Figure 12 21 shows an example of the setting procedure for cascaded operation Cascaded operation Set cascading Start counting Cascaded operation Set bits TPSC2 to TPSC0 in the channel 1 TCR to B 111 to select TCNT_2 overflow underflow counting Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation 1 ...

Page 376: ...ow TCLKC TCNT_2 FFFD TCNT_1 0001 TCLKD FFFE FFFF 0000 0001 0002 0001 0000 FFFF 0000 0000 Figure 12 23 Example of Cascaded Operation 2 12 5 5 PWM Modes In PWM mode PWM waveforms are output from the output pins 0 1 or toggle output can be selected as the output level in response to compare match of each TGR Settings of TGR registers can output a PWM waveform in the range of 0 to 100 duty Designating...

Page 377: ... register and the others as duty registers The value specified in TIOR is output by means of compare matches Upon counter clearing by a synchronous register compare match the output value of each pin is the initial value set in TIOR When the set values of the periodic and duty registers are identical the output value does not change even if a compare match occurs In PWM mode 2 a maximum 7 phase PW...

Page 378: ...t the initial value and output value Set the period in the TGR selected in 2 and set the duty in the other TGR Select the PWM mode with bits MD3 to MD0 in TMDR Set the CST bit in TSTR to 1 to start the count operation 1 2 3 4 5 6 1 2 3 4 5 6 Figure 12 24 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation Figure 12 25 shows an example of PWM mode 1 operation In this example TGRA c...

Page 379: ...r the initial output value and 1 for the output value of the other TGR registers TGRA_0 to TGRD_0 TGRA_1 to output a 5 phase PWM waveform In this case the value set in TGRB_1 is used as the period and the values set in the other TGRs as the duty TCNT value TGRB_1 H 0000 TIOCA0 Counter cleared by TGRB_1 compare match Time TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 12 26 E...

Page 380: ...A H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when periodic register and duty register compare matches occur simultaneously TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when periodic register and duty register compare matches occur simultaneously 0 duty Figure 12 27 Exampl...

Page 381: ...n an underflow occurs while TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag provides an indication of whether TCNT is counting up or down Table 12 20 shows the correspondence between external clock pins and channels Table 12 20 Clock Input Pins for Phase Counting Mode External Clock Pins Channels A Phase B Phase When channel 1 is set...

Page 382: ... mode 1 operation and table 12 21 summarizes the TCNT up down count conditions TCNT value Time Down count Up count TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 12 29 Example of Phase Counting Mode 1 Operation Table 12 21 Up Down Count Conditions in Phase Counting Mode 1 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation High level Low level Low leve...

Page 383: ...C channel 2 TCLKB channel 1 TCLKD channel 2 Figure 12 30 Example of Phase Counting Mode 2 Operation Table 12 22 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Don t care Low level Don t care High level Don t care Low level Down ...

Page 384: ...C channel 2 TCLKB channel 1 TCLKD channel 2 Figure 12 31 Example of Phase Counting Mode 3 Operation Table 12 23 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Down count Low level Don t care High level Don t care Low level Don t...

Page 385: ...e TCLKA channel 1 TCLKC channel 2 TCLKB channel 1 TCLKD channel 2 Figure 12 32 Example of Phase Counting Mode 4 Operation Table 12 24 Up Down Count Conditions in Phase Counting Mode 4 TCLKA Channel 1 TCLKC Channel 2 TCLKB Channel 1 TCLKD Channel 2 Operation High level Low level Up count Low level High level Don t care High level Low level Down count High level Low level Don t care Legend Rising ed...

Page 386: ...ler but the priority within a channel is fixed For details see section 5 Interrupt Controller Table 12 25 lists the TPU interrupt sources Table 12 25 TPU Interrupts Channel Name Interrupt Source Interrupt Flag Priority TGI0A TGRA_0 input capture compare match TGFA High TGI0B TGRB_0 input capture compare match TGFB TGI0C TGRC_0 input capture compare match TGFC TGI0D TGRD_0 input capture compare mat...

Page 387: ...r each channel Underflow Interrupt An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel The interrupt request is cleared by clearing the TCFU flag to 0 The TPU has a total of two underflow interrupts one each for channels 1 and 2 12 6 2 A D Converter Activation The A D converter can be activated by the...

Page 388: ...operation and figure 12 34 shows TCNT count timing in external clock operation TCNT TCNT input clock Internal clock φ N 1 N N 1 N 2 Falling edge Rising edge Figure 12 33 Count Timing in Internal Clock Operation TCNT TCNT input clock External clock φ N 1 N N 1 N 2 Falling edge Rising edge Falling edge Figure 12 34 Count Timing in External Clock Operation ...

Page 389: ...output compare output TIOC pin After a match between TCNT and TGR the compare match signal is not generated until the TCNT input clock is generated Figure 12 35 shows output compare output timing TGR TCNT TCNT input clock N N N 1 Compare match signal TIOC pin φ Figure 12 35 Output Compare Output Timing Input Capture Signal Timing Figure 12 36 shows input capture signal timing TCNT Input capture in...

Page 390: ...e match occurrence is specified and figure 12 38 shows the timing when counter clearing by input capture occurrence is specified TCNT Counter clear signal Compare match signal TGR N N H 0000 φ Figure 12 37 Counter Clear Timing Compare Match TCNT Counter clear signal Input capture signal TGR N H 0000 N φ Figure 12 38 Counter Clear Timing Input Capture ...

Page 391: ...nd 12 40 show the timing in buffer operation TGRA TGRB Compare match signal TCNT TGRC TGRD n N N n n 1 φ Figure 12 39 Buffer Operation Timing Compare Match TGRA TGRB TCNT Input capture signal TGRC TGRD N n n N 1 N N N 1 φ Figure 12 40 Buffer Operation Timing Input Capture ...

Page 392: ... in Case of Compare Match Figure 12 41 shows the timing for setting of the TGF flag in TSR by compare match occurrence and TGI interrupt request signal timing TGR TCNT TCNT input clock N N N 1 Compare match signal TGF flag TGI interrupt φ Figure 12 41 TGI Interrupt Timing Compare Match ...

Page 393: ...Figure 12 42 TGI Interrupt Timing Input Capture TCFV Flag TCFU Flag Setting Timing Figure 12 43 shows the timing for setting of the TCFV flag in TSR by overflow occurrence and TCIV interrupt request signal timing Figure 12 44 shows the timing for setting of the TCFU flag in TSR by underflow occurrence and TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT input clock H FFFF H ...

Page 394: ... Interrupt Setting Timing Status Flag Clearing Timing After a status flag is read as 1 by the CPU it is cleared by writing 0 to it Figure 12 45 shows the timing for status flag clearing by the CPU T1 T2 TSR write cycle TSR address Address Write signal Status flag Interrupt request signal Figure 12 45 Timing for Status Flag Clearing by CPU ...

Page 395: ... clock conditions in phase counting mode Overlap Phase differ ence Phase differ ence Overlap TCLKA TCLKC TCLKB TCLKD Pulse width Pulse width Pulse width Pulse width Notes Phase difference and overlap Pulse width 1 5 states or more 2 5 states or more Figure 12 46 Phase Difference Overlap and Pulse Width in Phase Counting Mode Caution on Period Setting When counter clearing by compare match is set T...

Page 396: ...dress φ TCNT address TCNT TCNT write cycle T1 T2 N H 0000 Figure 12 47 Contention between TCNT Write and Clear Operations Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle the TCNT write takes priority and TCNT is not incremented Figure 12 48 shows the timing in this case TCNT input clock Write signal Address φ TCNT address TCNT TCN...

Page 397: ...ress TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 Disabled Figure 12 49 Contention between TGR Write and Compare Match Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle the data transferred to TGR by the buffer operation will be the write data Figure 12 50 shows the timing in this case Compare match signal Write sig...

Page 398: ...ddress TGR TGR read cycle T1 T2 M Internal data bus X M Figure 12 51 Contention between TGR Read and Input Capture Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle the input capture operation takes priority and the write to TGR is not performed Figure 12 52 shows the timing in this case Input capture signal Write signal Ad...

Page 399: ... capture signal Write signal Address φ TCNT Buffer register write cycle T1 T2 N TGR N M M Buffer register Buffer register address Figure 12 53 Contention between Buffer Register Write and Input Capture Contention between Overflow Underflow and Counter Clearing If overflow underflow and counter clearing occur simultaneously the TCFV TCFU flag in TSR is not set and TCNT clearing takes priority Figur...

Page 400: ... there is an up count or down count in the T2 state of a TCNT write cycle and overflow underflow occurs the TCNT write takes priority and the TCFV TCFU flag in TSR is not set Figure 12 55 shows the operation timing when there is contention between TCNT write and overflow Write signal Address φ TCNT address TCNT TCNT write cycle T1 T2 H FFFF M TCNT write data TCFV flag Figure 12 55 Contention betwe...

Page 401: ... the TIOCB1 I O pin and the TCLKD input pin with the TIOCB2 I O pin When an external clock is input compare match output should not be performed from a multiplexed pin Interrupts in Module Stop Mode If module stop mode is entered when an interrupt has been requested it will not be possible to clear the CPU interrupt source Interrupts should therefore be disabled before entering module stop mode ...

Page 402: ...Rev 1 00 09 03 page 364 of 704 ...

Page 403: ...hannel 0 and three input pins for channel 1 Positive logic is assumed for all signals used within the timer connection facility An edge detection circuit is connected to the input pins simplifying signal input detection TMRX can be used for PWM input signal decoding TMRX can be used for clamp waveform generation An external clock signal divided by TMR1 can be used as the FRT capture input signal A...

Page 404: ...SYNCO output selection VSYNCI_0 HSYNCI_0 CBLANK CLAMPO HSYNCO VSYNCO HSYNCO_1 HSYNCO_0 VSYNCO_0 VSYNCO_1 CSYNCI_0 VSYNCI_1 HSYNCI_1 CSYNCI_1 VFBACKI_0 HFBACKI_0 Timer connection Channel 1 VSYNCO output selection Figure 13 1 Schematic Diagram of Timer Connection ...

Page 405: ...VSYNCO FTOA TMRI TMCI TMO 8 bit TMR_Y CBLANK FTOB HSYNCO TMO1 TMO1 output selection IHO signal selection CL4 generator CL4 signal CLAMPO FTIC CLO signal selection PDC signal PWM decode 8 bit TMR_X CMB TMO CMA ICR ICR 1C compare match TMRI TMCI CM1C CL1 signal CL2 signal CL3 signal IHI signal IHI signal selection HSYNCI TMI1 CSYNCI FTID HFBACKI FTCI TMOX IVG signal IVO signal IHG signal Phase inver...

Page 406: ...BACKI_0 Input Spare horizontal synchronization signal input pin or FTCI_0 input pin Clamp waveform output pin CLAMPO Output Clamp waveform output pin or FTIC_0 input pin 0 Blanking waveform output pin CBLANK Output Blanking waveform output pin or FTOB_0 output pin Vertical synchronization signal input pin VSYNCI_1 Input Vertical synchronization signal input pin or FTIA_1 input pin Horizontal synch...

Page 407: ...ion etc Bit Bit Name Initial Value R W Description 7 6 SIMOD1 SIMOD0 0 0 R W R W Input Synchronization Mode Select 1 0 Select the signal source of the IHI and IVI signals Mode 00 No signal 01 S on G mode 10 Composite mode 11 Separate mode IHI Signal 00 HFBACKI input setting prohibited for channel 1 01 CSYNCI input 10 HSYNCI input 11 HSYNCI input IVI Signal 00 VFBACKI input setting prohibited for c...

Page 408: ...1 Input capture function of TICRR and TICRF is operating Waiting for the time when a rising edge followed by a falling edge is detected on TMRIX Setting condition When 1 is written to ICST after reading ICST 0 3 HFINV 0 R W Spare Horizontal Synchronization Signal Inversion Selects inversion of the input phase of the spare horizontal synchronization signal HFBACKI This bit is reserved in channel 1 ...

Page 409: ...ynchronization Signal Inversion Selects inversion of the input phase of the vertical synchronization signal VSYNCI 0 The VSYNCI pin state is used directly as the VSYNCI input 1 The VSYNCI pin state is inverted before use as the VSYNCI input Table 13 2 Synchronization Signal Connection Enable Bit 5 Description SCONE Mode FTIA FTIB FTIC FTID TMCI1 TMRI1 TMCIX TMRIX 0 Normal connection Initial value ...

Page 410: ...anking waveform CBLANK in channel 0 These bits are reserved in channel 1 The initial value should not be changed HOE 0 The PB1 TMO1_0 HSYNCO pin functions as the PB1 TMO1_0 pin 1 The PB1 TMO1_0 HSYNCO pin functions as the HSYNCO pin VOE 0 The PB0 FTOA_0 VSYNCO pin functions as the PB0 FTOA_0 pin 1 The PB0 FTOA_0 VSYNCO pin functions as the VSYNCO pin CLOE 0 The PA4 FTIC_0 CLAMPO pin functions as t...

Page 411: ...it in TECR See table 13 4 1 0 CLOINV CBOINV 0 0 R W R W Output Synchronization Signal Inversion Selects inversion of the output phase of the clamp waveform CLAMPO and blanking waveform CBLANK in channel 0 These bits are reserved in channel 1 The initial value should not be changed CLOINV 0 The CLO signal CL1 CL2 CL3 or CL4 signal is used directly as the CLAMPO output 1 The CLO signal CL1 CL2 CL3 o...

Page 412: ...ut 0 1 1 The input signal of the HSYNCI_1 is used as the HSYNCO output 0 The input signal of the CSYNCI_0 is used as the HSYNCO output 0 1 The input signal of the CSYNCI_1 is used as the HSYNCO output 0 Port output 1 1 1 Setting prohibited Note The PB1DR value is output regardless of the PB1DDR setting Table 13 4 VSYNCO Output Selection TECR TCONRI_1 TCONRI_0 VS0 VOINV VOINV VSYNCO Output Signal 0...

Page 413: ...nchronization Output Mode Select 1 0 Select the signal source and generation method for the IHO signal ISGENE 0 00 The IHI signal without 2fH modification is selected 01 The IHI signal with 2fH modification is selected 1X The CL1 signal is selected ISGENE 1 XX The IHG signal is selected 3 2 VOMOD1 VOMOD0 0 0 R W R W Vertical Synchronization Output Mode Select 1 0 Select the signal source and gener...

Page 414: ...ode Select 1 0 Select the signal source for the CLO signal clamp waveform in channel 0 These bits are reserved in channel 1 The initial value should not be changed ISGENE 0 00 The CL1 signal is selected 01 The CL2 signal is selected 1X The CL3 signal is selected ISGENE 1 XX The CL4 signal is selected Legend X Don t care ...

Page 415: ...e Detects a rising edge on the HSYNCI pin 0 Clearing condition When 0 is written to HEDG after reading HEDG 1 1 Setting condition When a rising edge is detected on the HSYNCI pin 5 CEDG 0 R W 1 CSYNCI Edge Detects a rising edge on the CSYNCI pin 0 Clearing condition When 0 is written to CEDG after reading CEDG 1 1 Setting condition When a rising edge is detected on the CSYNCI pin 4 HFEDG 0 R W 1 H...

Page 416: ...IHI Signal 0 Clearing condition When 0 is written to PREQF after reading PREQF 1 1 Setting condition When a 2fH modification condition for the IHI signal is detected 1 IHI 2 R IHI Signal Level Indicates the current level of the IHI signal A signal source and phase inversion are selected for the IHI signal depends on the contents of TCONRI Read this bit to determine whether the input signal is posi...

Page 417: ...onization Signal Output Select 2 to 0 Select the signal output from the HSYNCO with the settings of the HOINV bit in TCONRO See table 13 3 3 2 ICKS1_1 ICKS0_1 0 0 R W R W Internal Clock Source Select Channel 1 Select the clock input to the timer counter TCNT for the TMR0_1 and TMR1_1 and count condition with the settings of the CKS2 to CKS0 bits in the timer control register 1 TCR_1 For details se...

Page 418: ...The PWM decoder contains a delay latch which uses the IHI signal as data and compare match signal B CMB as a clock and the state of the IHI signal the result of the pulse width decision at the first compare match signal B timing after the TCNT is reset by the rise of the IHI signal is output as the PDC signal Figure 13 3 shows a block diagram for the PWM decoding The pulse width setting using TICR...

Page 419: ...ed on φ Table 13 6 Examples of TCORB Pulse Width Threshold Settings φ φ φ φ 10 MHz φ φ φ φ 12 MHz φ φ φ φ 16 MHz φ φ φ φ 20 MHz H 07 0 8 µs 0 67 µs 0 5 µs 0 4 µs H 0F 1 6 µs 1 33 µs 1 µs 0 8 µs H 1F 3 2 µs 2 67 µs 2 µs 1 6 µs H 3F 6 4 µs 5 33 µs 4 µs 3 2 µs H 7F 12 8 µs 10 67 µs 8 µs 6 4 µs IHI signal IHI signal is tested at compare match Counter reset caused by IHI signal Counter clear caused by ...

Page 420: ...n an internal clock φ is selected as the TMRX counter clock and a value or H 01 or more when φ 2 is selected When an internal clock φ is selected the CL1 signal pulse width is TCORA set value 3 0 5 When the CL2 signal is used the setting must be made so that this pulse width is greater than the IHI signal pulse width The value to be used as the CL3 signal pulse width is written to TCORC TICR of th...

Page 421: ...ure Contol logic TCNT CMC CMC CMA CMA TMRI IHI signal CL2 CL3 CL1 Comparator C TCORC TICR TCORA Comparator A TMRX Figure 13 5 Block Diagram for Clamp Waveform Generation IHI signal CL1 signal CL2 signal TCNT TCORA Figure 13 6 Timing Chart for Clamp Waveform Generation CL1 and CL2 Signals ...

Page 422: ...Rev 1 00 09 03 page 384 of 704 IHI signal CL3 signal TCNT TICR TCORC TICR Figure 13 7 Timing Chart for Clamp Waveform Generation CL3 Signal ...

Page 423: ...set to count the external clock IHI signal pulses and to be cleared on the rising edge of the external reset signal inverse of the IVI signal The value to be used as the division ratio is written to TCORA and the TMO output method is specified by the OS bit in TCSR Examples of TCR and TCSR settings of the TMR1 and FRT are shown in table 13 7 and the timing chart for measurement of the IVI signal a...

Page 424: ...f the external clock IHI signal 0011 Not changed by compare match B output inverted by compare match A toggle output Division by 512 TCSR of TMR1 3 to 0 OS3 to OS0 1001 When TCORB TCORA 1 output on compare match B and 0 output on compare match A Division by 256 6 IEDGB 0 1 0 FRC value is transferred to ICRB on falling edge of input capture input B IHI divided signal waveform 1 FRC value is transfe...

Page 425: ... FRT and compare matches generated at these points The interval between the two compare matches is called a mask interval A value equivalent to approximately 1 3 the IHI signal period is written to OCRDM ICRD is set so that capture is performed on the rise of the IHI signal Figure 13 10 shows a block diagram for 2fH modification of the IHI signal Since the IHI signal supplied to the IHO signal sel...

Page 426: ...DM Settings Register Bit Abbreviation Contents Description 4 IEDGD 1 FRC value is transferred to ICRD on the rising edge of input capture input D IHI signal TCR of FRT 1 0 CKS1 CKS0 01 FRC is incremented on internal clock φ 8 TCSR of FRT 0 CCLRA 0 FRC clearing is disabled TCOR of FRT 7 ICRDMS 1 ICRD is set to the operating mode in which OCRDM is used OCRDM of FRT 7 to 0 OCRDM7 to OCRDM0 H 01 to H ...

Page 427: ...al operation To measure of the 8 bit timer divided waveform period TCNT of the TMR1 is set to count external clock IHI signal pulses and to be cleared on the rising edge of the external reset signal inverse of the IVI signal The number of IHI signal pulses until the fall of the IVI signal is written to TOCRB Since the IVI signal supplied to the IVO signal selection circuit is normally set on the r...

Page 428: ...9 and the fall modification and IHI synchronization timing chart is shown in figure 13 13 Vertical synchronization signal modification Clock Clear TCNT CMB Comparator B IVI signal Modification signal TCORB IHI signal TMR1 Figure 13 12 Block Diagram for IVI Signal Fall Modification and IHI Signal Operation ...

Page 429: ... the IVI signal 0 1 2 3 4 5 TCNT TCNT TCORB 3 IHI signal IVI signal PDC signal IVO signal without fall modification with IHI synchronization IVO signal with fall modification without IHI synchronization IVO signal with fall modification and IHI synchronization Figure 13 13 Fall Modification and IHI Synchronization Timing Chart 13 4 6 Internal Synchronization Signal Generation IHG IVG CL4 Signal Ge...

Page 430: ... TCORA compare match to fix the period and set the timer output TCORB is set so as to reset the timer output The IVG signal is connected as the TMRY reset input TMRI and the rise of the IVG signal can be treated in the same way as a TCORA compare match The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG signal and has an interval of 1 for 6 system clock...

Page 431: ... 00 09 03 page 393 of 704 Control logic Internal clock Clock CMA Clear Clear CMB TMO IVG signal IHG signal TCNT TCORA Comparator A TCORB Comparator B TMRY Figure 13 15 Block Diagram for IHG Signal Generation ...

Page 432: ...on internal clock φ 4 TCSR of TMRY 3 to 0 OS3 to OS0 0110 0 output on compare match B 1 output on compare match A TCORA of TMRY H 3F example IHG signal period φ 256 TCORB of TMRY H 03 example 1 interval of IHG signal φ 16 TCR of FRT 1 0 CKS1 CKS0 01 FRC is incremented on internal clock φ 8 OCRAR of FRT H 7FEF example 0 interval of IVG signal φ 262016 OCRAF of FRT H 000F example 1 interval of IVG s...

Page 433: ...em clocks 6 system clocks 6 system clocks OCRA 4 OCRA 3 OCRAR OCRA 3 OCRA 2 OCRAF OCRA 2 OCRA 1 OCRAR OCRA 1 OCRA 0 OCRAF OCRA FRC CL4 signal IHG signal TCORA TCORB TCNT IVG signal Figure 13 16 IVG Signal IHG Signal CL4 Signal Timing Chart ...

Page 434: ...signal is eliminated before output CL1 signal Horizontal synchronization signal part of CSYNCI input composite synchronization signal is separated before output S on G mode CSYNCI input IHG signal Internal synchronization signal is output IHI signal without 2fH modification HSYNCI input composite synchronization signal is output directly IHI signal with 2fH modification Double frequency part of HS...

Page 435: ...re output No signal VFBACKI input IVG signal Internal synchronization signal is output IVI signal without fall modification or IHI synchronization Vertical synchronization signal part of CSYNCI HSYNCI input composite synchronization signal is separated before output IVI signal without fall modification with IHI synchronization Vertical synchronization signal part of CSYNCI HSYNCI input composite s...

Page 436: ...nd the signal is synchronized with HSYNCI input horizontal synchronization signal before output Separate mode VSYNCI input IVG signal Internal synchronization signal is output 13 4 9 CBLANK Output Using the signals generated selected with the timer connection it is possible to generate an waveform based on the composite synchronization signal blanking waveform This function is not available in cha...

Page 437: ...14 1 Features Selection of a counter operating signal from eight operating clocks One of the eight operating clocks φ φ 2 φ 4 φ 8 φ 32 φ 2048 φ 32768 or φ 65536 can be selected Automatic duty measurement of eight external event signals for two systems Using an edge detection circuit enables both edges of the external event signal to be detected and capturing the counter value enables the duty to b...

Page 438: ...er 2 HSYNCI_0 HSYNCI_1 CSYNCI_0 CSYNCI_1 HFBACKI_0 HFBACKI_1 VSYNCI_0 VSYNCI_1 TWCNT TWICR TWCR1 TWCR2 Clock Input capture Interrupt signal TWOVI TWENDI TWCNT TWCR1 TWCR2 TWICR Overflow Clear Clock selection Legend Internal data bus Control logic Module data bus External signal selection Bus interface Edge detector Figure 14 1 Block Diagram of Duty Measurement Circuit ...

Page 439: ... signal 0 input pin CSYNCI_0 Input Composite synchronization signal 0 input pin Composite synchronization signal 1 input pin CSYNCI_1 Input Composite synchronization signal 1 input pin Spare horizontal synchronization signal input pin HFBACKI Input Spare horizontal synchronization signal input pin Spare vertical synchronization signal input pin VFBACKI Input Spare vertical synchronization signal i...

Page 440: ... 1 When the START bit in TWCR2 is set to 1 TWCNT is cleared and duty measurement is started For details on duty measurement operation see section 14 4 Operation The clock source is selected by bits CKS2 to CKS0 in TWCR1 When TWCNT overflows from H FF to H 00 the OVF bit in TWCR2 is set to 1 TWCNT is initialized to H 00 14 3 2 Input Capture Register TWICR TWICR is an 8 bit read only register When t...

Page 441: ...0 R W R W R W Clock Select 2 to 0 Select the clock input to TWCNT 000 Count on internal clock φ 001 Count on internal clock φ 2 010 Count on internal clock φ 4 011 Count on internal clock φ 8 100 Count on internal clock φ 32 101 Count on internal clock φ 2048 110 Count on internal clock φ 32768 111 Count on internal clock φ 65536 2 1 0 IS2 IS1 IS0 0 0 0 R W R W R W Input Select 2 to 0 Select the e...

Page 442: ...VIE 0 R W Overflow Interrupt Enable When the OVF flag in TWCR2 is set to 1 this bit enables or disables an interrupt request by the OVF flag 0 Disables an interrupt request TWOVI by OVF 1 Enables an interrupt request TWOVI by OVF 5 ENDF 0 R W Duty Measurement End A status flag indicating that duty measurement has ended Setting condition When duty measurement ends Clearing condition When 0 is writt...

Page 443: ...is bit duty measurement will start If this bit is read during duty measurement 1 is read from this bit If duty measurement ends this bit is automatically cleared to 0 If 0 is written during duty measurement duty measurement forcibly ends Even if 1 is written when the FRC bit in TWCR1 is 1 it is ignored Note Only 0 can be written to clear the flag ...

Page 444: ...00 4 When a rising edge of the external event signal is detected TWCNT starts counting Then if a falling edge of the external event signal is detected the TWCNT value is transferred to TWICR If the second rising edge of the external event signal is detected TWCNT stops counting At this time the ENDF flag in TWCR2 is set to 1 When TWICR and TWCNT values are read and then compared duty measurement f...

Page 445: ...CNT input clock Internal clock N 1 N N 1 Figure 14 3 TWCNT Count Timing 14 5 2 TWCNT Clear Timing by Setting START Bit Setting the START bit in TWCR2 to 1 starts duty measurement and then clears TWCNT Figure 14 4 shows the TWCNT clear timing TWCNT Clear signal START bit N 00 N Figure 14 4 TWCNT Clear Timing by Setting START Bit ...

Page 446: ...t start timing for duty measurement TWCNT TWCNT input clock External signal 01 00 Count enable signal Internal clock Figure 14 5 Count Start Timing for Duty Measurement 14 5 4 Capture Timing during Duty Measurement When a falling edge of the external event signal is detected during duty measurement the TWCNT value is transferred to TWICR Figure 14 6 shows the capture timing during duty measurement...

Page 447: ...ty measurement ends START bit Duty measurement end signal External signal Figure 14 7 Clear Timing for START Bit when Duty Measurement Ends 14 5 6 Set Timing for Duty Measurement End Flag ENDF When duty measurement ends the duty measurement end flag ENDF in TWCR2 is set to 1 Figure 14 8 shows the ENDF set timing ENDF Duty measurement end signal External signal Figure 14 8 Set Timing for Duty Measu...

Page 448: ...ag 14 6 Interrupt Sources The duty measurement circuit can request two interrupts TWOVI and TWENDI Table 14 2 lists the sources and priorities of these interrupts Each interrupt can be enabled or disabled by an interrupt enable bit in TCR or TCSR Independent signals are sent to the interrupt controller for each interrupt Table 14 2 Interrupt Sources for Duty Measurement Circuit Interrupt Interrupt...

Page 449: ...rite signal TWCNT TWCNT address TWCNT write cycle by CPU T1 T2 N M Counter write data Address Figure 14 10 TWCNT Write Increment Conflict 14 7 2 Write to START Bit during Free Running Counter Operation If 1 is written to the START bit in TWCR2 while the FRC bit in TWCR1 is 1 as shown in figure 14 11 duty measurement is ignored and the START bit is cleared to 0 START bit START bit clear signal TWCR...

Page 450: ...able 14 3 the changeover is regarded as a falling edge that generates the TWCNT clock and TWCNT is incremented Switching between an internal clock and external clock may also cause TWCNT to be incremented To prevent incorrect operation ensure that TWCNT should be stopped before an internal clock is changed Table 14 3 Switching of Internal Clock and TWCNT Operation No Timing of Switchover by Means ...

Page 451: ...clock TWCNT Switchover of CKS bit 4 Switching from high to high N N 1 N 2 N 3 Clock before switchover Clock after switchover TWCNT clock TWCNT Switchover of CKS bit Notes 1 Including switching from low to stop and from stop to low 2 Including switching from stop to high 3 Including switching from high to stop 4 Generated on the assumption that the switchover is a falling edge TWCNT is incremented ...

Page 452: ...rred to TWICR during duty measurement If the clock is changed when the old source is high and the new source is low as in case no 3 in table 14 4 the changeover is regarded as a falling edge and duty measurement is started or ended To prevent incorrect operation ensure that the IS bit should not be rewritten during duty measurement Table 14 4 Switching of External Event Signal and Operation of Edg...

Page 453: ... signal after switchover Rising edge detection signal Falling edge detection signal Switchover of IS bit 4 Switching from high to high External event signal before switchover External event signal after switchover Rising edge detection signal Falling edge detection signal Switchover of IS bit Notes 1 The switchover timing is detected as a rising edge 2 The switchover timing is detected as a fallin...

Page 454: ...Rev 1 00 09 03 page 416 of 704 ...

Page 455: ... Features Selectable from eight counter input clocks Switchable between watchdog timer mode and interval timer mode Watchdog Timer Mode If the counter overflows an internal reset or an internal NMI interrupt is generated Interval Timer Mode If the counter overflows an interval timer interrupt WOVI is generated A block diagram of the WDT is shown in figure 15 1 WOVI Interrupt request signal Interna...

Page 456: ...e timer control status register TCSR is cleared to 0 15 2 2 Timer Control Status Register TCSR TCSR selects the clock source to be input to TCNT and the timer mode Bit Bit Name Initial Value R W Description 7 OVF 0 R W Overflow Flag Indicates that TCNT has overflowed changes from H FF to H 00 Setting condition When TCNT overflows changes from H FF to H 00 When internal reset request generation is ...

Page 457: ... reset or an NMI interrupt is requested when TCNT has overflowed 0 An NMI interrupt is requested 1 An internal reset is requested 2 1 0 CKS2 CKS1 CKS0 0 0 0 R W R W R W Clock Select 2 to 0 Select the clock source to be input to TCNT The overflow cycle for φ 20 MHz is enclosed in parentheses 000 φ 2 cycle 25 6 µs 001 φ 64 cycle 819 2 µs 010 φ 128 cycle 1 6 ms 011 φ 512 cycle 6 5 ms 100 φ 2048 cycle...

Page 458: ...reset request from the watchdog timer and a reset input from the RES pin are processed in the same vector A reset source can be identified by the state of the XRST bit in SYSCR If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow the RES pin reset has priority and the XRST bit in SYSCR is set to 1 An NMI interrupt request from the watchdog ...

Page 459: ...hen TCNT overflows in interval timer mode the OVF bit in TCSR is set to 1 and at the same time an interval timer interrupt WOVI is requested The timing is shown in figure 15 4 TCNT value H 00 Time H FF WT 0 TME 1 WOVI Overflow Overflow Overflow Overflow WOVI Interval timer interrupt request occurrence WOVI WOVI WOVI Legend Figure 15 3 Interval Timer Mode Operation φ TCNT H FF H 00 Overflow signal ...

Page 460: ... Internal reset signal Figure 15 5 Internal Reset Signal Generation Timing 15 4 Interrupt Sources During interval timer mode operation an overflow generates an interval timer interrupt WOVI The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR The OVF flag must be cleared to 0 in the interrupt handling routine When the NMI interrupt request is selected in watchdog tim...

Page 461: ...the relative condition shown in figure 15 6 to write to TCNT or TCSR To write to TCNT the upper bytes must contain the value H 5A and the lower bytes must contain the write data before the transfer instruction execution To write to TCSR the upper bytes must contain the value H A5 and the lower bytes must contain the write data before the transfer instruction execution TCNT write TCSR write Address...

Page 462: ...ict between TCNT Write and Increment 15 5 3 Changing Values of CKS2 to CKS0 Bits If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating errors could occur in the incrementation Software must stop the watchdog timer by clearing the TME bit to 0 before changing the values of bits CKS2 to CKS0 15 5 4 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched...

Page 463: ...lly independent enabling transmission and reception to be executed simultaneously Double buffering is used in both the transmitter and the receiver enabling continuous transmission and continuous reception of serial data On chip baud rate generator allows any bit rate to be selected The external clock can be selected as a transfer clock source Choice of LSB first or MSB first transfer except in th...

Page 464: ...R Module data bus RDR TSR RSR Parity generation Parity check Legend RSR Receive shift register RDR Receive data register TSR Transmit shift register TDR Transmit data register SMR Serial mode register TDR Bus interface Internal data bus External clock SCR Serial control register SSR Serial status register SCMR Serial interface mode register BRR Bit rate register Figure 16 1 Block Diagram of SCI ...

Page 465: ...nel 1 receive data input 1 TxD1 Output Channel 1 transmit data output SCK2 I O Channel 2 clock input output RxD2 Input Channel 2 receive data input 2 TxD2 Output Channel 2 transmit data output SCK3 I O Channel 3 clock input output RxD3 Input Channel 3 receive data input 3 TxD3 Output Channel 3 transmit data output SCK4 I O Channel 4 clock input output RxD4 Input Channel 4 receive data input 4 TxD4...

Page 466: ...here it is stored After this RSR can receive the next data Since RSR and RDR function is a double buffer in this way continuous receive operations can be performed After confirming that the RDRF bit in SSR is set to 1 read RDR for only once RDR cannot be written to by the CPU The initial value of RDR is H 00 16 3 3 Transmit Data Register TDR TDR is an 8 bit register that stores transmit data When ...

Page 467: ...de 1 Clocked synchronous mode 6 CHR 0 R W Character Length enabled only in asynchronous mode 0 Selects 8 bits as the data length 1 Selects 7 bits as the data length LSB first is fixed and the MSB of TDR is not transmitted in transmission In clocked synchronous mode a fixed data length of 8 bits is used 5 PE 0 R W Parity Enable enabled only in asynchronous mode When this bit is set to 1 the parity ...

Page 468: ... MP 0 R W Multiprocessor Mode enabled only in asynchronous mode When this bit is set to 1 the multiprocessor communication function is enabled The PE bit and O E bit settings are invalid in multiprocessor mode 1 0 CKS1 CKS0 0 0 R W R W Clock Select 1 0 These bits select the clock source for the baud rate generator 00 φ clock n 0 01 φ 4 clock n 1 10 φ 16 clock n 2 11 φ 64 clock n 3 For the relation...

Page 469: ...s are enabled 5 TE 0 R W Transmit Enable When this bit is set to 1 transmission is enabled 4 RE 0 R W Receive Enable When this bit is set to 1 reception is enabled 3 MPIE 0 R W Multiprocessor Interrupt Enable enabled only when the MP bit in SMR is 1 in asynchronous mode When this bit is set to 1 receive data in which the multiprocessor bit is 0 is skipped and setting of the RDRF FER and ORER statu...

Page 470: ...ronous mode 00 Internal clock SCK pin functions as I O port 01 Internal clock Outputs a clock of the same frequency as the bit rate from the SCK pin 1x External clock Inputs a clock with a frequency 16 times the bit rate to the SCK pin Clocked synchronous mode 0x Internal clock SCK pin functions as clock output 1x External clock SCK pin functions as clock input Note x Don t care ...

Page 471: ...e Clearing conditions When 0 is written to TDRE after reading TDRE 1 When data is written to TDR 6 RDRF 0 R W Receive Data Register Full Indicates whether receive data is stored in RDR Setting condition When serial reception ends normally and receive data is transferred from RSR to RDR Clearing conditions When 0 is written to RDRF after reading RDRF 1 When data is read from RDR The RDRF flag is no...

Page 472: ... is written to PER after reading PER 1 2 TEND 1 R Transmit End Setting conditions When the TE bit in SCR is 0 When TDRE 1 at transmission of the last bit of a 1 byte serial transmit character Clearing conditions When 0 is written to TDRE after reading TDRE 1 When data is written to TDR 1 MPB 0 R Multiprocessor Bit Stores the multiprocessor bit in the receive frame When the RE bit in SCR is cleared...

Page 473: ...SB first in RDR The SDIR bit is valid only when the 8 bit data format is used for transmission reception when the 7 bit data format is used data is always transmitted received with LSB first 2 SINV 0 R W Data Invert Specifies inversion of the data logic level The SINV bit does not affect the logic level of the parity bit When the parity bit is inverted invert the O E bit in SMR 0 TDR contents are ...

Page 474: ...r Asynchronous mode B 64 2 N 1 2n 1 φ 106 Error 1 100 B 64 2 N 1 2n 1 φ 106 Clocked synchronous mode B 8 2 N 1 2n 1 φ 106 Smart card interface mode B S 2 N 1 2n 1 φ 106 Error B S 2 N 1 1 100 2n 1 φ 106 Notes B Bit rate bit s N BRR setting for baud rate generator 0 N 255 φ Operating frequency MHz n and S Determined by the SMR settings shown in the following table SMR Setting SMR Setting CKS1 CKS0 n...

Page 475: ...0 00 0 9 2 34 19200 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 2 0 00 38400 0 1 0 00 Operating Frequency φ φ φ φ MHz 3 6864 4 4 9152 5 Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 64 0 70 2 70 0 03 2 86 0 31 2 88 0 25 150 1 191 0 00 1 207 0 16 1 255 0 00 2 64 0 16 300 1 95 0 00 1 103 0 16 1 127 0 00 1 129 0 16 600 0 191 0 00 0 207 0 16 0 255 0 00 1 64 0 16 1200 0 95 0 00 0 103 0 16 0 127 0...

Page 476: ... 11 0 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5 0 00 Operating Frequency φ φ φ φ MHz 9 8304 10 12 12 288 Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 174 0 26 2 177 0 25 2 212 0 03 2 217 0 08 150 2 127 0 00 2 129 0 16 2 155 0 16 2 159 0 00 300 1 255 0 00 2 64 0 16 2 77 0 16 2 79 0 00 600 1 127 0 00 1 129 0 16 1 155 0 16 1 159 0 00 1200 0 255 0 00 1 6...

Page 477: ...3 0 47 0 00 0 51 0 16 0 55 0 00 19200 0 22 0 93 0 23 0 00 0 25 0 16 0 27 0 00 31250 0 13 0 00 0 14 1 70 0 15 0 00 0 16 1 20 38400 0 11 0 00 0 12 0 16 0 16 0 00 Operating Frequency φ φ φ φ MHz 18 19 6608 20 Bit Rate bit s n N Error n N Error n N Error 110 3 79 0 12 3 86 0 31 3 88 0 25 150 2 233 0 16 2 255 0 00 3 64 0 16 300 2 116 0 16 2 127 0 00 2 129 0 16 600 1 233 0 16 1 255 0 00 2 64 0 16 1200 1...

Page 478: ...0 19 6608 614400 0 0 7 3728 230400 0 0 20 625000 0 0 8 250000 0 0 Table 16 5 Maximum Bit Rate with External Clock Input Asynchronous Mode φ φ φ φ MHz External Input Clock MHz Maximum Bit Rate bit s φ φ φ φ MHz External Input Clock MHz Maximum Bit Rate bit s 2 0 5000 31250 9 8304 2 4576 153600 2 097152 0 5243 32768 10 2 5000 156250 2 4576 0 6144 38400 12 3 0000 187500 3 0 7500 46875 12 288 3 0720 1...

Page 479: ... 99 100k 0 4 0 9 0 19 0 24 0 39 0 49 250k 0 1 0 3 0 7 0 9 0 15 0 19 500k 0 0 0 1 0 3 0 4 0 7 0 9 1M 0 0 0 1 0 3 0 4 2 5M 0 0 0 1 5M 0 0 Legend Blank Setting prohibited Can be set but there will be a degree of error Continuous transmission or reception is not possible Table 16 7 Maximum Bit Rate with External Clock Input Clocked Synchronous Mode φ φ φ φ MHz External Input Clock MHz Maximum Bit Rate...

Page 480: ... start bit and starts serial communication Inside the SCI the transmitter and receiver are independent units enabling full duplex communication Both the transmitter and the receiver also have a double buffered structure so that data can be read from or written to during transmission or reception enabling continuous data transmission and reception LSB Start bit MSB Idle state mark state Stop bit 0 ...

Page 481: ...nchronous Mode PE 0 0 1 1 0 0 1 1 S 8 bit data STOP S 7 bit data STOP S 8 bit data STOP STOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit data MPB STOP STOP S 7 bit data STOP MPB S 7 bit data STOP MPB STOP S 7 bit data STOP STOP CHR 0 0 0 0 1 1 1 1 0 0 1 1 MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 SMR Settings 1 2 3 4 5 6 7 8 9 10 11 12 Serial Transmit Receiv...

Page 482: ... reception margin in asynchronous mode is determined by formula 1 below M 0 5 L 0 5 F 100 Formula 1 2N 1 N D 0 5 M Reception margin N Ratio of bit rate to clock N 16 D Clock duty D 0 5 to 1 0 L Frame length L 9 to 12 F Absolute value of clock rate deviation Assuming values of F 0 and D 0 5 in formula 1 the reception margin is determined by the formula below M 0 5 1 2 16 100 46 875 However this is ...

Page 483: ...nal clock is input at the SCK pin the clock frequency should be 16 times the bit rate When the SCI is operated on an internal clock the clock can be output from the SCK pin The frequency of the clock output in this case is equal to the bit rate and the phase is such that the rising edge of the clock is in the middle of the transmit data as shown in figure 16 4 0 1 frame D0 D1 D2 D3 D4 D5 D6 D7 0 1...

Page 484: ...Initialization completion Start initialization Set data transfer format in SMR and SCMR 1 Set CKE1 and CKE0 bits in SCR TE and RE bits are 0 No Yes Set value in BRR Clear TE and RE bits in SCR to 0 2 3 Set TE and RE bits in SCR to 1 and set RIE TIE TEIE and MPIE bits 4 1 bit interval elapsed 1 Set the clock selection in SCR Be sure to clear bits RIE TIE TEIE and MPIE and bits TE and RE to 0 When t...

Page 485: ...ultiprocessor bit may be omitted depending on the format and stop bit 4 The SCI checks the TDRE flag at the timing for sending the stop bit 5 If the TDRE flag is 0 the next transmit data is transferred from TDR to TSR the stop bit is sent and then serial transmission of the next frame is started 6 If the TDRE flag is 1 the TEND flag in SSR is set to 1 the stop bit is sent and then the mark state i...

Page 486: ... frame of 1s is output and transmission is enabled 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and clear the TDRE flag to 0 4 Br...

Page 487: ...and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an ERI interrupt request is generated 5 If reception finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request is generated If the RXI interrupt processing routine reads the receive data transferred to RDR b...

Page 488: ...ags RDRF ORER FER PER Receive Data Receive Error Type 1 1 0 0 Lost Overrun error 0 0 1 0 Transferred to RDR Framing error 0 0 0 1 Transferred to RDR Parity error 1 1 1 0 Lost Overrun error framing error 1 1 0 1 Lost Overrun error parity error 0 0 1 1 Transferred to RDR Framing error parity error 1 1 1 1 Lost Overrun error framing error parity error Note The RDRF flag retains the state it had befor...

Page 489: ...orming the appropriate error processing ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by reading the value of the input port corresponding to the RxD pin 4 SCI status check and receive data read Read SSR and check that RDRF 1 then read the receive data in RDR and clea...

Page 490: ...cessing Parity error processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Break PER 1 Clear RE bit in SCR to 0 Figure 16 9 Sample Serial Reception Flowchart 2 ...

Page 491: ...1 multiprocessor bit added to the ID code of the receiving station It then sends transmit data as data with a 0 multiprocessor bit added The receiving station skips data until data with a 1 multiprocessor bit is sent When data with a 1 multiprocessor bit is received the receiving station compares that data with its own ID The station whose ID matches then receives the data sent next Stations whose...

Page 492: ... 03 ID 04 Serial communication line Serial data ID transmission cycle receiving station specification Data transmission cycle Data transmission to receiving station specified by ID MPB 1 MPB 0 H 01 H AA Legend MPB Multiprocessor bit Figure 16 10 Example of Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A ...

Page 493: ...d TEND 1 Break output Clear TDRE flag to 0 1 SCI initialization The TxD pin is automatically designated as the transmit data output pin After the TE bit is set to 1 a frame of 1s is output and transmission is enabled 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR Set the MPBT bit in SSR to 0 or 1 Finally clear the TDRE f...

Page 494: ...bit Stop bit Start bit Data Data 2 Stop bit RXI interrupt request multiprocessor interrupt generated Idle state mark state RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine If not this station s ID MPIE bit is set to 1 again RXI interrupt request is not generated and RDR retains its state ID1 a Data does not match station s ID MPIE RDR value 0 D0 D1 D7 1 1 0 D0 D1 D...

Page 495: ...ck that the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0 If the data is this station s ID clear the RDRF flag to 0 4 SCI status check and data reception Read SSR and check that the RDRF flag is set to 1 then read the data in RDR 5 Receive error processing a...

Page 496: ...rror processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCR to 0 5 Figure 16 13 Sample Multiprocessor Serial Reception Flowchart 2 ...

Page 497: ...are Don t care One unit of transfer data character or frame Bit 0 Serial data Synchronization clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note High except in continuous transfer Figure 16 14 Data Format in Clocked Synchronous Communication LSB First 16 6 1 Clock Either an internal clock generated by the on chip baud rate generator or an external synchronization clock input at the SCK p...

Page 498: ...or set to 1 simultaneously Figure 16 15 Sample SCI Initialization Flowchart 16 6 3 Serial Data Transmission Clocked Synchronous Mode Figure 16 16 shows an example of SCI operation for transmission in clocked synchronous mode In serial transmission the SCI operates as described below 1 The SCI monitors the TDRE flag in SSR and if it is 0 recognizes that data has been written to TDR and transfers th...

Page 499: ...ata transmission Even if the TDRE flag is cleared to 0 transmission will not start while a receive error flag ORER FER or PER is set to 1 Make sure to clear the receive error flags to 0 before starting transmission Note that clearing the RE bit to 0 does not clear the receive error flags Transfer direction Bit 0 Serial data Synchronization clock 1 frame TDRE TEND Data written to TDR and TDRE flag ...

Page 500: ...The TxD pin is automatically designated as the transmit data output pin 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to TDR a...

Page 501: ... finishes successfully the RDRF bit in SSR is set to 1 and receive data is transferred to RDR If the RIE bit in SCR is set to 1 at this time an RXI interrupt request is generated If the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished continuous reception can be enabled Bit 7 Serial data Synchronization clock 1 frame ...

Page 502: ...ng If a receive error occurs read the ORER flag in SSR and after performing the appropriate error processing clear the ORER flag to 0 Transfer cannot be resumed if the ORER flag is set to 1 4 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be iden...

Page 503: ...de to simultaneous transmit and receive mode after checking that the SCI has finished transmission and the TDRE and TEND flags in SSR are set to 1 clear the TE bit in SCR to 0 Then simultaneously set the TE and RE bits to 1 with a single instruction To switch from receive mode to simultaneous transmit and receive mode after checking that the SCI has finished reception clear the RE bit to 0 Then af...

Page 504: ...d the ORER flag in SSR and after performing the appropriate error processing clear the ORER flag to 0 Transmission reception cannot be resumed if the ORER flag is set to 1 4 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI i...

Page 505: ...flag in SSR is set to 1 a TEI interrupt request is generated When the RDRF flag in SSR is set to 1 an RXI interrupt request is generated When the ORER PER or FER flag in SSR is set to 1 an ERI interrupt request is generated A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1 If a TEI interrupt and a TXI interrupt are generated simultaneously the TXI interrupt...

Page 506: ...e error ORER FER PER RXI1 Receive data full RDRF TXI1 Transmit data empty TDRE 1 TEI1 Transmit end TEND ERI2 Receive error ORER FER PER RXI2 Receive data full RDRF TXI2 Transmit data empty TDRE 2 TEI2 Transmit end TEND ERI3 Receive error ORER FER PER RXI3 Receive data full RDRF TXI3 Transmit data empty TDRE 3 TEI3 Transmit end TEND ERI4 Receive error ORER FER PER RXI4 Receive data full RDRF TXI4 T...

Page 507: ...unication line at mark state until the TE bit is set to 1 set both DDR and DR to 1 Since the TE bit is cleared to 0 at this point the TxD pin becomes an I O port and 1 is output from the TxD pin To send a break during serial transmission first set DDR to 1 and DR to 0 and then clear the TE bit to 0 When the TE bit is cleared to 0 the transmitter is initialized regardless of the current transmissio...

Page 508: ... transmission mode initialize the SCI first Figure 16 21 shows a sample flowchart for mode transition during transmission Figures 16 22 and 16 23 show the pin states during transmission Start transmission Transmission 1 No No No Yes Yes Yes Read TEND flag in SSR Make transition to software standby mode etc Cancel software standby mode etc TE 0 Initialization TE 1 2 3 All data transmitted Change op...

Page 509: ...nsition to software standby mode Software standby mode cancelled SCI TxD output Port Port SCI TxD output Last TxD bit retained Note Initialized in software standby mode Figure 16 23 Pin States during Transmission in Clocked Synchronous Mode Internal Clock Reception Before making the transition to module stop software standby watch subactive or subsleep mode stop reception RE 0 RSR RDR and SSR are ...

Page 510: ...RDR Read RDRF flag in SSR Make transition to software standby mode etc Cancel software standby mode etc RE 0 Initialization RE 1 2 Change operating mode RDRF 1 1 Data being received will be invalid 2 Module stop mode is included Figure 16 24 Sample Flowchart for Mode Transition during Reception ...

Page 511: ...ure 16 25 Switching from SCK Pins to Port Pins To prevent the low pulse output that is generated when switching the SCK pins to the port pins specify the SCK pins for input pull up the SCK port pins externally and follow the procedure below with DDR 1 DR 1 C A 1 CKE1 0 CKE0 0 and TE 1 1 End serial data transmission 2 TE bit 0 3 CKE1 bit 1 4 C A bit 0 switch to port output 5 CKE1 bit 0 SCK Port CKE...

Page 512: ...Rev 1 00 09 03 page 474 of 704 ...

Page 513: ...uous transmission reception can be performed Start and stop conditions generated automatically in master mode Selection of acknowledge output levels when receiving Automatic loading of acknowledge bit when transmitting Bit synchronization wait function In master mode the state of the SCL is monitored per bit and the timing is synchronized automatically If transfer is not ready set the SCL to low u...

Page 514: ... control Transmission reception control circuit ICCRB ICMR ICSR ICIER ICDRR ICDRS ICDRT I2 C bus control register A I2 C bus control register B I2 C mode register I2 C status register I2 C interrupt enable register I2 C transmit data register I2 C receive data register I2 C bus shift register Slave address register Legend ICCRA ICCRB ICMR ICSR ICIER ICDRT ICDRR ICDRS SAR SAR SDA Internal data bus ...

Page 515: ...Rev 1 00 09 03 page 477 of 704 Vcc Vcc SCL in SCL SDA in SDA SCL Master Slave 1 Slave 2 SDA SCL in SCL SDA in SDA SCL in SCL SDA in SDA Figure 17 2 External Circuit Connections of I O Pins ...

Page 516: ...lock SCL3 I O IIC3_3 serial clock input output Serial data SDA3 I O IIC3_3 serial data input output Note The pin symbols are represented as SCL and SDA channel numbers are omitted in this manual 17 3 Register Descriptions The IIC3 has the following registers for each channel I 2 C bus control register A ICCRA I 2 C bus control register B ICCRB I 2 C bus mode register ICMR I 2 C bus interrupt enabl...

Page 517: ...en TRS is 0 and ICDRR is read 0 Enables next reception 1 Disables next reception 5 4 MST TRS 0 0 R W R W Master Slave Select Transmit Receive Select When arbitration is lost in master mode MST and TRS are both reset by hardware causing a transition to slave receive mode Modification of the TRS bit should be made between transfer frames Operating modes are described below according to MST and TRS c...

Page 518: ... 3 2 I 2 C Bus Control Register B ICCRB ICCRB issues start stop conditions manipulates the SDA pin monitors the SCL pin and controls a reset in IIC control Bit Bit Name Initial Value R W Description 7 BBSY 0 R W Bus Busy There are two functions a flag function which indicates whether the I 2 C bus is occupied or released and a function which issues start and stop conditions in master mode This bit...

Page 519: ... reading and the SDAO bit is 1 the SDA pin outputs high When reading and the SDAO bit is 0 the SDA pin outputs low 4 1 R W Reserved The write value should always be 1 3 SCLO 1 R Monitors the SCL output level When reading and the SCLO bit is 1 the SCL pin outputs high When reading and the SCLO bit is 0 the SCL pin outputs low 2 1 Reserved This bit is always read as 1 1 IICRST 0 R W IIC Control Part...

Page 520: ...1 after the fall of the clock for the last data bit low period is extended for two transfer clocks If the WAIT bit is cleared to 0 data and acknowledge bits are transferred consecutively with no wait inserted The setting of this bit is invalid in slave mode 5 4 1 1 Reserved These bits are always read as 1 3 BCWP 1 R W BC Write Protect Controls the BC2 to BC0 modifications When modifying the BC2 to...

Page 521: ...4 I 2 C Bus Interrupt Enable Register ICIER ICIER enables or disables interrupt sources and acknowledge bits sets acknowledge bits to be transmitted and confirms acknowledge bits to be received Bit Bit Name Initial Value R W Description 7 TIE 0 R W Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1 this bit enables or disables the transmit data empty interrupt TXI 0 Transmit data empt...

Page 522: ...e interrupt request NAKI is disabled 1 NACK receive interrupt request NAKI is enabled 3 STIE 0 R W Stop Condition Detection Interrupt Enable 0 Stop condition detection interrupt request STPI is disabled 1 Stop condition detection interrupt request STPI is enabled 2 ACKE 0 R W Acknowledge Bit Determination Select 0 The value of the acknowledge bit is ignored and continuous transfer is performed 1 I...

Page 523: ...Setting condition When the ninth clock of SCL rises while the TDRE flag is 1 Clearing conditions When 0 is written to TEND after reading TEND 1 When data is written to ICDRT 5 RDRF 0 R W Receive Data Full Setting condition When receive data is transferred from ICDRS to ICDRR Clearing conditions When 0 is written to RDRF after reading RDRF 1 When data is read from ICDRR 4 NACKF 0 R W No Acknowledge...

Page 524: ...ernal SDA and SDA pin does not match at the rise of SCL in master transmit mode When the SDA pin goes high in master mode while a start condition is detected Clearing condition When 0 is written to AL after reading AL 1 1 AAS 0 R W Slave Address Recognition Flag In slave receive mode this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR Setting condi...

Page 525: ...served This bit is readable writable The write value should always be 0 17 3 7 Slave Address Register A SARA SARA sets slave addresses When the chip is in slave mode if the upper 7 bits in SARA match the upper 7 bits of the first frame received after a start condition the chip operates as the slave device Bit Bit Name Initial Value R W Description 7 to 1 SVA6 to SVA0 All 0 R W Slave Address 6 to 0...

Page 526: ...ng of transmit modes in slave mode Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 MSA6 MSA5 MSA4 MSA3 MSA2 MSA1 MSA0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W Slave Address Mask 6 to 0 Correspond to the SVA6 to SVA0 bits in SAR and control comparison conditions for addresses set in SAR and addresses of upper 7 bits of the first frame received after a start condition in slave mode 0 Compa...

Page 527: ...ndition When the slave address is detected in slave receive mode Clearing condition When 0 is written to AASB after reading AASB 1 5 to 0 All 0 Reserved These bits are always read as 0 17 3 11 I 2 C Bus Transmit Data Register ICDRT ICDRT is an 8 bit readable writable register that stores the transmit data When ICDRT detects the space in the I 2 C bus shift register ICDRS it transfers the transmit ...

Page 528: ... is a register that is used to transfer receive data In transmission data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin In reception data is transferred from ICDRS to ICDRR after one byte of data is received This register cannot be read from the CPU ...

Page 529: ... R A DATA A A P 1 1 1 1 n 7 1 m a I2C bus format b I2C bus format start condition retransmission Transfer bit count n 1 to 8 Transfer frame count m 1 S SLA R A DATA 1 1 1 n1 7 1 m1 S SLA R A DATA A P 1 1 1 n2 7 1 m2 1 1 1 A Upper row Transfer bit count n1 n2 1 to 8 Lower row Transfer frame count m1 m2 1 1 1 Figure 17 3 I 2 C Bus Formats SDA SCL S 1 7 SLA 8 R 9 A 1 7 DATA 8 9 1 7 8 9 A DATA P A Fig...

Page 530: ...sing the MOV instruction Start condition issued This generates the start condition 3 After confirming that TDRE in ICSR has been set write the transmit data the first byte data show the slave address and R W to ICDRT At this time TDRE is automatically cleared to 0 then data is transferred from ICDRT to ICDRS TDRE is set again 4 When transmission of one byte data is completed while TDRE is 1 TEND i...

Page 531: ... Address R Data 1 Data 1 Data 2 Address R Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 1 2 3 4 5 6 7 8 9 A R Figure 17 5 Operation Timing in Master Transmit Mode 1 TDRE 6 Issue stop condition Clear TEND 7 Set slave receive mode TEND ICDRT ICDRS 1 9 2 3 4 5 6 7 8 9 A A SCL master output SDA master output SDA slave output Bit 7 Bit 6 Data n Data n Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 Wri...

Page 532: ...to SDA at the 9th receive clock pulse 3 After the reception of one frame data is completed the RDRF bit in ICSR is set to 1 at the rise of 9th receive clock pulse At this time the received data can be read by reading ICDRR and at the same time the RDRF bit is cleared to 0 4 The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time RDRF is set If the 8th receive clock...

Page 533: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 User processing Data 1 Data 1 Figure 17 7 Operation Timing in Master Receive Mode 1 RDRF RCVD ICDRS ICDRR Data n 1 Data n Data n Data n 1 5 Read ICDRR after setting RCVD 6 Issue stop condition 7 Read ICDRR and clear RCVD 8 Set slave receive mode 1 9 2 3 4 5 6 7 8 9 A A SCL master output SDA master output SDA slave output Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit...

Page 534: ...slave receive mode and wait until the slave address matches 2 When the slave address matches in the first frame following detection of the start condition the slave device outputs the level specified by ACKBT in ICIER to SDA at the rise of the 9th clock pulse At this time if the 8th bit data R W is 1 the TRS in ICCRA and TDRE in ICSR are set to 1 and the mode changes to slave transmit mode automat...

Page 535: ...mode Slave transmit mode SDA master output SDA slave output SCL slave output Bit 7 Bit 7 Data 1 Data 1 Data 2 Data 3 Data 2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 Write data to ICDRT data 1 2 Write data to ICDRT data 2 2 Write data to ICDRT data 3 User processing Figure 17 9 Operation Timing in Slave Transmit Mode 1 ...

Page 536: ...ure and operations in slave receive mode are described below 1 Set the ICE bit in ICCRA to 1 Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in ICCRA to 1 initial setting Set the MST and TRS bits in ICCRA to select slave receive mode and wait until the slave address matches 2 When the slave address matches in the first frame following detection of the start condition the slave device outputs th...

Page 537: ...Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2 Read ICDRR dummy read 2 Read ICDRR User processing Figure 17 11 Operation Timing in Slave Receive Mode 1 ICDRS ICDRR 1 2 3 4 5 6 7 8 9 9 A A RDRF SCL master output SDA master output SDA slave output SCL slave output User processing Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 1 3 Set ACKBT 3 Read ICDRR 4 Read ICDRR Data 2 Data 1 Figure 17 12 Operation ...

Page 538: ...nput signal is sampled on the system clock but is not passed forward to the next circuit unless the outputs of both latches match If they do not match the previous value is retained C Q D Match detector Internal SCL or SDA signal SCL or SDA input signal Sampling clock Sampling clock System clock cycle Latch Latch C Q D Figure 17 13 Block Diagram of Noise Canceler 17 4 7 Example of Use Flowcharts i...

Page 539: ... No No No No Yes Yes TEND 1 Yes Yes Yes 1 Test the status of the SCL and SDA lines 2 Set master transmit mode 3 Start condition issuance 4 Set transmit data for the first byte slave address R W 5 Wait for 1 byte to be transmitted 6 Test the acknowledge bit transferred from the specified slave device 7 Set transmit data for the second and subsequent data except for the last byte 8 Wait for ICDRT em...

Page 540: ...lear TDRE 2 Set acknowledge to the transmit device 3 Dummy reading of ICDDR 4 Wait for 1 byte to be received 5 Check if last receive 1 6 Read the receive data 7 Set acknowledge of the last byte Disable continuous reception RCVD 1 8 Read receive data of last byte 1 9 Wait for the last byte to be received 10 Clear STOP flag 11 Stop condition issuance 12 Wait for the generation of stop condition 13 R...

Page 541: ...my reading of ICDRR Clear TDRE in ICSR End 1 Clear the AAS flag 2 Set transmit data to ICDRT except for the last byte 3 Wait for ICDRT empty 4 Set the last byte of the transmit data 5 Wait the transmission end of the last byte 6 Clear the TEND flag 7 Set slave receive mode 8 Dummy reading of ICDRR to release the SCL line 9 Clear the TDRE flag No No Yes TEND 1 1 2 3 4 5 6 7 8 9 Figure 17 16 Sample ...

Page 542: ...d ICDRR End No Yes 1 2 3 4 5 6 7 8 9 10 1 Clear the AAS flag 2 Set the acknowledge for the transmit device 3 Dummy reading of ICDRR 4 Wait the reception end of 1 byte 5 Test the last receive 1 6 Read the received data 7 Set the acknowledge for the last byte 8 Read the received data of the last byte 1 9 Wait the reception end of the last byte 10 Read the received data of the last byte Figure 17 17 ...

Page 543: ...STOP recognition and arbitration lost Table 17 3 shows the contents of each interrupt request Table 17 3 Interrupt Requests Interrupt Request Abbreviation Interrupt Condition Transmit data empty TXI TDRE 1 TIE 1 Transmit end TEI TEND 1 TEIE 1 Receive data full RXI RDRF 1 RIE 1 STOP recognition STPI STOP 1 STIE 1 NACK detection Arbitration lost NAKI NACKF 1 AL 1 NAKIE 1 ...

Page 544: ...ort in the two states described above Therefore it monitors the SCL and communicates by bits with synchronization Figure 17 18 shows the timing of the bit synchronous circuit and table 17 4 shows the time when SCL output changes from low to Hi Z then the SCL is monitored SCL VIH Reference clock for SCL monitor timing Internal SCL Figure 17 18 Timing of Bit Synchronous Circuit Table 17 4 Time for M...

Page 545: ...channel min Two kinds of operating modes Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels or 1 to 8 channels Eight data registers Conversion results are retained in a 16 bit data register for each channel Sample and hold function Three kinds of conversion start Conversion can be started by software conversion start trigger by 16 bit timer pulse unit ...

Page 546: ... AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 Conversion start trigger from 8 bit timer or TPU Successive approximations register Multiplexer Legend ADCR A D control register ADCSR A D control status register ADDRA A D data register A ADDRB A D data register B ADDRC A D data register C ADDRD A D data register D ADDRE A D data register E ADDRF A D data register F ADDRG A D data...

Page 547: ...VSS Input Analog block ground Reference voltage pin Vref Input A D conversion reference voltage Analog input pin 0 AN0 Input Analog inputs for channel set 0 Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Analog input pin 5 AN5 Input Analog input pin 6 AN6 Input Analog input pin 7 AN7 Input Analog input pin 8 AN8 Input Analog inpu...

Page 548: ...read only ADDR registers ADDRA to ADDRH used to store the results of A D conversion ADDR which store a conversion result for each channel are shown in table 18 2 The converted 10 bit data is stored in bits 15 to 6 The lower 6 bit data is always read as 0 The data bus between the CPU and the A D converter is 16 bit width ADDR can be read directly from the CPU Table 18 2 Analog Input Channels and Co...

Page 549: ...ADF bit when this bit is set to 1 5 ADST 0 R W A D Start Clearing this bit to 0 stops A D conversion and the A D converter enters the wait state When this bit is set to 1 by software conversion start trigger by the TPU or TMR or ADTRG pin A D conversion starts This bit remains set to 1 during A D conversion In single mode this bit is cleared to 0 automatically when conversion on the specified chan...

Page 550: ...N13 0110 AN6 1110 AN14 0111 AN7 1111 AN15 When SCANE 1 and SCANS 0 0000 AN0 1000 AN8 0001 AN0 and AN1 1001 AN8 and AN9 0010 AN0 to AN2 1010 AN8 to AN10 0011 AN0 to AN3 1011 AN8 to AN11 0100 AN4 1100 AN12 0101 AN4 and AN5 1101 AN12 and AN13 0110 AN4 to AN6 1110 AN12 to AN14 0111 AN4 to AN7 1111 AN12 to AN15 When SCANE 1 and SCANS 1 0000 AN0 1000 AN8 0001 AN0 and AN1 1001 AN8 and AN9 0010 AN0 to AN2...

Page 551: ... A D conversion start by ADTRG pin is enabled 5 4 SCANE SCANS 0 0 R W R W Scan Mode Select single mode or scan mode as the A D conversion operating mode 0x Single mode 10 Scan mode A D conversion is performed continuously for channels 1 to 4 11 Scan mode A D conversion is performed continuously for channels 1 to 8 3 2 CKS1 CKS0 0 0 R W R W Clock Select 1 and 0 Set the A D conversion time Only set ...

Page 552: ...nversion A D conversion stops and the A D converter enters the wait state 18 4 2 Scan Mode In scan mode A D conversion is to be performed sequentially on the specified channels maximum four channels or maximum eight channels Operations are as follows 1 When the ADST bit in ADCSR is set to 1 by software TPU or external trigger input A D conversion starts on the first channel in the specified channe...

Page 553: ... is set to 1 then starts conversion Figure 18 2 shows the A D conversion timing Table 18 3 shows the A D conversion time As shown in figure 18 2 the A D conversion time tCONV includes tD and the input sampling time tSPL The length of tD varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in tables 18 3 In scan mode the ...

Page 554: ...r of states Table 18 4 A D Conversion Time Scan Mode CKS1 CKS0 Conversion Time State 0 512 Fixed 0 1 256 Fixed 0 128 Fixed 1 1 64 Fixed 18 4 4 External Trigger Input Timing A D conversion can be started by an external trigger input When the TRGS1 and TRGS0 bits in ADCR are set to 11 an external trigger input is enabled at the ADTRG pin A falling edge at the ADTRG pin sets the ADST bit in ADCSR to ...

Page 555: ...urce The A D converter generates an A D conversion end interrupt ADI at the end of A D conversion Setting the ADIE bit to 1 enables an ADI interrupt request while the ADF bit in ADCSR is set to 1 after A D conversion is completed Table 18 5 A D Converter Interrupt Source Name Interrupt Source Interrupt Flag ADI End of A D conversion ADF ...

Page 556: ...ue B 0000000000 H 000 to B 0000000001 H 001 see figure 18 5 Full scale error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the digital output changes from B 1111111110 H 3FE to B 1111111111 H 3FF see figure 18 5 Nonlinearity error The error with respect to the ideal A D conversion characteristic between the zero voltage and the full scale voltage...

Page 557: ...tal output Ideal A D conversion characteristic Analog input voltage Figure 18 4 A D Conversion Accuracy Definitions FS Digital output Ideal A D conversion characteristic Nonlinearity error Analog input voltage Offset error Actual A D conversion characteristic Full scale error Figure 18 5 A D Conversion Accuracy Definitions ...

Page 558: ...hin the sampling time if the sensor output impedance exceeds 5 kΩ charging may be insufficient and it may not be possible to guarantee the A D conversion accuracy However if a large capacitance is provided externally for conversion in single mode the input load will essentially comprise only the internal input resistance of 10 kΩ and the signal source impedance is ignored However since a low pass ...

Page 559: ...the Vref pin should be set in the range Vref AVcc 18 7 5 Notes on Board Design In board design digital circuitry and analog circuitry should be as mutually isolated as possible and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible Failure to do so may result in incorrect operation of the analog circuitr...

Page 560: ...uit in the A D converter exceeds the current input via the input impedance Rin an error will arise in the analog input pin voltage Careful consideration is therefore required when deciding the circuit constants AVCC 1 1 Vref AN0 to AN15 AVSS Notes Values are reference values 1 2 Rin Input impedance Rin 2 100 0 1 µF 0 01 µF 10 µF Figure 18 7 Example of Analog Input Protection Circuit Table 18 6 Ana...

Page 561: ...RAM The RAM is connected to the CPU by a 16 bit data bus enabling one state access by the CPU to both byte data and word data The on chip RAM can be enabled or disabled by means of the RAME bit in the system control register SYSCR For details on SYSCR see section 3 2 2 System Control Register SYSCR ...

Page 562: ...Rev 1 00 09 03 page 524 of 704 ...

Page 563: ... kbytes Programming erasing interface by the download of on chip program This LSI has a dedicated programming erasing program After downloading this program to the on chip RAM programming erasing can be performed by setting the argument parameter Programming erasing time The flash memory programming time is 3 ms typ in 128 byte simultaneous programming and approximately 25 µs per byte The erasing ...

Page 564: ... User MAT 256 kbytes User boot MAT 8 kbytes Operating mode Module bus FWE pin Mode pin Internal address bus Internal data bus 16 bits Legend FCCS Flash code control status register FPCS Flash program code select register FECS Flash erase code select register FKEY Flash key code register FMATS Flash MAT select register FTDAR Flash transfer destination address register To read from or write to the r...

Page 565: ...ry can be read programmed or erased on the board only in boot mode user program mode and user boot mode Flash memory can be read programmed or erased by means of the PROM programmer in programmer mode Reset state Programmer mode User mode User program mode User boot mode Boot mode On board programming mode 0 0 User mode setting U s e r b o o t m o d e s e t t i n g 0 Boot mode setting 0 0 Programm...

Page 566: ...de Changing mode setting and reset Changing FLSHE bit and FWE pin Changing mode setting and reset Notes 1 All erasure is performed After that the specified block can be erased 2 Firstly the reset vector is fetched from the embedded program storage MAT After the flash memory related registers are checked the reset vector is fetched from the user boot MAT The user boot MAT can be programmed or erase...

Page 567: ... must be switched by using FMATS The user MAT or user boot MAT can be read in all modes However the user boot MAT can be programmed only in boot mode and programmer mode User MAT User Boot MAT Address H 000000 Address H 03FFFF Address H 000000 Address H 001FFF 256 kbytes 8 kbytes Figure 20 3 Flash Memory Configuration The size of the user MAT is different from that of the user boot MAT An address ...

Page 568: ...ming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes Programming unit 128 bytes H 001000 H 001001 H 001002 H 002000 H 002001 H 002002 H 003000 H 003001 H 003002 H 004000 H 004001 H 004002 H 00C000 H 00C001 H 00C002 H 00D000 H 00D001 H 00D002 H 00E000 H 00E001 H 00E002 H ...

Page 569: ...dure program for programming erasing End user procedure program Yes Programming in 128 byte units or erasing in one block units downloaded program execution Download on chip program by setting FKEY and SCO bits No Programming erasing completed Figure 20 5 Overview of User Procedure Program 1 Selection of On chip Program to be Downloaded For programming erasing execution the FLSHE bit in SYSCR must...

Page 570: ...n SYSCR and the FWE pin must be set to 1 to make a transition to user program mode The program data programming destination address is specified in 128 byte units when programming The block to be erased is specified in erase block units when erasing These specifications are set by using the programming erasing interface parameter and the on chip program is initiated The on chip program is executed...

Page 571: ... on SYSCR see section 3 2 2 System Control Register SYSCR Flash code control status register FCCS Flash program code select register FPCS Flash erase code select register FECS Flash key code register FKEY Flash MAT select register FMATS Flash transfer destination address register FTDAR Download pass fail result DPFR Flash pass fail result FPFR Flash multipurpose address area FMPAR Flash multipurpo...

Page 572: ...nterface Parameters FEBS Notes 1 The setting is required when programming or erasing the user MAT in user boot mode 2 The setting may be required according to the combination of initiation mode and read target MAT 20 3 1 Programming Erasing Interface Registers The programming erasing interface registers are described below They are all 8 bit registers that can be accessed only in bytes These regis...

Page 573: ...o 1 flash memory enters the error protection state When this bit is set to 1 high voltage is applied to the internal flash memory To reduce the damage to flash memory the reset must be released after the reset period of 100 µs which is longer than normal 0 Flash memory operates normally Programming erasing protection for flash memory error protection is invalid Clearing condition By a reset or in ...

Page 574: ... the interrupt exception handling cannot be guaranteed An occurrence of any interrupts should be masked 1 The space for the interrupt vector table is modified Even when interrupt vector data is not read successfully the interrupt exception handling up to vector number 31 is enabled 2 1 All 0 R W Reserved The initial value should not be changed 0 SCO 0 R W Source Program Copy Operation Requests the...

Page 575: ...5 is written to FKEY During execution in the on chip RAM Note This bit is a write only bit This bit is always read as 0 2 Flash Program Code Select Register FPCS FPCS selects the on chip programming program to be downloaded Bit Bit Name Initial Value R W Description 7 to 1 All 0 R W Reserved The initial value should not be changed 0 PPVS 0 R W Program Pulse Verify Selects the programming program 0...

Page 576: ...loaded programming erasing program these processing cannot be executed if the key code is not written Bit Bit Name Initial Value R W Description 7 6 5 4 3 2 1 0 K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Key Code Only when H A5 is written writing to the SCO bit is valid When the value other than H A5 is written to FKEY the SCO bit cannot be set to 1 Therefore downloadi...

Page 577: ...e to FMATS When the MAT is switched follow section 20 6 Switching between User MAT and User Boot MAT The user boot MAT cannot be programmed in user program mode if user boot MAT is selected by FMATS The user boot MAT must be programmed in boot mode or in programmer mode H AA The user boot MAT is selected in user MAT selection state when the value of these bits are other than H AA Initial value whe...

Page 578: ...e SCO bit to 1 and the value specified by bits TDA6 to TDA0 is within the range of H 00 to H 03 0 The value specified by bits TDA6 to TDA0 is within the range 1 The value specified by bits TDA6 to TDA0 is over the range H 04 to H FF and the download is stopped 6 5 4 3 2 1 0 TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W Transfer Destination Address Specify the start a...

Page 579: ...he CPU except for R0L are stored The return value of the processing result is written to R0L Since the stack area is used for storing the registers except for R0L the stack area must be saved at the processing start A maximum size of stack area to be used is 128 bytes The programming erasing interface parameters are used in the following four items 1 Download control 2 Initialization before progra...

Page 580: ... 1 Download Control The on chip program is automatically downloaded by setting the SCO bit to 1 The on chip RAM area to be downloaded is the 2 kbyte area starting from the address specified by FTDAR Download control is set by the programming erasing interface registers and DPFR indicates the return value a Download Pass Fail Result Parameter DPFR Single Byte of On Chip RAM Start Address Specified ...

Page 581: ...ended normally or not The determination result whether program that is downloaded to the on chip RAM is read back and then transferred to the on chip RAM is returned 0 Downloading on chip program is ended normally no error 1 Downloading on chip program is ended abnormally error occurs 2 Programming Erasing Initialization The on chip programming erasing program to be downloaded includes the initial...

Page 582: ...mber to three decimal places and be shown in a number of two decimal places The value multiplied by 100 is converted to the binary digit and is written to FPEFEQ general register ER0 For example when the operating frequency of the CPU is 20 000 MHz the value is as follows The number to three decimal places of 20 000 is rounded and the value is thus 20 00 The formula that 20 00 100 2000 is converte...

Page 583: ... area parameter FMPAR Since program data is always in 128 bytes the lower eight bits A7 to A0 must be H 00 or H 80 as the boundary of the programming start address in the user MAT 2 The program data for the user MAT must be prepared in the consecutive area The program data must be in the consecutive space which can be accessed by using the MOV B instruction of the CPU and in other than the flash m...

Page 584: ...Therefore the specified programming start address becomes a 128 byte boundary and bits MOA6 to MOA0 are always 0 b Flash Multipurpose Data Destination Parameter FMPDR General Register ER0 of CPU FMPDR sets the start address in the area which stores the data to be programmed to the user MAT When the storage destination of the program data is in flash memory an error occurs The error occurrence is i...

Page 585: ...e performed FWE 0 or FLER 1 5 EE R W Error Detect During Programming Execution 1 is returned to this bit when the specified data could not be written because the user MAT was not erased If this bit is set to 1 there is a high possibility that the user MAT is partially reprogrammed In this case after removing the error source erase the user MAT If FMATS is set to H AA and the user boot MAT is selec...

Page 586: ... the following items are specified as the start address of the programming destination an error occurs When the programming destination address in the area other than flash memory is specified When the specified address is not in a 128 byte boundary The lower eight bits of the address are other than H 00 and H 80 0 Setting of programming destination address is normal 1 Setting of programming desti...

Page 587: ...a Flash Erase Block Select Parameter FEBS General Register ER0 of CPU FEBS specifies the erase block number The several block numbers cannot be specified Bit Bit Name Initial Value R W Description 31 to 12 Unused These bits should be cleared to 0 11 10 9 8 7 6 5 4 3 2 1 0 EB11 EB10 EB9 EB8 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 R W R W R W R W R W R W R W R W R W R W R W R W Erase Block Set the erase blo...

Page 588: ...or Detect 1 is returned to this bit when the user MAT could not be erased or when flash memory related register settings are partially changed If this bit is set to 1 there is a high possibility that the user MAT is partially erased In this case after removing the error source erase the user MAT If FMATS is set to H AA and the user boot MAT is selected an error occurs when erasure is performed In ...

Page 589: ... flash memory see figure 20 2 Table 20 5 Setting On Board Programming Mode Mode Setting FWE MD2 MD1 MD0 Boot mode 1 0 0 1 User program mode 1 1 1 1 User boot mode 1 1 0 1 Note Before downloading the programming erasing programs the FLSHE bit must be set to 1 to make a transition to user program mode 20 4 1 Boot Mode Boot mode executes programming erasing the user MAT and user boot MAT by the metho...

Page 590: ...rate which is transmitted by the host according to the measured low period and transmits the bit adjustment end sign 1 byte of H 00 to the host The host must confirm that this bit adjustment end sign H 00 has been received normally and transmit 1 byte of H 55 to this LSI When reception is not performed normally boot mode is initiated again reset and the operation described above must be executed T...

Page 591: ...amming command When programming is finished the programming start address must be set to H FFFFFFFF and transmitted Then the state for waiting program data is returned to the state for waiting programming erasing command When the erasure preparation notice is received the state for waiting erase block data is entered The erase block number must be transmitted following the erasing command When the...

Page 592: ...ent Processing of inquiry setting command All user MAT and user boot MAT erasure Wait for program data Wait for erase block data Read check command reception Command response Program selection command reception Program data transmission Erasure selection command reception Program completed Erase block specification Erasure completed Inquiry command reception H 55 reception Inquiry command response...

Page 593: ...eased after the reset input period of 100 µs which is longer than normal When programming program data is prepared Programming erasing procedure program is transferred to the on chip RAM and executed Programming erasing start Programming erasing end Make sure that program data will not overlap the download destination specified by FTDAR The FWE bit is set to 1 by inputting a high level signal to t...

Page 594: ...rolled so that these programs do not overlap Figure 20 10 shows the program area to be downloaded System use area 15 bytes On chip RAM Address Area to be downloaded Size 2 kbytes Not available during programming erasing processing period Area that can be used by user DPFR Return value 1 byte Programming erasing program entry Initialization program entry Initialization programming program or Initia...

Page 595: ... 7 8 9 10 11 12 13 14 15 1 1 3 Download Initialization Programming Initialization JSR FTDAR setting 32 Initialization error processing Set parameters to ER1 and ER0 FMPAR and FMPDR Start programming procedure program Figure 20 11 Programming Procedure The procedure program must be executed in an area other than the flash memory to be programmed Especially the part where the SCO bit in FCCS is set ...

Page 596: ...o FKEY B The SCO bit writing is executed in the on chip RAM When the SCO bit is set to 1 download is started automatically When the user procedure program is returned the SCO bit is cleared to 0 Therefore the SCO bit cannot be confirmed to be 1 in the user procedure program The download result can be confirmed only by the return value of DPFR Before the SCO bit is set to 1 incorrect determination ...

Page 597: ...load destination in FTDAR may be abnormal In this case confirm the setting of the TDER bit in FTDAR If the value of DPFR is different from that before downloading check the SS and FK bits in DPFR to ensure that the download program selection and FKEY setting were normal respectively 6 Set the operating frequency to FPEFEQ for initialization The current frequency of the CPU clock is set to FPEFEQ g...

Page 598: ...n the user system The interrupts that are retained must be executed after all program processing 10 Set FKEY to H 5A to enable the user MAT programming 11 Set the parameter which is required for programming The start address of the programming destination of the user MAT FMPAR is set to the general register ER1 The start address of the program data area FMPDR is set to the general register ER0 Exa...

Page 599: ...f the necessary data has finished If more than 128 bytes of data needs to be programmed specify FMPAR and FMPDR in 128 byte units and repeat steps 12 to 14 Increment the programming destination address by 128 bytes and update the programming data pointer correctly If an address which has already been programmed is programmed again not only will a programming error occur but also flash memory will ...

Page 600: ...Y to 0 1 2 3 4 5 6 1 1 Download Initialization Erasing Initialization JSR FTDAR setting 32 Erasing JSR FTDAR setting 16 Select on chip program to be downloaded and specify download destination by FTDAR Start erasing procedure program Figure 20 12 Erasing Procedure The procedure program must be executed in an area other than the user MAT to be erased Especially the part where the SCO bit in FCCS is...

Page 601: ...user MAT is set no block is erased even though the erasing program is executed and an error is returned to the return value parameter FPFR 3 Execute erasing Similar to as in programming there is an entry point of the erasing program in the area from the start address of a download destination specified by FTDAR 16 bytes of on chip RAM The subroutine should be called and erasing should be executed ...

Page 602: ...g program Set FMPDR to program relevant block execute programming program Confirm operation End Figure 20 13 Repeating Procedure of Erasing and Programming In the above procedure download and initialization are performed only once at the beginning In this kind of operation note the following Be careful not to damage on chip RAM with overlapped settings In addition to the erasing program area and p...

Page 603: ... user boot mode the built in check routine runs The user MAT and user boot MAT states are checked by this check routine While the check routine is running NMI and all other interrupts cannot be accepted Next processing starts from the execution start address of the reset vector in the user boot MAT At this point H AA is set to FMATS because the execution MAT is the user boot MAT 2 User MAT Program...

Page 604: ...ect on chip program to be downloaded and specify download destination by FTDAR Figure 20 14 Procedure for Programming User MAT in User Boot Mode The difference between the programming procedures in user program mode and user boot mode is whether the MAT is switched or not as shown in figure 20 14 In user boot mode the user boot MAT can be seen in the flash memory space with the user MAT hidden in ...

Page 605: ...ownload error processing Set the FPEFEQ parameter End erasing procedure program FPFR 0 Initialization error processing Disable interrupts and bus master operation other than CPU Clear FKEY to 0 Set FEBS parameter Yes No Clear FKEY and erasing error processing Yes Required block erasing is completed No Set FKEY to H 5A Clear FKEY to 0 1 1 Download Initialization Erasing Set FMATS to value other tha...

Page 606: ... following conditions 1 Conditions that Apply to Programming Erasing 1 The on chip programming erasing program is downloaded from the address in the on chip RAM specified by FTDAR therefore this area is not available for use 2 The on chip programming erasing program will use 128 bytes at the maximum as a stack So make sure that this area is secured 3 Download by setting the SCO bit to 1 will lead ...

Page 607: ... which MAT is selected when switching between them 8 When the data storable area indicated by programming parameter FMPDR is within the flash memory area an error will occur even when the data stored is normal Therefore the data should be transferred to the on chip RAM to place the address indicated by FMPDR in an area other than the flash memory In consideration of these conditions there are thre...

Page 608: ...n chip program to be downloaded Operation for writing H A5 to FKEY Execution of writing SCO 1 in FCCS download Operation for FKEY clear Determination of download result Operation for download error Operation for settings of initialization parameter Execution of initialization Determination of initialization result Operation for initialization error NMI handling routine Operation for disabling inte...

Page 609: ...m On chip RAM User MAT External Space Extended Mode User MAT Embedded Program Storage MAT Execution of programming Determination of program result Operation for program error Operation for FKEY clear Note Transferring the data to the on chip RAM enables this area to be used ...

Page 610: ...r writing H A5 to FKEY Execution of writing SCO 1 in FCCS download Operation for FKEY clear Determination of download result Operation for download error Operation for settings of initialization parameter Execution of initialization Determination of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupt Operation for writing H 5A to FKEY Ope...

Page 611: ...00 09 03 page 573 of 704 Storable Executable Area Selected MAT Item On chip RAM User MAT External Space Extended Mode User MAT Embedded Program Storage MAT Operation for erasure error Operation for FKEY clear ...

Page 612: ... for selection of on chip program to be downloaded Operation for writing H A5 to FKEY Execution of writing SCO 1 in FCCS download Operation for FKEY clear Determination of download result Operation for download error Operation for settings of initialization parameter Execution of initialization Determination of initialization result Operation for initialization error NMI handling routine Operation...

Page 613: ... Embedded Program Storage MAT Operation for settings of program parameter Execution of programming Determination of program result Operation for program error 2 Operation for FKEY clear Switching MATs by FMATS Notes 1 Transferring the data to the on chip RAM enables this area to be used 2 Switching FMATS in the on chip RAM enables this area to be used ...

Page 614: ...downloaded Operation for writing H A5 to FKEY Execution of writing SCO 1 in FCCS download Operation for FKEY clear Determination of download result Operation for download error Operation for settings of initialization parameter Execution of initialization Determination of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupt Switching MATs ...

Page 615: ...r Boot MAT External Space Extended Mode User MAT User Boot MAT Embedded Program Storage MAT Execution of erasure Determination of erasure result Operation for erasure error Operation for FKEY clear Switching MATs by FMATS Note Switching FMATS in the on chip RAM enables this area to be used ...

Page 616: ...ase FWE pin protection When a low level signal is input to the FWE pin the FWE bit in FCCS is cleared and the program erase protected state is entered Reset standby protection The program erase interface registers are initialized by a reset including a reset by the WDT and in hardware standby mode and the program erase protected state is entered The reset state will not be entered by a reset using...

Page 617: ...cedures for programming erasing Forcibly suspending programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing If the microcomputer malfunctions during programming erasing of the flash memory the FLER bit in FCCS is set to 1 and the error protection state is entered and this suspends the programming or erasure The FLER bit is set in the followi...

Page 618: ... the user boot MAT should take place in boot mode or programmer mode 1 MAT switching by FMATS should always be executed in the on chip RAM 2 To ensure that the MAT that has been switched to is accessible execute four NOP instructions in the on chip RAM immediately after writing to FMATS in the on chip RAM this prevents access to the flash memory during MAT switching 3 If an interrupt has occurred ...

Page 619: ... for switching to the user boot MAT 1 Mask interrupts 2 Write H AA to FMATS 3 Execute four NOP instructions before accessing the user boot MAT Procedure for switching to the user MAT 1 Mask interrupts 2 Write a value other than H AA to FMATS 3 Execute four NOP instructions before accessing the user MAT Figure 20 17 Switching between User MAT and User Boot MAT ...

Page 620: ...gy microcomputers with 256 kbyte flash memory as a device type Figure 20 18 shows a memory map in programmer mode A status polling system is adopted for operation in automatic program automatic erase and status read modes In status read mode details of the system s internal signals are output after execution of automatic programming or automatic erasure In programmer mode provide a 12 MHz input cl...

Page 621: ...nquiry selection state 2 Inquiry Selection State In this state the boot program responds to inquiry commands from the host The device name clock mode and bit rate are selected After selection of these settings the program is made to enter the programming erasing state by the command for a transition to the programming erasing state The program transfers the libraries required for erasure to the on...

Page 622: ...ry Response Erasing Programming Reset Bit rate adjustment state Operations for erasing user MATs and user boot MATs Operations for inquiry and selection Operations for programming Operations for checking Operations for erasing Operations for response Inquiry response wait Figure 20 19 Boot Program States ...

Page 623: ...r serial communications between the host and the boot program is as shown below 1 One Byte Commands and One Byte Responses These commands and responses are comprised of a single byte These are consists of the inquiries and the ACK for successful completion 2 n Byte Commands or n Byte Responses These commands and responses are comprised of n bytes of data These are selections and responses to inqui...

Page 624: ...s selection programming erasing and checking Response one byte Response to an inquiry Size one byte The amount of data for transfer excluding the command amount of data and checksum Checksum one byte The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H 00 Error response one byte Error response to a command Error code one byte Type of the error ...

Page 625: ... maximum and minimum values of the main clock and peripheral clocks H 24 User boot MAT information inquiry Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT H 25 User MAT information inquiry Inquiry regarding the number of user MATs and the start and last addresses of each MAT H 26 Erasing block information inquiry Inquiry regarding the number of blocks an...

Page 626: ...orted device inquiry Size one byte Number of bytes to be transferred excluding the command size and checksum that is the amount of data consists of the number of devices characters device codes and product names Number of devices one byte The number of device types supported by the boot program Number of characters one byte The number of characters in the device codes and boot program s name Devic...

Page 627: ...nse H 31 one byte Response to the clock mode inquiry Size one byte Amount of data that represents the number of modes and modes Number of clock modes one byte The number of supported clock modes H 00 indicates no clock mode or the device allows to read the clock mode Mode one byte Values of the supported clock modes i e H 01 means clock mode 1 SUM one byte Checksum d Clock Mode Selection The boot ...

Page 628: ...ze one byte The amount of data that represents the number of clock sources and multiplication ratios and the multiplication ratios Number of types one byte The number of supported multiplied clock types e g when there are two multiplied clock types which are the main and peripheral clocks the number of types will be H 02 Number of multiplication ratios one byte The number of multiplication ratios ...

Page 629: ...d operating clock frequency types e g when there are two operating clock frequency types which are the main and peripheral clocks the number of types will be 2 Minimum value of operating clock frequency two bytes The minimum value of the multiplied or divided clock frequency The minimum and maximum values represent the values in MHz valid to the hundredths place of MHz and multiplied by 100 e g wh...

Page 630: ...here are areas SUM one byte Checksum h User MAT Information Inquiry The boot program will return the number of user MATs and their addresses Command H 25 Command H 25 one byte Inquiry regarding user MAT information Response H 35 Size Number of areas Area start address Area last address SUM Response H 35 one byte Response to the user MAT information inquiry Size one byte The number of bytes that re...

Page 631: ...last Address four bytes Last address of a block There are as many groups of data representing the start and last addresses as there are blocks SUM one byte Checksum j Programming Unit Inquiry The boot program will return the programming unit used to program data Command H 27 Command H 27 one byte Inquiry regarding programming unit Response H 37 Size Programming unit SUM Response H 37 one byte Resp...

Page 632: ...ll be 2 Multiplication ratio 1 one byte The value of multiplication or division ratios for the main operating frequency Multiplication ratio The value of the multiplication ratio e g when the clock frequency is multiplied by four the multiplication ratio will be H 04 Division ratio The inverse of the division ratio as a negative number e g when the clock frequency is divided by two the value of di...

Page 633: ...a multiplication ratio error is generated 3 Operating Frequency Operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio The input frequency is input to the LSI and the LSI is operated at the operating frequency The expression is given below Operating frequency Input frequency Multiplication ratio or Operating frequency Input frequen...

Page 634: ...Bit Rate Selection Sequence 6 Transition of Programming Erasing State The boot program will transfer the erasing program and erase the user MATs and user boot MATs in that order On completion of this erasure ACK will be returned and the programming erasing state will be entered The host should select the device code clock mode and new bit rate with device selection clock mode selection and new bit...

Page 635: ...ion and set with a device selection H 10 command 3 A clock mode inquiry H 21 should be made to inquire about the supported clock modes 4 The clock mode should be selected from among those described by the returned information and set 5 After selection of the device and clock mode inquiries for other required information should be made such as the multiplication ratio inquiry H 22 or operating freq...

Page 636: ...check Checks the blank data of the user boot MAT H 4D User MAT blank check Checks the blank data of the user MAT H 4F Boot program status inquiry Inquires the boot program s status Programming Programming is executed by a programming selection command and a 128 byte programming command Firstly the host should send the programming selection command and select the programming method and programming ...

Page 637: ...amming Selection The boot program will transfer a programming program The data is programmed to the user boot MATs by the transferred programming program Command H 42 Command H 42 one byte User boot MAT programming selection Response H 06 Response H 06 one byte Response to user boot MAT programming selection When the programming program has been transferred ACK will be returned Error Response H C2...

Page 638: ... Command H 50 one byte 128 byte programming Programming address four bytes Start address for programming Multiple of the size specified in response to the programming unit inquiry i e H 00 H 01 H 00 H 00 H 010000 Programming data 128 bytes Data to be programmed The size is specified in the response to the programming unit inquiry SUM one byte Checksum Response H 06 Response H 06 one byte Response ...

Page 639: ...nse H D0 ERROR Error response H D0 one byte Error response for 128 byte programming ERROR one byte Error code H 11 Checksum error H 53 Programming error An error has occurred in programming and programming cannot be continued 10 Erasure Erasure is performed with the erasure selection and block erasure commands Firstly erasure is selected by the erasure selection command and the boot program then e...

Page 640: ...byte Response for erasure selection After the erasure program has been transferred ACK will be returned Error Response H C8 ERROR Error response H C8 one byte Error response to erasure selection ERROR one byte Error code H 54 Selection processing error transfer error occurs and processing is not completed b Block Erasure The boot program will erase the contents of the specified block Command H 58 ...

Page 641: ...sure Size one byte The number of bytes that represents the block number This is fixed to 1 Block number one byte H FF Stop code for erasure SUM one byte Checksum Response H 06 Response H 06 one byte Response to end of erasure ACK When erasure is to be performed after the block number H FF has been specified the procedure should be executed from the erasure selection command 11 Memory Read The boot...

Page 642: ...T H 2B Size error The read size exceeds the MAT 12 User Boot MAT Sum Check The boot program will return the byte by byte total of the contents of the bytes of the user boot MAT as a four byte value Command H 4A Command H 4A one byte Sum check for user boot MAT Response H 5A Size Checksum of MATs SUM Response H 5A one byte Response to the sum check of user boot MAT Size one byte The number of bytes...

Page 643: ...nk check for user boot MAT Response H 06 Response H 06 one byte Response to the blank check of user boot MAT If all user boot MATs are blank H FF ACK will be returned Error Response H CC H 52 Error response H CC one byte Error response to blank check for user boot MAT Error code H 52 one byte Erasure has not been completed 15 User MAT Blank Check The boot program will check whether or not all user...

Page 644: ...number of bytes This is fixed to 2 Status one byte State of the boot program ERROR one byte Error state ERROR 0 indicates normal operation ERROR 1 indicates an error has occurred SUM one byte Checksum Table 20 13 Status Codes Code Description H 11 Device Selection Wait H 12 Clock Mode Selection Wait H 13 Bit Rate Selection Wait H 1F Programming Erasing State Transition Wait Bit rate selection is c...

Page 645: ... Mode Mismatch Error H 24 Bit Rate Selection Error H 25 Input Frequency Error H 26 Multiplication Ratio Error H 27 Operating Frequency Error H 29 Block Number Error H 2A Address Error H 2B Data Length Error H 51 Erasure Error H 52 Erasure Incomplete Error H 53 Programming Error H 54 Selection Processing Error H 80 Command Error H FF Bit Rate Adjustment Confirmation Error ...

Page 646: ... immediately after programming erasing has finished secure the reset period period of RES 0 of more than 100 µs Though a transition to the reset state or hardware standby state during programming erasing is prohibited if reset is executed accidentally reset must be released after the reset input period of 100 µs which is longer than normal 7 At powering on or off the Vcc power supply fix the RES p...

Page 647: ...proximately TBD µs at the maximum 13 A programming erasing program for flash memory used in the conventional H8S F ZTAT microcomputer which does not support download of the on chip program by a SCO transfer request cannot run in this LSI Be sure to download the on chip program to execute programming erasing of flash memory in this LSI 14 Unlike the conventional H8S F ZTAT microcomputer no counterm...

Page 648: ...Rev 1 00 09 03 page 610 of 704 ...

Page 649: ... duty adjustment circuit and divider Figure 21 1 shows a block diagram of the clock pulse generator System clock To pin Internal clock To peripheral modules Oscillator SCKCR System clock control register Legend Duty adjustment circuit Divider SCKCR SCK2 to SCK0 EXTAL XTAL Figure 21 1 Block Diagram of Clock Pulse Generator The internal frequency is changed by software according to the settings of t...

Page 650: ...he division ratio for the divider Bit Bit Name Initial Value R W Description 7 PSTOP 0 R W φ Output Disabled Controls φ output In normal operation 0 φ output 1 Fixed to high In sleep mode 0 φ output 1 Fixed to high In software standby mode 0 Fixed to high 1 Fixed to high In hardware standby mode 0 High impedance 1 High impedance 6 to 3 All 0 R W Reserved Although these bits are readable writable o...

Page 651: ...l Value R W Description 2 1 0 SCK2 SCK1 SCK0 0 0 0 R W R W R W System Clock Select 2 to 0 Select the division ratio 000 1 1 001 1 2 010 1 4 011 Setting prohibited 100 Setting prohibited 101 Setting prohibited 11x Setting prohibited Legend x Don t care ...

Page 652: ...tal resonator should be used Figure 21 3 shows the equivalent circuit of a crystal resonator A crystal resonator having the characteristics given in table 21 2 should be used EXTAL XTAL Rd CL2 CL1 CL1 CL2 10 to 22 pF Figure 21 2 Typical Connection to Crystal Resonator Table 21 1 Damping Resistor Values Frequency MHz 10 12 16 20 Rd Ω 0 0 0 0 XTAL CL AT cut parallel resonance crystal resonator EXTAL...

Page 653: ...Example of external clock input when XTAL pin left open EXTAL XTAL External clock input b Example of external clock input when an inverted clock is input to XTAL pin Figure 21 4 Example of External Clock Input Table 21 3 External Clock Input Conditions VCC 3 0 to 3 6 V Item Symbol Min Max Unit Test Conditions External clock input pulse width low level tEXL 15 ns External clock input pulse width hi...

Page 654: ...ate Table 21 4 shows the output stabilization delay time for the external clock Figure 21 6 shows the timing of the output stabilization delay time for the external clock Table 21 4 Output Stabilization Delay Time for External Clock Condition VCC 2 7 V to 3 6 V AVCC 2 7 V to 3 6 V VSS AVSS 0 V Item Symbol Min Max Unit Remarks Output stabilization delay time for external clock tDEXT 500 µs Figure 2...

Page 655: ...y reference be sure to use an resonator that has been sufficiently evaluated by the user Consult with the resonator manufacturer about the resonator circuit ratings which vary depending on the stray capacitances of the resonator and installation circuit Make sure the voltage applied to the oscillation pins do not exceed the maximum rating 21 5 2 Notes on Board Design When using a crystal resonator...

Page 656: ...eration Confirmation Even if a crystal resonator is not connected to the EXTAL and XTAL pins or an external clock is not input self oscillation may occur at the several kHz frequency Therefore make sure that this LSI operates at the correct frequency ...

Page 657: ...pheral modules and so on This LSI s operating modes are high speed mode and five power down modes Clock division mode Sleep mode Module stop mode Software standby mode Hardware standby mode Sleep mode is a CPU state clock division mode is CPU and on chip peripheral function states and module stop mode is an on chip peripheral function state A combination of these modes can be set After a reset thi...

Page 658: ...ted Retained Halted Retained Halted Reset FRT Functions Functions Functions Halted Retained Halted Retained Halted Reset Timer connection Functions Functions Functions Halted Retained Halted Retained Halted Reset Duty measurement circuit Functions Functions Functions Halted Retained Halted Retained Halted Reset TPU Functions Functions Functions Halted Retained Halted Retained Halted Reset A D Func...

Page 659: ...rnal clock is duty adjustment circuit output clock Reset state pin low pin high pin low SSBY 0 MSTPCR H FFFF H FFFE EXMSTPCR H FFFF SSBY 0 SSBY 1 SCK2 to SCK0 0 pin high SCK2 to SCK0 0 SLEEP instruction Transition after exception handling Power down mode SLEEP instruction Any interrupt SLEEP instruction Interrupt Hardware standby mode Sleep mode main clock Software standby mode Clock division mode...

Page 660: ... R W Software Standby Specifies the transition mode after executing the SLEEP instruction 0 Shifts to sleep mode after the SLEEP instruction is executed 1 Shifts to software standby mode after the SLEEP instruction is executed This bit does not change when clearing software standby mode by using external interrupts and shifting to normal operation Write 0 to this bit when clearing 6 OPE 1 R W Outp...

Page 661: ...the MCU waits for the clock to stabilize when software standby mode is cleared Make a selection according to the operating frequency so that the standby time is at least 8 ms oscillation stabilization time With an external clock make a selection according to the operating frequency so that the standby time is at least 500 µs output stabilization delay time for external clock For relationship betwe...

Page 662: ... not be changed 11 MSTP11 1 R W Duty measurement circuit TWM 10 MSTP10 1 R W 16 bit timer pulse unit TPU 9 MSTP9 1 R W A D converter 8 MSTP8 1 R W 8 bit PWM timer PWM 14 bit PWM timer PWMX MSTPCRL Bit Bit Name Initial Value R W Module 7 MSTP7 1 R W 6 MSTP6 1 R W Reserved The initial value should not be changed 5 MSTP5 1 R W 16 bit free running timer FRT_1 4 MSTP4 1 R W 16 bit free running timer FR...

Page 663: ...TP27 1 R W 10 MSTP26 1 R W 9 MSTP25 1 R W Reserved The initial value should not be changed 8 MSTP24 1 R W Serial communication interface 4 SCI_4 EXMSTPCRL Bit Bit Name Initial Value R W Module 7 MSTP23 1 R W Serial communication interface 3 SCI_3 6 MSTP22 1 R W Serial communication interface 2 SCI_2 5 MSTP21 1 R W Serial communication interface 1 SCI_1 4 MSTP20 1 R W Serial communication interface...

Page 664: ...rupt clock division mode is restored When the RES pin is driven low the reset state is entered and clock division mode is cleared The same applies to a reset caused by a watchdog timer overflow When the STBY pin is driven low a transition is made to hardware standby mode 22 2 2 Sleep Mode Transition to Sleep Mode When the SLEEP instruction is executed when the SSBY bit is 0 in SBYCR the CPU enters...

Page 665: ... IRQ7 or by means of the RES pin or STBY pin Setting the SSI bit in SSIER to 1 enables IRQ0 to IRQ7 to be used as software standby mode clearing sources Clearing with Interrupt When an NMI or IRQ0 to IRQ7 interrupt request signal is input clock oscillation starts and after the elapse of the time set in bits STS2 to STS0 in SBYCR stable clocks are supplied to the entire LSI software standby mode is...

Page 666: ... for operating frequencies and settings of bits STS2 to STS0 Using External Clock The desired value can be set Table 22 2 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 20 MHz 10 MHz 8 MHz 6 MHz Unit 0 0 0 8192 states 0 4 0 8 1 0 1 3 ms 1 16384 states 0 6 1 6 2 0 2 7 1 0 32768 states 1 6 3 3 4 1 5 5 1 65536 states 3 3 6 6 8 2 10 9 1 0 0 131072 states 6 6 13 1 16 4 21 8 1 26214...

Page 667: ...bit in INTCR cleared to 0 falling edge specification then the NMIEG bit is set to 1 rising edge specification the SSBY bit is set to 1 and a SLEEP instruction is executed causing a transition to software standby mode Software standby mode is then cleared at the rising edge on the NMI pin Oscillator NMI φ NMIEG SSBY NMI exception handling NMIEG 1 SSBY 1 SLEEP instruction Software standby mode power...

Page 668: ... mode during a reset at power on Clearing Hardware Standby Mode Hardware standby mode is cleared by means of the STBY pin and the RES pin When the STBY pin is driven high while the RES pin is low the reset state is set and clock oscillation is started Ensure that the RES pin is held low until the clock oscillator stabilizes for details on the oscillation stabilization time refer to table 22 2 When...

Page 669: ...at the end of the bus cycle In module stop mode the internal states of modules other than the PWM PWMX SCI and IIC3 are retained After reset clearance all modules are in module stop mode The module registers which are set in module stop mode cannot be read or written to 22 3 φ φ φ φ Clock Output Control Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR and DDR for the corr...

Page 670: ...ng State Register Setting DDR PSTOP Normal Operating State Sleep Mode Software Standby Mode Hardware Standby Mode 0 X High impedance High impedance High impedance High impedance 1 0 φ output φ output Fixed high High impedance 1 1 Fixed high Fixed high Fixed high High impedance ...

Page 671: ...ntering module stop mode 22 4 4 Writing to MSTPCR EXMSTPCR MSTPCR and EXMSTPCR should only be written to by the CPU 22 4 5 Notes on Clock Division Mode The following points should be noted in clock division mode Select the clock division ratio specified by the SCK2 to SCK0 bits so that the frequency of φ is within the operation guaranteed range of clock cycle time tcyc shown in the Electrical Char...

Page 672: ...Rev 1 00 09 03 page 634 of 704 ...

Page 673: ...gister Bits Bit configurations of the registers are described in the same order as the Register Addresses Address Order above Reserved bits are indicated by in the bit name column The bit number in the bit name column indicates that the whole register is allocated as a counter or for holding data Each line covers eight bits so 16 bit registers are shown as 2 lines 3 Register States in Each Operati...

Page 674: ... H IPRH 16 H FD8E Interrupts 16 2 Interrupt priority register I IPRI 16 H FD90 Interrupts 16 2 Interrupt priority register J IPRJ 16 H FD92 Interrupts 16 2 Interrupt priority register K IPRK 16 H FD94 Interrupts 16 2 IRQ sense control register ISCR 16 H FD96 Interrupts 16 2 Software standby release IRQ enable register SSIER 8 H FD98 Interrupts 16 2 Interrupt control register INTCR 8 H FD99 Interru...

Page 675: ..._3 SMR_3 8 H FDC8 SCI_3 8 2 Bit rate register_3 BRR_3 8 H FDC9 SCI_3 8 2 Serial control register_3 SCR_3 8 H FDCA SCI_3 8 2 Transmit data register_3 TDR_3 8 H FDCB SCI_3 8 2 Serial status register_3 SSR_3 8 H FDCC SCI_3 8 2 Receive data register_3 RDR_3 8 H FDCD SCI_3 8 2 Serial interface mode register_3 SCMR_3 8 H FDCE SCI_3 8 2 Serial mode register_4 SMR_4 8 H FDD0 SCI_4 8 2 Bit rate register_4 ...

Page 676: ...FRT_0 16 2 Timer control status register_0 TCSR_0 8 H FE01 FRT_0 16 2 Free running counter_0 FRC_0 16 H FE02 FRT_0 16 2 Output compare register A_0 OCRA_0 16 H FE04 FRT_0 16 2 Output compare register B_0 OCRB_0 16 H FE04 FRT_0 16 2 Timer control register_0 FR_TCR_0 8 H FE06 FRT_0 16 2 Timer output compare control register_0 TOCR_0 8 H FE07 FRT_0 16 2 Input capture register A_0 ICRA_0 16 H FE08 FRT...

Page 677: ...egister B1_0 TCORB1_0 8 H FE1F TMR01_0 16 2 Timer counter 0_0 TCNT0_0 8 H FE20 TMR01_0 16 2 Timer counter 1_0 TCNT1_0 8 H FE21 TMR01_0 16 2 Timer connection register I_0 TCONRI_0 8 H FE24 Timer connection_0 8 2 Timer connection register O_0 TCONRO_0 8 H FE25 Timer connection_0 8 2 Timer connection register S_0 TCONRS_0 8 H FE26 Timer connection_0 8 2 Edge sense register_0 SEDGR_0 8 H FE27 Timer co...

Page 678: ...er F_1 TICRF_1 8 H FE43 TMRX_1 8 2 Timer counter X_1 TCNTX_1 8 H FE44 TMRX_1 8 2 Time constant register C_1 TCORC_1 8 H FE45 TMRX_1 8 2 Time constant register AX_1 TCORAX_1 8 H FE46 TMRX_1 8 2 Time constant register BX_1 TCORBX_1 8 H FE47 TMRX_1 8 2 Timer control register 0_1 TCR0_1 8 H FE48 TMR01_1 16 2 Timer control register 1_1 TCR1_1 8 H FE49 TMR01_1 16 4 Timer control status register 0_1 TCSR...

Page 679: ... H FE92 Flash memory 8 2 Flash key code register FKEY 8 H FE94 Flash memory 8 2 Flash MAT select register FMATS 8 H FE95 Flash memory 8 2 Flash transfer destination address register FTDAR 8 H FE96 Flash memory 8 2 Mode control register MDCR 8 H FEB0 SYSTEM 8 2 System control register SYSCR 8 H FEB1 SYSTEM 8 2 Standby control register SBYCR 8 H FEB2 SYSTEM 8 2 System clock control register SCKCR 8 ...

Page 680: ...8 2 Port 8 data register P8DR 8 H FED8 PORT 8 2 Port 9 data register P9DR 8 H FED9 PORT 8 2 Port A data register PADR 8 H FEDA PORT 8 2 Port B data register PBDR 8 H FEDB PORT 8 2 Port C data register PCDR 8 H FEDC PORT 8 2 Port 1 data direction register P1DDR 8 H FEE1 PORT 8 2 Port 2 data direction register P2DDR 8 H FEE2 PORT 8 2 Port 3 data direction register P3DDR 8 H FEE3 PORT 8 2 Port 4 data...

Page 681: ...ansmit data register_0 ICDRT_0 8 H FF86 IIC3_0 8 2 I2 C receive data register_0 ICDRR_0 8 H FF87 IIC3_0 8 2 I2 C bus control register A_1 ICCRA_1 8 H FF88 IIC3_1 8 2 I2 C bus control register B_1 ICCRB_1 8 H FF89 IIC3_1 8 2 I2 C bus mode register_1 ICMR_1 8 H FF8A IIC3_1 8 2 I2 C bus interrupt enable register_1 ICIER_1 8 H FF8B IIC3_1 8 2 I2 C bus status register_1 ICSR_1 8 H FF8C IIC3_1 8 2 Slave...

Page 682: ... register_3 ICSR_3 8 H FFA4 IIC3_3 8 2 Slave address register_3 SAR_3 8 H FFA5 IIC3_3 8 2 I2 C transmit data register_3 ICDRT_3 8 H FFA6 IIC3_3 8 2 I2 C receive data register_3 ICDRR_3 8 H FFA7 IIC3_3 8 2 I2 C status register A_2 ICSRA_2 8 H FFA8 IIC3_2 8 2 Slave address register A_2 SARA_2 8 H FFA9 IIC3_2 8 2 Slave address register B_2 SARB_2 8 H FFAA IIC3_2 8 2 Slave address mask register_2 SAMR...

Page 683: ...mon 16 2 Timer synchro register TSYR 8 H FFCD TPU common 16 2 Timer control register_0 TCR_0 8 H FFD0 TPU_0 16 2 Timer mode register_0 TMDR_0 8 H FFD1 TPU_0 16 2 Timer I O control register H_0 TIORH_0 8 H FFD2 TPU_0 16 2 Timer I O control register L_0 TIORL_0 8 H FFD3 TPU_0 16 2 Timer interrupt enable register_0 TIER_0 8 H FFD4 TPU_0 16 2 Timer status register_0 TSR_0 8 H FFD5 TPU_0 16 2 Timer cou...

Page 684: ...gister_2 TCR_2 8 H FFF0 TPU_2 16 2 Timer mode register_2 TMDR_2 8 H FFF1 TPU_2 16 2 Timer I O control register_2 TIOR_2 8 H FFF2 TPU_2 16 2 Timer interrupt enable register_2 TIER_2 8 H FFF4 TPU_2 16 2 Timer status register_2 TSR_2 8 H FFF5 TPU_2 16 2 Timer counter_2 TCNT_2 16 H FFF6 TPU_2 16 2 Timer general register A_2 TGRA_2 16 H FFF8 TPU_2 16 2 Timer general register B_2 TGRB_2 16 H FFFA TPU_2 ...

Page 685: ...PRE10 IPRE9 IPRE8 IPRE6 IPRE5 IPRE4 IPRE2 IPRE1 IPRE0 IPRF IPRF14 IPRF13 IPRF12 IPRF10 IPRF9 IPRF8 IPRF6 IPRF5 IPRF4 IPRF2 IPRF1 IPRF0 IPRG IPRG14 IPRG13 IPRG12 IPRG10 IPRG9 IPRG8 IPRG6 IPRG5 IPRG4 IPRG2 IPRG1 IPRG0 IPRH IPRH14 IPRH13 IPRH12 IPRH10 IPRH9 IPRH8 IPRH6 IPRH5 IPRH4 IPRH2 IPRH1 IPRH0 IPRI IPRI14 IPRI13 IPRI12 IPRI10 IPRI9 IPRI8 IPRI6 IPRI5 IPRI4 IPRI2 IPRI1 IPRI0 IPRJ IPRJ14 IPRJ13 IPR...

Page 686: ...t5 bit4 bit3 bit2 bit1 bit0 SCMR_1 SDIR SINV SMR_2 C A CHR PE O E STOP MP CKS1 CKS0 SCI_2 BRR_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCR_2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SSR_2 TDRE RDRF ORER FER PER TEND MPB MPBT RDR_2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SCMR_2 SDIR SINV SMR_3 C A CHR PE O E STOP MP CKS1 CKS0 SCI_3 BRR_3 bit7 bit6 bit5 bit4 b...

Page 687: ... AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADDRG AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADDRH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADCSR ADF ADIE ADST CH3 CH2 CH1 CH0 ADCR TRGS1 TRGS0 SCANE SCANS CKS1 CKS0 TWICR bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TWCNT bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TWCR1 FRC CKS2 CKS1 CKS0 IS2 IS1 IS0 Duty measurement circuit TWCR2 ENDIE OVIE ENDF OVF START FR_TIER_0 ...

Page 688: ...it6 bit5 bit4 bit3 bit2 bit1 bit0 OCRDM_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ICRD_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCRX_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMRX_0 TCSRX_0 CMFB CMFA OVF ICF OS3 OS2 OS1 OS0 TICRR_0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TICRF_0 bit7 bit6 bit5 bit4 bit...

Page 689: ... FR_TIER_1 ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE FRT_1 TCSR_1 ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA FRC_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OCRA_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 OCRB_1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 FR_TCR_1 IEDGA IE...

Page 690: ...IE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR01_1 TCR1_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCSR0_1 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 TCSR1_1 CMFB CMFA OVF OS3 OS2 OS1 OS0 TCORA0_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCORA1_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TMR01_1 TCORB0_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCORB1_1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCNT0_1 bit7 bit6 bit5 bit...

Page 691: ...TP2 MSTP1 MSTP0 EXMSTPCRH MSTP31 MSTP30 MSTP29 MSTP28 MSTP27 MSTP26 MSTP25 MSTP24 EXMSTPCRL MSTP23 MSTP22 MSTP21 MSTP20 MSTP19 MSTP18 MSTP17 MSTP16 TECR VS0 HS2 HS1 HS0 ICKS1_1 ICKS0_1 ICKS1_0 ICKS0_0 PORT0 P07 P06 P05 P04 P03 P02 P01 P00 Port PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT2 P27 P26 P25 P24 P23 P22 P21 P20 PORT3 P37 P36 P35 P34 P33 P32 P31 P30 PORT4 P47 P46 P45 P44 P43 P42 P41 P40 PORT...

Page 692: ...33DDR P32DDR P31DDR P30DDR P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR P5DDR P57DDR P56DDR P55DDR P54DDR P53DDR P52DDR P51DDR P50DDR P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR P8DDR P87DDR P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR P9DDR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR P...

Page 693: ... AAS ADZ SAR_1 SVA6 SVA5 SVA4 SVA3 SVA2 SVA2 SVA1 ICDRT_1 ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0 ICDRR_1 ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0 ICSRA_0 AASA AASB IIC3_0 SARA_0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 SARE SARB_0 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 SARE SAMR_0 MSA6 MSA5 MSA4 MSA3 MSA2 MSA1 MSA0 MTRS ICSRA_1 AASA AASB IIC3_1 SARA_1 SVA6 SVA5 SVA4 SVA3 SVA2...

Page 694: ...A3 MSA2 MSA1 MSA0 MTRS ICSRA_3 AASA AASB IIC3_3 SARA_3 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 SARE SARB_3 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 SARE SAMR_3 MSA6 MSA5 MSA4 MSA3 MSA2 MSA1 MSA0 MTRS BCR ICIS PNCASH ADMXE BSC BCRA1 ABW1 AST1 PNCCS1 AW1 WMS11 WMS10 WC11 WC10 BCRA2 ABW2 AST2 PNCCS2 AW2 WMS21 WMS20 WC21 WC20 BCRA3 ABW3 AST3 PNCCS3 AW3 WMS31 WMS30 WC31 WC30 TCNT bit7 bit6 bit5 bit4 bit3 bit2 bit...

Page 695: ...it13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TGRB_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TGRC_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TGRD_0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 ...

Page 696: ...R_2 TTGE TCIEU TCIEV TGIEB TGIEA TSR_2 TCFD TCFU TCFV TGFB TGFA TCNT_2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TGRA_2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 TGRB_2 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Note To classify the same name registers of the other tim...

Page 697: ...ialized Initialized SSIER Initialized Initialized INTCR Initialized Initialized IER Initialized Initialized ISR Initialized Initialized SMR_0 Initialized Initialized SCI_0 BRR_0 Initialized Initialized SCR_0 Initialized Initialized TDR_0 Initialized Initialized Initialized Initialized SSR_0 Initialized Initialized Initialized Initialized RDR_0 Initialized Initialized Initialized Initialized SCMR_0...

Page 698: ...ed Initialized SSR_3 Initialized Initialized Initialized Initialized RDR_3 Initialized Initialized Initialized Initialized SCMR_3 Initialized Initialized SMR_4 Initialized Initialized SCI_4 BRR_4 Initialized Initialized SCR_4 Initialized Initialized TDR_4 Initialized Initialized Initialized Initialized SSR_4 Initialized Initialized Initialized Initialized RDR_4 Initialized Initialized Initialized ...

Page 699: ... Initialized Initialized OCRAR_0 Initialized Initialized ICRB_0 Initialized Initialized OCRAF_0 Initialized Initialized ICRC_0 Initialized Initialized OCRDM_0 Initialized Initialized ICRD_0 Initialized Initialized TCRX_0 Initialized Initialized TMRX_0 TCSRX_0 Initialized Initialized TICRR_0 Initialized Initialized TICRF_0 Initialized Initialized TCNTX_0 Initialized Initialized TCORC_0 Initialized ...

Page 700: ...lized TCORBY_0 Initialized Initialized TCNTY_0 Initialized Initialized FR_TIER_1 Initialized Initialized FRT_1 TCSR_1 Initialized Initialized FRC_1 Initialized Initialized OCRA_1 Initialized Initialized OCRB_1 Initialized Initialized FR_TCR_1 Initialized Initialized TOCR_1 Initialized Initialized ICRA_1 Initialized Initialized OCRAR_1 Initialized Initialized ICRB_1 Initialized Initialized OCRAF_1 ...

Page 701: ...ed TCNT1_1 Initialized Initialized TCONRI_1 Initialized Initialized TCONRO_1 Initialized Initialized TCONRS_1 Initialized Initialized SEDGR_1 Initialized Initialized Timer connection_1 TCRY_1 Initialized Initialized TMRY_1 TCSRY_1 Initialized Initialized TCORAY_1 Initialized Initialized TCORBY_1 Initialized Initialized TCNTY_1 Initialized Initialized TISR_1 Initialized Initialized FCCS Initialized...

Page 702: ...PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 PORT8 PORT9 PORTA PORTB PORTC P1DR Initialized Initialized P2DR Initialized Initialized P3DR Initialized Initialized P4DR Initialized Initialized P5DR Initialized Initialized P6DR Initialized Initialized P8DR Initialized Initialized P9DR Initialized Initialized PADR Initialized Initialized PBDR Initialized Initialized PCDR Initialized Initialized P1DDR Ini...

Page 703: ...ODR Initialized Initialized PFCR Initialized Initialized PTCNT0 Initialized Initialized PTCNT1 Initialized Initialized PTCNT2 Initialized Initialized ICCRA_0 Initialized Initialized IIC3_0 ICCRB_0 Initialized Initialized ICMR_0 Initialized Initialized ICIER_0 Initialized Initialized ICSR_0 Initialized Initialized SAR_0 Initialized Initialized ICDRT_0 Initialized Initialized ICDRR_0 Initialized Ini...

Page 704: ...tialized ICIER_2 Initialized Initialized ICSR_2 Initialized Initialized SAR_2 Initialized Initialized ICDRT_2 Initialized Initialized ICDRR_2 Initialized Initialized ICCRA_3 Initialized Initialized IIC3_3 ICCRB_3 Initialized Initialized ICMR_3 Initialized Initialized ICIER_3 Initialized Initialized ICSR_3 Initialized Initialized SAR_3 Initialized Initialized ICDRT_3 Initialized Initialized ICDRR_3...

Page 705: ...zed Initialized DADRA Initialized Initialized Initialized Initialized PWMX DACR Initialized Initialized Initialized Initialized DADRB Initialized Initialized Initialized Initialized DACNTH Initialized Initialized Initialized Initialized DACNTL Initialized Initialized Initialized Initialized TSTR Initialized Initialized TPU common TSYR Initialized Initialized TCR_0 Initialized Initialized TPU_0 TMD...

Page 706: ... Initialized Initialized TCNT_1 Initialized Initialized TGRA_1 Initialized Initialized TGRB_1 Initialized Initialized TCR_2 Initialized Initialized TPU_2 TMDR_2 Initialized Initialized TIOR_2 Initialized Initialized TIER_2 Initialized Initialized TSR_2 Initialized Initialized TCNT_2 Initialized Initialized TGRA_2 Initialized Initialized TGRB_2 Initialized Initialized Note To classify the same name...

Page 707: ... 3 to VCC 0 3 Input voltage ports 0 and 7 Vin 0 3 to AVCC 0 3 Reference power supply voltage AVref 0 3 to AVCC 0 3 Analog power supply voltage AVCC 0 3 to 4 3 Analog input voltage VAN 0 3 to AVCC 0 3 Operating temperature Topr 20 to 75 C Operating temperature when flash memory is programmed or erased Topr 0 to 75 Storage temperature Tstg 55 to 125 Caution Permanent damage to this LSI may result if...

Page 708: ... 05 V RES STBY NMI FWE MD0 to MD2 SCK0 to SCK4 RxD0 to RxD4 TMI0_0 TMI1_0 TMIX_0 TMIY_0 TMI0_1 TMI1_1 TMIX_1 TMIY_1 FTCI_0 FTIA_0 FTIB_0 FTIC_0 FTID_0 FTCI_1 FTIA_1 FTIB_1 FTIC_1 FTID_1 TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 ExTCLKA ExTCLKB ExTCLKC ExTCLKD ExTIOCA0 ExTIOCB0 ExTIOCC0 ExTIOCD0 ExTIOCA1 ExTIOCB1 ExTIOCA2 ExTIOCB2 VCC 0 9 VCC 0 3 SCL3 SCL2 SCL1...

Page 709: ...ree state leakage current off state Ports 80 to 83 ports C0 to C3 1 0 Vin 0 5 to 5 5 V Input pull up MOS current Ports 1 to 3 6 IP 5 150 Vin 0 V All input pins except for P80 toP83 PC0 to PC3 Cin 10 pF Input capacitance P80 to P83 PC0 to PC3 10 Vin 0 V f 1 MHz Ta 25 C Normal operation 5 23 35 VCC 3 0 V to 3 6 V f 20 MHz when all module stop cleared high speed mode Sleep mode 15 25 mA VCC 3 0 V to ...

Page 710: ...lues are for VIH min VCC 0 2 V and VIL max 0 2 V with all output pins unloaded and the on chip pull up MOSs in the off state 4 The values are for VRAM VCC 3 0 V VIH min VCC 0 2 V and VIL max 0 2 V 5 Except for flash memory programming erasing Table 24 3 Permissible Output Currents Conditions VCC 3 0 V to 3 6 V VSS 0 V Item Symbol Min Typ Max Unit Permissible output low current per pin SCL0 to SCL3...

Page 711: ...ludes capacitance of measuring jigs I O reference level 1 5 V Figure 24 2 Output Load Circuit 24 3 1 Clock Timing Table 24 4 shows the clock timing The clock timing specified here covers oscillation stabilization times for clock output φ clock pulse generator crystal and external clock input EXTAL pin For details on external clock input EXTAL pin and EXCL pin timing see section 21 Clock Pulse Gene...

Page 712: ...ulse width tCL 10 Clock rise time tCr 8 Clock fall time tCf 8 Figure 24 3 Reset oscillation stabilization crystal tOSC1 10 ms Figure 24 4 Software standby oscillation stabilization time crystal tOSC2 8 Figure 24 5 External clock output stabilization delay time tDEXT 500 µs Figure 24 4 tCr tCL tCf tCH tcyc Figure 24 3 System Clock Timing tOSC1 tOSC1 EXTAL VCC φ tDEXT tDEXT Figure 24 4 Oscillation S...

Page 713: ... 3 6 V VSS 0 V φ 5 MHz to 20 MHz Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 ns RES pulse width tRESW 20 tcyc Figure 24 6 NMI setup time tNMIS 150 ns NMI hold time tNMIH 10 NMI pulse width exiting software standby mode tNMIW 200 IRQ setup time IRQ0 to IRQ7 ExIRQ0 to ExIRQ7 tIRQS 150 IRQ hold time IRQ0 to IRQ7 ExIRQ0 to ExIRQ7 tIRQH 10 IRQ pulse width IRQ0 to IRQ7 ExIRQ0 to Ex...

Page 714: ...f 704 tRESW tRESS tRESS Figure 24 6 Reset Input Timing φ edge input level input NMI i 0 to 7 tIRQS tIRQH tNMIS tNMIH tIRQS tNMIW tIRQW Note To cancel software standby mode SSIER should be set Figure 24 7 Interrupt Input Timing ...

Page 715: ... AS delay time tASD 20 RD delay time 1 tRSD1 20 RD delay time 2 tRSD2 20 Read data setup time tRDS 15 Read data hold time tRDH 0 Read data access time 2 tACC2 1 5 x tcyc 25 Read data access time 3 tACC3 2 0 x tcyc 30 Read data access time 4 tACC4 2 5 x tcyc 25 Read data access time 5 tACC5 3 0 x tcyc 30 WR delay time 1 tWRD1 20 WR delay time 2 tWRD2 20 WR pulse width 1 tWSW1 1 0 x tcyc 20 WR pulse...

Page 716: ...e 678 of 704 φ A15 to A0 to Read D15 to D0 Read Write D15 to D0 Write tRSD2 tAS tAH tACC2 tRSD1 tASD tASD tAD tACC3 tWRD2 tWRD2 tWSW1 tWDD tWDH tAH T1 T2 tRDS tAS tAS tCSD tRDH Figure 24 8 Basic Bus Timing 2 State Access ...

Page 717: ...679 of 704 φ Read D15 to D0 Read Write D15 to D0 Write A15 to A0 to tRSD2 tAS tACC4 tRSD1 tASD tASD tAD tACC5 tRDH tWRD2 tWRD1 tWSW2 tWDD tWDH T1 T3 tWDS T2 tRDS tAH tAS tCSD tAH Figure 24 9 Basic Bus Timing 3 State Access ...

Page 718: ...Rev 1 00 09 03 page 680 of 704 φ Read D15 to D0 Read Write D15 to D0 Write A15 to A0 tWTH T1 T2 Tw T3 tWTS tWTH tWTS Figure 24 10 Basic Bus Timing 3 State Access with One Wait State ...

Page 719: ...SD1 20 RD delay time 2 tRSD2 20 Read data setup time tRDS 15 Read data hold time tRDH 0 Read data access time 2 tACC2 1 5 x tcyc 25 Read data access time 4 tACC4 2 5 x tcyc 30 Read data access time 6 tACC6 3 5 x tcyc 25 Read data access time 7 tACC7 4 5 x tcyc 30 WR delay time 1 tWRD1 20 WR delay time 2 tWRD2 20 WR pulse width 1 tWSW1 1 0 x tcyc 20 WR pulse width 2 tWSW2 1 5 x tcyc 20 Write data d...

Page 720: ...82 of 704 T1 T2 AD15 to AD0 AD15 to AD0 T3 T4 tAH2 tAS2 tCSD tAHD tAD tRSD2 tACC2 tWSW1 tRSD1 tWRD2 tWDD tAD tWRD2 tRDH tRDS tWDH tACC6 D15 to D0 A15 to A0 D15 to D0 A15 to A0 Figure 24 11 Muliplex Bus Timing 2 State Access ...

Page 721: ... 704 T1 T2 AD15 to AD0 AD15 to AD0 T3 T4 T5 tAH2 tAS2 tCSD tAHD tAD tRSD2 tACC4 tWSW2 tRSD1 tWRD1 tWDD tWDS tAD tWRD2 tRDH tRDS tWDH tACC6 D15 to D0 A15 to A0 D15 to D0 A15 to A0 Figure 24 12 Multiplex Bus Timing 3 State Access ...

Page 722: ...Rev 1 00 09 03 page 684 of 704 tWTH T1 T2 Read AD15 to AD0 Read Write AD15 to AD0 Write T3 T4 TDOW T5 tWTS tWTH tWTS Figure 24 13 Multiplex Bus Timing 3 State Access with One Wait State ...

Page 723: ...ure 24 17 Timer input setup time tTICS 25 Timer clock input setup time tTCKS 25 Figure 24 18 Single edge tTCKWH 1 5 tcyc Timer clock pulse width Both edges tTCKWL 2 5 TMR Timer output delay time tTMOD 40 ns Figure 24 19 Timer reset input setup time tTMRS 25 Figure 24 21 Timer clock input setup time tTMCS 25 Single edge tTMCWH 1 5 tcyc Timer clock pulse width Both edges tTMCWL 2 5 Figure 24 20 PWM ...

Page 724: ... A to C write tPRS T1 T2 tPWD tPRH Figure 24 14 I O Port Input Output Timing φ FTOA_0 FTOB_0 FTOA_1 FTOB_1 FTIA_0 FTIB_0 FTIC_0 FTID_0 FTIA_1 FTIB_1 FTIC_1 FTID_1 tFTIS tFTOD Figure 24 15 FRT Input Output Timing φ FTCI_0 FTCI_1 tFTCS tFTCWH tFTCWL Figure 24 16 FRT Clock Input Timing ...

Page 725: ...ExTIOCC0 ExTIOCD0 Figure 24 17 TPU Input Output Timing TCLKA to TCLKD ExTCLKA to ExTCLKD tTCKWL tTCKWH tTCKS tTCKS Figure 24 18 TPU Clock Input Timing φ TMO0_0 TMO1_0 TMOX_0 TMOY_0 TMO0_1 TMO1_1 TMOX_1 TMOY_1 tTMOD Figure 24 19 8 Bit Timer Output Timing φ TMI0_0 TMI1_0 TMIX_0 TMIY_0 TMI0_1 TMI1_1 TMIX_1 TMIY_1 tTMCS tTMCS tTMCWH tTMCWL Figure 24 20 8 Bit Timer Clock Input Timing ...

Page 726: ...imer Reset Input Timing φ PW7 to PW0 EXPW7 to EXPW0 PWX1 PWX0 tPWOD Figure 24 22 PWM PWMX Output Timing tScyc tSCKr tSCKW SCK0 to SCK4 tSCKf Figure 24 23 SCK Clock Input Timing SCK0 to SCK4 TxD0 to TxD4 transmit data RxD0 to RxD4 receive data tTXD tRXH tRXS Figure 24 24 SCI Input Output Timing Clock Synchronous Mode ...

Page 727: ...L input high width tSCLH 3tcyc 300 ns SCL input low width tSCLL 5tcyc 300 ns SCL and SDA input fall time tSf 300 ns SCL and SDA input spike pulse removal time tSP 1tcyc ns SDA input bus free time tBUF 5tcyc ns Start condition input hold time tSTAH 3tcyc ns Retransmission start condition input setup time tSTAS 3tcyc ns Setup time for stop condition input tSTOS 3tcyc ns Data input setup time tSDAS 1...

Page 728: ...S tSCLH tSCLL tSf tSr tSCL tSDAH tSDAS P S Sr P VIH VIL SDA0 to SDA5 SCL0 to SCL5 Note S P and Sr indicate the following conditions S Start condition P Stop condition Sr Retransmission start condition Figure 24 26 Input Output Timing of I 2 C Bus Interface 3 ...

Page 729: ...0 V to 3 6 V AVCC 3 0 V to 3 6 V AVref 3 0 V to AVCC VSS AVSS 0 V φ 5 MHz to 20 MHz Condition Item Min Typ Max Unit Resolution 10 Bits Conversion time 6 7 µs Analog input capacitance 20 pF Permissible signal source impedance 5 0 kΩ Nonlinearity error 5 5 LSB Offset error 5 5 Full scale error 5 5 Quantization error 0 5 Absolute accuracy 6 0 Note Value when using the maximum operating frequency in s...

Page 730: ...mming time total 1 2 4 Σ tP 5 15 s 256 kbytes Ta 25 C Erase time total 1 2 4 Σ tE 5 15 s 256 kbytes Ta 25 C Programming and erase time total 1 2 4 Σ tPE 10 30 s 256 kbytes Ta 25 C Reprogramming count NWEC 100 3 Times Data retention time 4 tDRP 10 Years Notes 1 Programming and erase time depends on the data 2 Programming and erase time does not include data transfer time 3 This value indicates the ...

Page 731: ...ltage An example of connection is shown in figure 24 27 VCL VSS External capacitor for power stabilization 0 1 µF or 0 47 µF Do not connect Vcc power supply to the VCL pin Always connect a capacitor for power stabilization Use a ceramic multilayer capacitor 0 1 µF or 0 47 µF and place it near the pin Figure 24 27 Connection of VCL Capacitor ...

Page 732: ...Rev 1 00 09 03 page 694 of 704 ...

Page 733: ...ort Port 2 EXPE 1 T T Kept Kept Address output I O port A15 to A8 EXPE 0 I O port Port 3 EXPE 1 T T T T D15 to D8 D15 to D8 EXPE 0 Kept Kept I O port Port 4 EXPE 1 T T Kept Kept I O port EXPE 0 Port 5 EXPE 1 T T Kept Kept I O port EXPE 0 Port 6 EXPE 1 T T Kept Kept D7 to D0 I O port D7 to D0 EXPE 0 I O port Port 7 EXPE 1 T T T T Input port EXPE 0 Port 8 EXPE 1 T T Kept Kept I O port EXPE 0 Port 97...

Page 734: ... 1 T T Kept Kept I O port EXPE 0 I O port Port B EXPE 1 T T Kept Kept I O port EXPE 0 Port C EXPE 1 T T Kept Kept EXPE 0 I O port PC7 to PC4 are input ports Legend H High level L Low level T High impedance Kept Input ports are in the high impedance state when DDR 0 and PCR 1 the input pull up MOS remains on Output ports retain their previous state Depending on the pins the on chip peripheral modul...

Page 735: ...697 of 704 B Product Lineup Product Type Type Code Mark Code Package Code H8S 2437 F ZTAT version HD64F2437F DF2437F 128 pin QFP FP 128B H8S 2437 F ZTAT version HD64F2437FV DF2437FV 128 pin QFP FP 128B Note Pb free version ...

Page 736: ...y Package Code JEDEC JEITA Mass reference value FP 128B Conforms 1 7 g Dimension including the plating thickness Base material dimension 0 10 M 20 16 0 0 2 65 38 128 0 5 0 10 1 0 0 5 0 2 3 15 Max 0 8 22 0 0 2 102 64 39 103 1 0 22 0 05 14 0 17 0 05 2 70 0 10 0 15 0 10 0 75 0 75 0 20 0 04 0 15 0 04 Unit mm Figure C 1 Package Dimensions FP 128B ...

Page 737: ...43 Register indirect with post decrement 44 Register indirect with pre decrement 44 ADI 517 ASTCR 95 Asynchronous Mode 442 basic pulse 223 Bcc 31 39 bit rate 436 Boot Mode 551 BRR 436 636 648 659 Buffer Operation 334 Carrier frequency 219 Cascaded Connection 287 Cascaded Operation 337 CBLANK Output 398 Clamp Waveform Generation 382 Clear Timing 408 Clock Pulse Generator 611 Clocked Synchronous Mod...

Page 738: ... ICCRB 480 643 655 665 ICDRR 489 643 655 665 ICDRS 490 ICDRT 489 643 655 665 ICIA 260 ICIB 260 ICIC 260 ICID 260 ICIER 483 643 655 665 ICIX 291 ICMR 482 643 655 665 ICR 242 638 650 661 ICSR 489 643 655 665 IER 71 636 647 659 IHI signal divided waveform 385 Increment Timing 407 Input Capture 254 Input Capture Function 330 Input Capture Operation 289 input pull up MOS control register 131 input pull...

Page 739: ... 642 654 665 P6DR 174 642 654 664 P6ODR 175 643 654 665 P8DDR 183 642 654 665 P8DR 184 642 654 664 P9DDR 189 642 654 665 P9DR 190 642 654 664 parity error 449 PCSR 231 645 656 667 Periodic count operation 328 PFCR 191 643 654 665 Phase Counting Mode 343 Pin Arrangement 3 Pin Functions 9 PORT0 137 641 653 664 PORT1 140 641 653 664 PORT2 144 641 653 664 PORT3 156 641 653 664 PORT4 163 642 653 664 PO...

Page 740: ...2 SYSCR 53 641 653 663 TCI0V 348 TCI1U 348 TCI1V 348 TCI2U 348 TCI2V 348 TCNT 323 418 644 656 667 TCONRI 369 639 651 662 TCONRO 372 639 651 662 TCONRS 375 639 651 662 TCORA 273 639 650 661 TCORB 273 639 650 661 TCORC 282 639 650 661 TCR 248 305 638 650 661 TCSR 245 645 656 667 TDR 428 636 648 659 TEI0 468 TEI1 468 TEI2 468 TGI0A 348 TGI0B 348 TGI0C 348 TGI0D 348 TGI1A 348 TGI1B 348 TGI2A 348 TGI2B...

Page 741: ...Rev 1 00 09 03 page 703 of 704 user memory MAT 525 User Program Mode 555 VSYNCO Output 397 Watchdog Timer WDT 417 Watchdog Timer Mode 420 Waveform Output by Compare Match 329 WOVI 422 ...

Page 742: ...Rev 1 00 09 03 page 704 of 704 ...

Page 743: ...ev 1 00 September 19 2003 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Technical Documentation Information Department Renesas Kodaira Semiconductor Co Ltd 2003 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 744: ...acher Str 3 D 85622 Feldkirchen Germany Tel 49 89 380 70 0 Fax 49 89 929 30 11 Renesas Technology Hong Kong Ltd 7 F North Tower World Finance Centre Harbour City Canton Road Hong Kong Tel 852 2265 6688 Fax 852 2375 6836 Renesas Technology Taiwan Co Ltd FL 10 99 Fu Hsing N Rd Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Shanghai Co Ltd 26 F Ruijin Building No 205 Maoming...

Page 745: ......

Page 746: ...H8S 2437 Group Hardware Manual REJ09B0059 0100Z ...

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