Rabbit 6000 User’s Manual
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35.2 Dependencies
35.2.1 I/O Pins
The I
2
C peripheral can transmit and receive data on parallel port pins E0 or E4, and can transmit a clock
on E1 or E5. These options are selected in SGMCR.
The glitch filtering built in to the I
2
C peripheral does not meet the 50 ns requirement at system clocks over
140 MHz. When using clock speeds above 140 MHz, it is recommended to add a ferrite bead rated at
1000
at 100 MHz to both the SCL and SDA lines to provide additional glitch filtering. See Texas Instru-
ments Application Report SLEA053 for more information.
35.2.2 Clocks
In the master mode, the data clock for the I
2
C peripheral is based on the peripheral clock and is divided by
the 16-bit divider in SGCDxR. In the slave mode, the external master provides the clock.
35.2.3 Other Registers
35.2.4 Interrupts
An I
2
C interrupt can be generated whenever one of the following occurs.
•
Start condition detected
•
Stop condition detected
•
Slave address match or general call
•
Byte received
•
Byte transmitted
•
Arbitration lost (master mode)
•
non-ACK response (master mode)
The interrupt selection is in SGC1R.
The I
2
C interrupt vector is located in the IIR at offset 0x150. It can be set as Priority 1, 2, or 3 in SGMCR.
Table 35-1. Pin Usage I
2
C
Function
Parallel Port
Pin Options
Data (SDA)
PE0, PE4
Clock (SCL)
PE1, PE5
Register
Function
PEFR, PEAHR,
PEALR
Alternate port output selection
Summary of Contents for 6000
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