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Rabbit 6000 User’s Manual
digi.com
64
5.3.4 Memory Modes
The Rabbit 6000 supports both 8-bit and 16-bit memories on all chip selects, including both internal
RAMs. It also provides support for page-mode devices. The mode for each chip select is set in MACR; 8-
bit mode is the default for all chip selects.
When in basic 8-bit mode, the wait states are selected in the memory bank registers, MBxCR; the options
are 0, 1, 2, or 4 wait states. Note that this may put an upper bound on the processor clock speed, depending
on the access time of your 8-bit memory device. When in 16-bit or page-mode (either 8- or 16-bit), the
wait states are selected by both the MBxCR and the advanced chip select registers, ACSxCR.
A 16-bit memory device may or may not support byte writes, so there is an option to select between these
two cases in ACSxCR. With the default option any byte writes or unaligned word writes to a 16-bit mem-
ory will be suppressed (i.e., the /WE will not be asserted). Any aligned word reads or writes are recognized
internally and are combined into just one write transaction on the external bus. The other option for the 16-
bit bus does not inhibit byte writes or unaligned word writes, and replicates the byte data on both halves of
the data bus in these cases. In this mode the A0 and /A0 signals must be used by the memory to enable the
individual bytes.
Table 5-2. Memory Modes
Mode
Byte
Writes?
Word
Reads?
Word
Writes?
Wait State
Register
Wait State
Options
8-bit
Yes
No
No
MBxCR
0, 1, 2, 4
16-bit
Selectable
Yes
Yes
MBxCR
ACSxCR
0–19
8-bit Page Mode
Yes
No
No
MBxCR
ACSxCR
0–19 first access,
0–11 page
accesses
16-bit Page Mode
Selectable
Yes
Yes
MBxCR
ACSxCR
0–19 first access,
0–11 page
accesses
Table 5-3. A0 and /A0 Signals for Various Transaction Types
Transaction Type
A0
/A0
Word Read (prefetch only)
Low
Low
Word Write
Low
Low
Byte Read or Write — Even
Address
Low
High
Byte Read or Write — Odd Address
High
Low
Summary of Contents for 6000
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