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Rabbit 6000 User’s Manual
digi.com
16
2. C
LOCKS
2.1 Overview
The Rabbit 6000 supports up to five separate clocks at once—the main clock, the 32 kHz clock, the 20
MHz Wi-Fi clock, the 25 MHz Ethernet clock, and the 48 MHz USB clock. The main clock is used to
drive the processor clock and the peripheral clock inside the processor. The 32 kHz clock is used to drive
the asynchronous serial bootstrap, the real-time clock, the periodic interrupt, and the watchdog timers.
The 32 kHz clock input requires an external clock signal; the remaining clock inputs have internal oscilla-
tors that can be driven with just an external crystal. If desired, each of the remaining clock inputs can also
be used with an external clock as well, bypassing the internal oscillator.
The Ethernet peripheral can be driven from the main clock instead of the PHY clock input, removing the
need for separate main and Ethernet clocks. When this feature is enabled, the main clock must be 25 MHz
for proper Ethernet operation.
The main clock can be fed into a phase-locked loop (PLL), generating CPU and peripheral clocks in the
range of 150–200 MHz, depending on the input clock and PLL settings. This clock can be further adjusted
by the clock divider if desired. Dividers exist for most peripherals to scale their clocks over a wide range
of frequencies.
The Rabbit 6000 has a spectrum spreader on the main clock that shortens and lengthens clock cycles. This
has the net effect of reducing the peak energy of clock harmonics by spreading the spectral energy into
nearby frequencies, which reduces EMI and facilitates government-mandated EMI testing. Gated clocks
are used whenever possible to avoid clocking unused portions of the processor, and separate power-supply
pins for the core and I/O ring further reduce EMI from the Rabbit 6000. Note that the spectrum spreader is
not usable at main clock frequencies above 115 MHz because of the short period.
The main clock can be doubled or divided by 2, 4, 6, or 8 to reduce EMI and power consumption. The 32
kHz clock (which can be divided by 2, 4, 8, or 16) can be used instead of the main clock to generate pro-
cessor and peripheral clocks as low as 2 kHz for significant power savings. Note that dividing the 32 kHz
clock only affects the processor and peripheral clocks; the full 32 kHz signal is still provided to the real-
time clock and watchdog timer peripherals that use it directly. The periodic interrupt is disabled automati-
cally since there is not enough time to process it when it is running off the 32 kHz clock. Also, note that
the internal RAM content will not be maintained at CPU frequencies below 12MHz.
There is also a 25 MHz Ethernet oscillator that connects directly to the Ethernet PHY if you are using the
Ethernet option, but want a different main clock frequency. See Chapter 25 for more details on the Ether-
net clock.
The Wi-Fi peripheral requires a 20 MHz clock input, which goes to a dedicated PLL to produce the
required clocks for the 802.11a/b/g peripheral. The USB peripheral requires a 48 MHz clock for proper
operation.
Summary of Contents for 6000
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