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Rabbit 6000 User’s Manual
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251
pair of control bytes, a byte count for the data, a source address, a destination address, and an optional link
address. In addition, each DMA channel retains a count of the number of bytes remaining in the buffer to
allow software to determine the amount of valid data in a buffer that are terminated early by the source of
the data.
A buffer descriptor in memory consists of either 12 or 16 consecutive bytes organized as shown in
Table 24-2. The DMA channel uses the information in the control byte to determine the length of the buf-
fer descriptor as well as which information to fetch from the buffer descriptor. If no link address field is
present, the buffer descriptor is only 12 bytes long. A memory address for either source or destination
causes the DMA channel to fetch three bytes from the corresponding field in the buffer descriptor. An
internal I/O or external I/O address for either source or destination causes the DMA channel to fetch two
bytes from the corresponding field in the buffer descriptor.
DMA memory addresses are always physical addresses, and are never translated by the MMU. All DMA
memory addresses use the memory control signals, wait states, and flipped bits as selected in the Master
Memory Bank Control registers. All DMA external I/O addresses use the I/O control signals and wait
states as selected in the external I/O registers.
The first byte in the first buffer descriptor (the byte pointed to by the initial address) is reserved for status
information when transferring data from an internal serial or network device. This automatic status transfer
means that the processor does not need to service any interrupts from a serial or network receiver except in
the case of an error condition.
When transferring data to an internal HDLC serial or Ethernet transmitter, the last byte of the last buffer
will be written automatically to a special destination address to tag the data as the last in the frame, without
processor intervention. However, this function is not available in the case where the buffer contains only
one byte of data. If this case should occur, the buffer descriptor must contain the special destination
address.
All the DMA channels request interrupts at the same priority level, which is set by a field in the DMA
Master Control Register, but each DMA channel has its own interrupt vector location. This speeds up
interrupt processing for the DMA interrupts by eliminating the need to resolve which DMA channel is
actually requesting an interrupt.
DMA transfers may be programmed to occur at any priority level. If the programmed level is greater than
or equal to the current CPU operating level, DMA transfers will occur on demand. When the CPU operat-
ing level is greater than the programmed DMA operating level, no DMA transfers can occur. This allows
interrupt services routines, or other critical code, to run with a guarantee that there will be no DMA activ-
ity during execution. Note that a simultaneous interrupt request and DMA transfer request will be resolved
in favor of the DMA transfer request.
Summary of Contents for 6000
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