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Rabbit 6000 User’s Manual
digi.com
258
24.3.3 DMA Priority with the Processor
When the bus-interleaving mode is in use, DMA transfers will not interrupt the CPU code execution, so
the priority is of less importance than when the bus-sharing mode is in use. In that situation, normal code
execution cannot occur while the DMA is active. This includes handling interrupts, so it is important to
limit the amount of time that the DMA can operate if the bus-sharing mode is used.
This is handled in several ways. First of all, the DMA transfers can be set to take place whenever the pro-
cessor is operating at one of the four priority levels, 0–3 (note that there is a single priority level for all
DMA transfers).
Setting an interrupt priority to something greater than the DMA transfer priority will ensure that no DMA
activity occurs during that interrupt handler. Note that when both an interrupt and a DMA transfer are
pending, the DMA transfer will be selected for execution first (provided its priority is equal or greater than
the current processor priority level).
When a DMA transfer is occurring in the bus-sharing mode, normal code execution will not occur until the
transfer is completed. To prevent DMA transfers from excessively blocking interrupts or otherwise inter-
fering with normal code execution, two options can be set in DMTCR. First, the maximum limit of a DMA
transfer can be set from 1 to 64 bytes, which sets an upper limit on interrupt latency arising from a DMA
transfer. Second, the minimum number of clocks before the DMA can be active again can be set from 12 to
512 clocks, guaranteeing processing time for the application.
The values providing roughly equal access to the memory bus for both the processor and the DMA is eight
bytes per burst and 64 clocks between bursts.
If you are using the bus-interleaving mode, set the maximum burst size in DCSTCR.
The DMA requires several cycles of overhead when starting up. This overhead comes about because the
DMA actually uses part of the processor to perform the data transfers, and consists of one instruction fetch
time plus three clock cycles. The byte fetched during the instruction fetch time is discarded, and will be
refetched at the completion of the DMA burst. At the end of the DMA burst, two clock cycles are required
before this first instruction fetch starts. An individual DMA channel transfers data without any overhead
between bytes, but there is always one clock cycle of dead time when switching between DMA channels.
Table 24-4 shows the effective number of clock cycles required per burst, assuming a single DMA channel
transfer, 8-bit memory, and no wait states. Access via 16-bit memory would provide up to twice the
throughput, depending on the address alignment.
Table 24-3. DMA Transfer Priority
DMA Transfers at
Operation
Priority 0
DMA transfers only allowed when
processor priority at 0
Priority 1
DMA transfers only allowed when
processor priority at 0 or 1
Priority 2
DMA transfers only allowed when
processor priority at 0, 1, or 2
Priority 3
DMA transfers allowed at any time
Summary of Contents for 6000
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