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Rabbit 6000 User’s Manual

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24.4 Register Descriptions

DMA Master Control/Status LSB Register

(DMCSLR)

(Address = 0x0100)

Bit(s)

Value

Description

7:0

0

No effect on the corresponding DMA channel (7–0).

(Write-

only)

1

Start (or restart) the corresponding DMA channel (7–0) using the contents
of the DMA channel registers. This command should only be issued after
all the DMA channel registers (source, destination, length, and link if
applicable) have been loaded.

7:0

0

The corresponding DMA channel (7–0) is either disabled or has
completed the last buffer descriptor.

(Read-

only)

1

The corresponding DMA channel (7–0) is enabled and active. These bits
are set by the start command and remain set until the completion of the
last buffer.

DMA Master Control/Status MSB Register

(DMCSMR)

(Address = 0x0101)

Bit(s)

Value

Description

7:0

0

No effect on the corresponding DMA channel (15–8).

(Write-

only)

1

Start (or restart) the corresponding DMA channel (15–8) using the
contents of the DMA channel registers. This command should only be
issued after all the DMA channel registers (source, destination, length,
and link if applicable) have been loaded.

7:0

0

The corresponding DMA channel (15–8) is either disabled or has
completed the last buffer descriptor.

(Read-

only)

1

The corresponding DMA channel (15–8) is enabled and active. These bits
are set by the start command and remain set until the completion of the
last buffer.

DMA Master Auto-Load LSB Register

(DMALLR)

(Address = 0x0110)

Bit(s)

Value

Description

7:0

0

No effect on the corresponding DMA channel (7–0).

(wr-only)

1

Start (using auto-load) the corresponding DMA channel (7-0), using the buffer
descriptor in memory addressed by the channel Initial Address Register. This
command should only be issued after the Initial Address has been loaded.

7:0

0

The corresponding DMA channel (7-0) is either disabled or has completed the
last buffer descriptor.

(rd-only)

1

The corresponding DMA channel (7-0) is enabled and active. These bits are set
by the Start command and remain set until the completion of the last buffer or
receipt of a Halt command.

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Summary of Contents for 6000

Page 1: ...Rabbit 6000 Microprocessor User s Manual 90001108_J...

Page 2: ...ernational reserves the right to make changes and improvements to its products without providing notice Trademarks Rabbit and Dynamic C are registered trademarks of Digi International Inc Rabbit 6000...

Page 3: ...isters 44 4 2 Dependencies 45 4 2 1 I O Pins 45 4 2 2 Clocks 45 4 2 3 Interrupts 45 4 3 Operation 46 4 3 1 Periodic Interrupt 46 4 3 2 Real Time Clock 46 4 3 3 Watchdog Timer 47 4 3 4 Secondary Watchd...

Page 4: ...Register Descriptions 131 13 Parallel Port F 13 1 Overview 136 13 1 1 Block Diagram 138 13 1 2 Registers 139 13 2 Dependencies 139 13 2 1 I O Pins 139 13 2 2 Clocks 139 13 2 3 Other Registers 139 13...

Page 5: ...er Setup 220 21 3 2 Slave Setup 220 21 3 3 Master Slave Communication 221 21 3 4 Slave Master Communication 221 21 3 5 Handling Interrupts 221 21 3 6 Example ISR 221 21 3 7 Other Configurations 222 21...

Page 6: ...t Mode 327 28 4 Register Descriptions 328 29 Quadrature Decoder 29 1 Overview 333 29 1 1 Block Diagram 335 29 1 2 Registers 335 29 2 Dependencies 336 29 2 1 I O Pins 336 29 2 2 Clocks 336 29 2 3 Other...

Page 7: ...ave Mode Data Read 394 35 4 Register Descriptions 395 36 Low Power Operation 36 1 Overview 403 36 1 1 Registers 404 36 2 Operation 405 36 2 1 Unused Pins 405 36 2 2 Unused Peripherals 405 36 2 3 Clock...

Page 8: ...bit now a Digi International brand running at up to 200 MHz with compact code and support for up to 16 MB of memory Operating with a 1 2 V core and 3 3 V I O the Rabbit 6000 boasts 16 channels of DMA...

Page 9: ...t data bus three chip select lines two output enable lines and two write enable lines can be interfaced directly with up to six memory devices Up to 1 MB of code memory and 15 MB of data memory can be...

Page 10: ...O addresses and the external I O bus Directing a DMA channel to or from an internal peripheral such as a serial port or the Ethernet port automatically connects DMA enable signals Burst size priority...

Page 11: ...Rabbit 6000 User s Manual digi com 11 1 3 Block Diagram Figure 1 1 Rabbit 6000 Block Diagram...

Page 12: ...MHz Digital I O 64 arranged in eight 8 bit ports Network Interfaces 10 100Base T 802 11b g Wi Fi Serial Ports 6 CMOS compatible 2 CMOS compatible Baud Rate Clock speed 8 max asynchronous I2 C Ports 1...

Page 13: ...peration Voltage I O 1 2 V 10 3 3 V 10 1 8 V 10 3 3 V 10 1 8 V 10 3 3 V 10 Maximum I O Input Voltage 3 6 V 3 6 V 3 6 V 5 5 V 5 5 V Current Consumption 32kHz 200MHz 0 37 mA MHz 1 2 V 3 3 V Wi Fi and Et...

Page 14: ...5 7 5 External I O Data Address Bus Yes Yes Yes Yes None Number of Serial Ports 6 6 6 6 4 DMA Channels 16 8 8 None None Serial Ports Capable of SPI Clocked Serial 4 A B C D 4 A B C D 4 A B C D 4 A B...

Page 15: ...erface Modules 2 None None None None Hardware Breakpoints 7 7 7 None None User A D Converter Channels 8 None None None None A D Converter Channels Wi Fi disabled 3 3 None None None D A Converter Chann...

Page 16: ...e net effect of reducing the peak energy of clock harmonics by spreading the spectral energy into nearby frequencies which reduces EMI and facilitates government mandated EMI testing Gated clocks are...

Page 17: ...ol Status Register GCSR 0x0000 R W 11000000 Global Clock Modulator 0 Register GCM0R 0x000A W 00000000 Global Clock Modulation 1 Register GCM1R 0x000B W 00000000 Global Clock Double Register GCDR 0x000...

Page 18: ...he pins assigned to each clock and how they are controlled The 32 kHz clock input is on the CLK_32K pin There is an internal Schmitt trigger on this pin to reduce sensitivity to noise The peripheral c...

Page 19: ...in clock or external 25 MHz clock for Ethernet select CPU clock or PLL output for Flexible Interface Modules MSSR Used to select crystal or external oscillator for Wi Fi and USB clocks and read main a...

Page 20: ...clock operates at full speed this allows some power reduction while keeping settings like serial baud rates and the PWM at their desired values When the 32 kHz clock is enabled in GCSR it can be furt...

Page 21: ...the output frequency range is limited to 300 400 MHz There are further restrictions on the internal frequency The main PLL divider values are located in GCM0R and GCM1R These should be set to a nonzer...

Page 22: ...preader There are three settings that correspond to normal and strong spreading in the 0 50 MHz and 50 MHz main clock range Each setting will affect the clock cycle differently the maximum cycle short...

Page 23: ...with proper time delays GCM0R is only read by the spectrum spreader at the moment when the spectrum spreader is enabled by setting bit 7 of GCM1R If bit 7 of GCM1R is cleared when disabling the spect...

Page 24: ...r GCDR The clock doubler uses an on chip delay circuit that must be programmed by the user at startup if there is a need to double the clock Table 2 5 lists the recommended delays in GCDR for various...

Page 25: ...or decrease in temperature The doubled clock is created by xor ing the delayed and inverted clock with itself If the original clock does not have a 50 50 duty cycle then alternate clocks will have a s...

Page 26: ...the clock as part of a power management scheme 2 3 5 32 kHz Clock The 32 768 kHz clock is used to drive the asynchronous serial bootstrap the real time clock the periodic interrupt and the watchdog ti...

Page 27: ...ing Crystals with low series resistance R 35 k will start faster The 32 kHz oscillator can be used to drive the processor and the peripheral clock to provide significant power savings in ultra sleepy...

Page 28: ...heral clock from the main clock 010 Processor clock from the main clock Peripheral clock from the main clock 011 Processor clock from the main clock divided by 2 Peripheral clock from the main clock d...

Page 29: ...PLL output frequency is the input frequency divided by the value of the PLL pre divider and multiplied by the value of the PLL loop divider Neither divider value should not be modified while the PLL i...

Page 30: ...uit is disabled 00001 9 nS nominal Low time 00010 10 5 nS nominal Low time 00011 12 nS nominal Low time 00100 13 5 nS nominal Low time 00101 15 nS nominal Low time 00110 16 5 nS nominal Low time 00111...

Page 31: ...first opcode byte fetch 01 STATUS pin is active low during an interrupt acknowledge 10 STATUS pin is low 11 STATUS pin is high 3 2 00 WDTOUT pin functions normally 01 Enable WDTOUT for test mode Reser...

Page 32: ...nternal 10 100 PHY Reads always return zero Write only 1 Reset the internal 10 100 PHY hardware This command must not be issued until at least 600 ms after the internal PHY has been enabled in ENPR Th...

Page 33: ...ystal oscillator 4 0 Direct USB clock input 1 Enable USB crystal oscillator 3 0 Normal operation Read only 1 Small package address and data bus option enabled TEST 0xF or 0xC 2 0 Large package Read on...

Page 34: ...port 4 0 Internal 10 100 PHY This bit is ignored unless bit 6 of this register is also set at which point the internal PHY is powered up 1 External 10 100 PHY 3 2 00 Network Port D interrupts are dis...

Page 35: ...he Rabbit 6000 checks the state of the SMODE and SYSCFG pins Depending on the state of the SMODE pins it either begins normal operation by fetching instruction bytes from memory bank zero which is map...

Page 36: ...Rabbit 6000 User s Manual digi com 36 3 1 1 Block Diagram 3 1 2 Registers Register Name Mnemonic I O Address R W Reset Slave Port Control Register SPCR 0x0024 R W 0xx00000...

Page 37: ...CS1 In this case a pullup resistor is required on CS1 to keep the RAM deselected during powerdown RESOUT The RESOUT pin which is powered by the backup battery is high during reset and power down as lo...

Page 38: ...required on CS1 to keep the RAM deselected during powerdown The RESOUT pin which is powered by the backup battery is high during reset and powerdown as long as VBAT and VBATIO are present but low at a...

Page 39: ...e third byte is the data to be written If the uppermost bit of the address is 1 then the address is assumed to be an internal register address instead of a memory address and the data are written to t...

Page 40: ...nput so a 32 kHz clock is required for this mode 3 3 2 Serial Flash Bootstrap When the serial flash bootstrap mode is selected by the SMODE pins the Rabbit 6000 will enable the SPI serial flash bootst...

Page 41: ...with zero 4 2 000 Disable the slave port Parallel Port A is a byte wide input port 001 Disable the slave port Parallel Port A is a byte wide output port 010 Enable the slave port with SCS from Paralle...

Page 42: ...ates a Priority 3 second ary watchdog interrupt when it is not reset within that time The primary use for the secondary watchdog is to act as a safety net for the periodic interrupt if the secondary w...

Page 43: ...Rabbit 6000 User s Manual digi com 43 4 1 1 Block Diagram...

Page 44: ...Time Clock Byte 5 Register RTC5R 0x0007 R xxxxxxxx Watchdog Timer Control Register WDTCR 0x0008 W 00000000 Watchdog Timer Test Register WDTTR 0x0009 W 00000000 Secondary Watchdog Timer Register SWDTR...

Page 45: ...low during external I O cycles active low during data memory cycles or driven high or low The values in the battery backed onchip encryption RAM bytes are cleared if the signal on the SMODE pins chan...

Page 46: ...be read again Writing to RTC0R latches the current real time clock value into the RTCxR holding registers so the fol lowing sequence should be used to read the real time clock 1 Write any value to RT...

Page 47: ...period to SWDTR or writing 0x5F to WDTCR If the secondary watchdog timer counts down to zero a Priority 3 secondary watchdog interrupt will occur This interrupt request is cleared by writing a new tim...

Page 48: ...heral clock from the main clock 010 Processor clock from the main clock Peripheral clock from the main clock 011 Processor clock from the main clock divided by 2 Peripheral clock from the main clock d...

Page 49: ...the reset function 0xC0 Reset all six bytes of the real time clock counter to 0x00 and remain in byte increment mode in preparation for setting the time 7 6 01 This bit combination must be used with e...

Page 50: ...mer Test Register WDTTR Address 0x0009 Bit s Value Description 7 0 0x51 Clock the least significant byte of the watchdog timer from the peripheral clock 0x52 Clock the most significant byte of the wat...

Page 51: ...ce 0x5A 0x52 0x44 to this register Global ROM Configuration Register GROM Address 0x002C Bit s Value Description 7 0 Program fetch as a function of the SMODE pins Read only 1 Ignore the SMODE pins pro...

Page 52: ...pin functions normally 01 Enable WDTOUT for test mode Reserved for internal use only 10 WDTOUT pin is low 1 cycle min 2 cycles max of 32 kHz 11 This bit combination is reserved and should not be used...

Page 53: ...ead only 1 Ignore the SMODE pins program fetch function 6 5 Read These bits report the state of the SMODE pins 4 0 00000 CPU identifier for this version of the chip Battery Backed Onchip Encryption RA...

Page 54: ...e Rabbit 6000 contains 1 MB of internal high speed RAM and 32 KB of battery backed SRAM also high speed that reside on their own chip select signal They can both be enabled in either the 8 bit or the...

Page 55: ...mapped directly to physical address 0x000000 while the data and stack segments can be mapped to 4 KB boundaries anywhere in the physical space The boundaries between the root and data segments and the...

Page 56: ...nificant bit of the bank select bits is inverted for all data accesses in the root and or data segments before bank selection physical device occurs These two features allow both code and data to acce...

Page 57: ...Rabbit 6000 User s Manual digi com 57 5 1 1 Block Diagram...

Page 58: ...xxxxxxx MMU Expanded Code Register MECR 0x0018 R W 00000000 Memory Timing Control Register MTCR 0x0019 R W 00000000 Memory Alternate Control Register MACR 0x001D R W 00000000 Memory Bank 0 Low Control...

Page 59: ...Protect Segment B Low Register WPSBLR 0x0485 W 00000000 Write Protect Segment B High Register WPSBHR 0x0486 W 00000000 Stack Limit Control Register STKCR 0x0444 R W 00000000 Stack Low Limit Register S...

Page 60: ...ess and data bus pins and for the memory strobe pins except CS1 via ADPCR DBPCR and CPCR CS1 has a fixed setting of 8 mA drive and fast slew Internal pullup and or pulldown resistors are also selectab...

Page 61: ...ng as 1 2 V is kept on VBAT 5 3 2 Memory Management Unit MMU Code execution takes place in the 64 KB logical memory space which is divided into four segments root data stack and extended XMEM The root...

Page 62: ...a valid setting before use If SYSCFG is high Memory Bank 0 is enabled to use CS3 OE0 and WE0 in 16 bit mode This allows the processor to start operation directly out of the internal 1 MB RAM The size...

Page 63: ...WE strobes by one half of a clock This provides slightly longer strobes for slower memories see the timing diagrams in Chapter 37 These options are available in MTCR It is possible to force CS1 to be...

Page 64: ...byte writes or unaligned word writes to a 16 bit mem ory will be suppressed i e the WE will not be asserted Any aligned word reads or writes are recognized internally and are combined into just one wr...

Page 65: ...t enable signals The logic recognizes which OE is being used with each chip select in the Page Mode As mentioned previously the ACSxCR registers each contain three fields to control the generation of...

Page 66: ...provides a shortcut for updating code by accessing it as data It pro vides a window that uses the instruction address decoding when read or written as data This mapping will only occur when the RAMSR...

Page 67: ...tection registers to dis able it set all the write protect block registers to zero 5 3 7 Stack Protection The Rabbit 6000 provides stack overflow and underflow protection Low and high logical address...

Page 68: ...n with zero 5 0 Enable A16 and bank select address MSB inversion independent of instruction data 1 Enable A16 and bank select address MSB inversion for data accesses only This enables the instruction...

Page 69: ...of physical address offset to use if SEGSIZ 7 4 Addr 15 12 0xE Stack Segment High Register STACKSEGH Address 0x001B Bit s Value Description 7 4 These bits are reserved and should always be written as...

Page 70: ...4 These bits are reserved and should always be written as zero These bits always return zeros when read 3 0 Four MSBs of physical address offset to use if SEGSIZ 3 0 Addr 15 12 SEGSIZ 7 4 Segment Siz...

Page 71: ...4 0 Pass bank select address LSB for accesses in this bank 1 Invert bank select address LSB for accesses in this bank 3 2 00 OE0 and WE0 are active for accesses in this bank 01 OE1 and WE1 are active...

Page 72: ...bank select address MSB for accesses in this bank 4 0 Pass bank select address LSB for accesses in this bank 1 Invert bank select address LSB for accesses in this bank 3 2 00 OE0 and WE0 are active f...

Page 73: ...e used 111 Bank Select Address is A18 A17 4 This bit is reserved and should be written with zero Read returns zeros 3 0 0000 Normal operation 0001 This bit combination is reserved and should not be us...

Page 74: ...clock earlier than normal 2 0 Normal timing for OE0 rising edge to rising edge one clock minimum 1 Extended timing for OE0 one half clock earlier than normal 1 0 Normal timing for WE1 rising edge to...

Page 75: ...by strapping a pin this bit is forced high 6 This bit is reserved and must not be used 5 4 00 Normal 8 bit operation for CS2 01 Page Mode 8 bit operation for CS2 10 Normal 16 bit operation for CS2 11...

Page 76: ...e Mode read access 111 Seven extra wait state for reads writes or first Page Mode read access 4 3 00 Zero extra wait states for subsequent Page Mode accesses 01 One extra wait state for subsequent Pag...

Page 77: ...rite Protect Segment x Register WPSAR Address 0x0480 WPSBR Address 0x0484 Bit s Value Description 7 0 When these eight bits 23 16 match bits of the physical address write protect that 64 KB range in 4...

Page 78: ...able 4 KB write protect for relative address 0x4000 0x4FFF in WP Segment x 1 Enable 4 KB write protect for relative address 0x4000 0x4FFF in WP Segment x 3 0 Disable 4 KB write protect for relative ad...

Page 79: ...sable 4 KB write protect for relative address 0xC000 0xCFFF in WP Segment x 1 Enable 4 KB write protect for relative address 0xC000 0xCFFF in WP Segment x 3 0 Disable 4 KB write protect for relative a...

Page 80: ...interrupt is generated Stack High Limit Register STKHLR Address 0x0446 Bit s Value Description 7 0 Upper limit for stack limit checking If a stack operation or stack relative memory access is attempt...

Page 81: ...reserved and should be written with zeros 4 0 Fast output slew rate 1 Slow output slew rate 3 2 00 4 mA output drive capability 01 8 mA output drive capability 10 10 mA output drive capability 11 14...

Page 82: ...on 7 5 These bits are reserved and should be written with zeros 4 0 Fast output slew rate 1 Slow output slew rate 3 2 00 4 mA output drive capability 01 8 mA output drive capability 10 10 mA output dr...

Page 83: ...t actu ally enter Priority 3 any attempt to enter Priority 3 will actually be requested as Priority 2 When an interrupt is handled a call is executed to a fixed location in the interrupt vector tables...

Page 84: ...he internal interrupt vector table The first column is the vector address offset within the table The second column shows the vectors in the first 256 bytes of the table and the third column shows the...

Page 85: ...t Vector Table Structure Offset 0x0000 Offset 0x0100 Offset 0x00 External Interrupt 0 0x10 External Interrupt 1 0x20 External Interrupt 2 0x30 External Interrupt 3 0x40 External Interrupt 4 Breakpoint...

Page 86: ...TCCSR Slave Port Rd Read from SPD0R SPD1R or SPD2R Wr Write to SPD0R SPD1R SPD2R or dummy write to SPSR DMA 15 0 Cleared automatically by interrupt acknowledge cycle Network Port B Read interrupt stat...

Page 87: ...rt s being used can be read Each interrupt vector can be set to trigger on a rising edge a falling edge or both edges The signal on the external interrupt pin must be present for at least three periph...

Page 88: ...Rabbit 6000 User s Manual digi com 88 7 2 Block Diagram...

Page 89: ...Control Register I1CR 0x0099 R W 00000000 Interrupt 2 Control Register I2CR 0x009A R W xx000000 Interrupt 3 Control Register I3CR 0x009B R W xx000000 Interrupt 4 Control Register I4CR 0x009C R W xx000...

Page 90: ...s to trigger an interrupt 7 3 3 Interrupts An external interrupt is generated whenever the selected edge occurs on an enabled pin The interrupt request is automatically cleared when the interrupt is h...

Page 91: ...errupts what edges are detected on each pin and the interrupt priority 3 When an interrupt occurs for interrupt 0 or 1 read PDDR and or PEDR to determine which pin has a signal if more than one pin is...

Page 92: ...e interrupt disabled 01 Parallel Port E high nibble interrupt on falling edge 10 Parallel Port E high nibble interrupt on rising edge 11 Parallel Port E high nibble interrupt on both edges 3 2 00 Para...

Page 93: ...t bit 1 010 Interrupt from parallel port bit 2 011 Interrupt from parallel port bit 3 100 Interrupt from parallel port bit 4 101 Interrupt from parallel port bit 5 110 Interrupt from parallel port bit...

Page 94: ...arallel Port A can also be used as an external I O data bus to isolate external I O from the main data bus The drive strength and slew rate can be individually controlled for each Parallel Port A pin...

Page 95: ...User s Manual digi com 95 8 1 1 Block Diagram 8 1 2 Registers Register Name Mnemonic I O Address R W Reset Port A Data Register PADR 0x0030 R W xxxxxxxx Port Ax Control Register x 0 7 PAxCR 0x04B0 x...

Page 96: ...write 0x08C to SPCR All Parallel Port A bits are inputs at startup or reset Drive strength slew rate and the pullup down resistor status are selectable via PAxCR See the associated peripheral chapters...

Page 97: ...ata can be read or written by accessing PADR Note that Parallel Port A is not available for general purpose I O while the slave port or the external I O bus is selected or when it is being used by one...

Page 98: ...rallel Port Ax Control Register PA0CR Address 0x04B0 PA1CR Address 0x04B1 PA2CR Address 0x04B2 PA3CR Address 0x04B3 PA4CR Address 0x04B4 PA5CR Address 0x04B5 PA6CR Address 0x04B6 PA7CR Address 0x04B7...

Page 99: ...the slave port with SCS from Parallel Port E bit 7 011 Enable the external I O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combinatio...

Page 100: ...llel Port B pin When the external I O bus option is enabled either six or eight pins carry the external I O address signals selected in SPCR Two pins are used for the clocks for Serial Ports A and B w...

Page 101: ...7 and two outputs bits 0 1 When PBDR is read the actual voltage on the pins is returned whether the pins are set as inputs or out puts 9 1 1 Block Diagram Table 9 2 Parallel Port B Pin Alternate Inpu...

Page 102: ...enabled in SPCR the Parallel Port B pins associated with those peripherals perform those actions no matter what the settings are in PBDR or PBDDR See the associated peripheral chapters for details on...

Page 103: ...llel Port B pin set that in the appropriate PBxCR 3 If the slave port or the external I O bus is selected refer to the chapters for those peripherals for fur ther setup information Once the port is se...

Page 104: ...0 The corresponding port bit is an input 1 The corresponding port bit is an output Parallel Port Bx Control Register PB0CR Address 0x04C0 PB1CR Address 0x04C1 PB2CR Address 0x04C2 PB3CR Address 0x04C...

Page 105: ...e the slave port with SCS from Parallel Port E bit 7 011 Enable the external I O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combinati...

Page 106: ...and slew rate can be individually controlled for each Parallel Port C pin In addition a 75 k pullup or pulldown resistor can be enabled on each pin Note that it is possible for either Flexible Interfa...

Page 107: ...s sors these outputs are driven with a logic zero low on PC6 and a logic one high on PC4 PC2 and PC0 When PCDR is read the actual voltage on the pins is returned whether the pins are set as inputs or...

Page 108: ...a PCxCR See the associated peripheral chapters for details on how they use Parallel Port C 10 2 2 Clocks All outputs on Parallel Port C are clocked by the peripheral clock 10 2 3 Other Registers 10 2...

Page 109: ...n select it via PCALR or PCAHR and then enable it via PCFR Refer to the appropriate peripheral chapter for further use of that pin Once the port is set up data can be read or written by accessing PCDR...

Page 110: ...escription 7 6 00 Parallel Port C bit 3 alternate output 0 TXC 01 Parallel Port C bit 3 alternate output 1 I3 10 Parallel Port C bit 3 alternate output 2 TIMER C3 11 Parallel Port C bit 3 alternate ou...

Page 111: ...01 Parallel Port C bit 5 alternate output 1 I5 10 Parallel Port C bit 5 alternate output 2 PWM1 11 Parallel Port C bit 5 alternate output 3 RCLKE 1 0 00 Parallel Port C bit 4 alternate output 0 TXB 0...

Page 112: ...ddress 0x04D6 PC7CR Address 0x04D7 Bit s Value Description 7 5 These bits are reserved and should be written with zeros 4 0 Fast output slew rate 1 Slow output slew rate 3 2 00 4 mA output drive capab...

Page 113: ...either be programmed as open drain or driven high and low Because of the buffered nature of Parallel Port D a read modify write type of operation can lead to old data being written to PDDR To alleviat...

Page 114: ...Alternate Input Functions Pin Name Input Capture Serial Ports A D Serial Ports E F DMA External Interrupts Quad Decode PD7 yes RXA RXE PD6 PD5 yes RXB RCLKE PD4 TCLKE PD3 yes RXC RXF DREQ1 QD2A PD2 S...

Page 115: ...Rabbit 6000 User s Manual digi com 115 11 1 1 Block Diagram...

Page 116: ...0062 R W 00000000 Port D Alternate High Register PDAHR 0x0063 R W 00000000 Port D Control Register PDCR 0x0064 R W xx00xx00 Port D Function Register PDFR 0x0065 R W xxxxxxxx Port D Drive Control Regis...

Page 117: ...l chapters for details on how they use Parallel Port D 11 2 2 Clocks All outputs on Parallel Port D are clocked by the peripheral clock unless changed in PDCR where the option of updating the Parallel...

Page 118: ...a pin select it via PDALR or PDAHR and then enable it via PDFR Refer to the appropriate peripheral chapter for further use of that pin Once Parallel Port D is set up data can be read or written by ac...

Page 119: ...01 Parallel Port D bit 3 alternate output 1 I3 10 Parallel Port D bit 3 alternate output 2 TIMER C3 11 Parallel Port D bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port D bit 2 alternate output 0 SC...

Page 120: ...D bit 4 alternate output 0 TXB 01 Parallel Port D bit 4 alternate output 1 I4 10 Parallel Port D bit 4 alternate output 2 PWM0 11 Parallel Port D bit 4 alternate output 3 TCLKE Parallel Port D Contro...

Page 121: ...DDDR Address 0x0067 Bit s Value Description 7 0 0 The corresponding port bit is an input 1 The corresponding port bit is an output Parallel Port D Bit 0 Register PDB0R Address 0x0068 Bit s Value Descr...

Page 122: ...bit The port buffer will be transferred to the port output register on the next rising edge of the port transfer clock Parallel Port D Bit 4 Register PDB4R Address 0x006C Bit s Value Description 7 5...

Page 123: ...s bit The port buffer will be transferred to the port output register on the next rising edge of the port transfer clock Parallel Port D Bit 7 Register PDB7R Address 0x006F Bit s Value Description 6 0...

Page 124: ...ddress 0x04E6 PD7CR Address 0x04E7 Bit s Value Description 7 5 These bits are reserved and should be written with zeros 4 0 Fast output slew rate 1 Slow output slew rate 3 2 00 4 mA output drive capab...

Page 125: ...ause of the buffered nature of Parallel Port E using a read modify write type of operation can lead to old data being written to PEDR To alleviate this potential problem each bit of the port can be wr...

Page 126: ...I O Hand shake Serial Ports A D Serial Ports E F DMA External Interrupts Quad Decode USB PE7 yes yes RXA RXE DREQ1 QD2A PE6 yes DREQ0 QD2B PE5 yes yes RXB RCLKE INT1 QD1A PE4 yes TCLKE INT0 QD1B PE3...

Page 127: ...Rabbit 6000 User s Manual digi com 127 12 1 1 Block Diagram...

Page 128: ...0072 R W 00000000 Port E Alternate High Register PEAHR 0x0073 R W 00000000 Port E Control Register PECR 0x0074 R W xx00xx00 Port E Function Register PEFR 0x0075 R W 00000000 Port E Drive Control Regis...

Page 129: ...eral chapters for details on how they use Parallel Port E 12 2 2 Clocks All outputs on Parallel Port E are clocked by the peripheral clock unless changed in PECR where the option of updating the Paral...

Page 130: ...for a pin select it via PEALR or PEAHR and then enable it via PEFR Refer to the appropriate peripheral chapter for further use of that pin Once the port is set up data can be read or written by acces...

Page 131: ...l Port E bit 3 alternate output 1 no functionality 10 Parallel Port E bit 3 alternate output 2 TIMER C3 11 Parallel Port E bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port E bit 2 alternate output...

Page 132: ...E bit 5 alternate output 3 RCLKE 1 0 00 Parallel Port E bit 4 alternate output 0 I4 01 Parallel Port E bit 4 alternate output 1 SDATG 10 Parallel Port E bit 4 alternate output 2 PWM0 11 Parallel Port...

Page 133: ...r PEDDR Address 0x0077 Bit s Value Description 7 0 0 The corresponding port bit is an input 1 The corresponding port bit is an output Parallel Port E Bit 0 Register PEB0R Address 0x0078 Bit s Value De...

Page 134: ...his bit The port buffer will be transferred to the port output register on the next rising edge of the peripheral clock Parallel Port E Bit 4 Register PEB4R Address 0x007C Bit s Value Description 7 5...

Page 135: ...bit The port buffer will be transferred to the port output register on the next rising edge of the peripheral clock Parallel Port Ex Control Register PE0CR Address 0x04F0 PE1CR Address 0x04F1 PE2CR A...

Page 136: ...Timer B1 or Timer B2 can be used for this function with each nibble of the port having a separate select field to control this timing Each bit can either be programmed as open drain or driven high and...

Page 137: ...om 137 Table 13 2 Parallel Port F Pin Alternate Input Functions Pin Name External Interrupts FIM PF7 INT2 7 FIMA7 PF6 INT2 7 FIMA6 PF5 INT2 7 FIMA5 PF4 INT2 7 FIMA4 PF3 INT2 7 FIMA3 PF2 INT2 7 FIMA2 P...

Page 138: ...Rabbit 6000 User s Manual digi com 138 13 1 1 Block Diagram...

Page 139: ...cks All outputs on Parallel Port F are clocked by the peripheral clock unless changed in PFCR where the option of updating the Parallel Port F pins can be synchronized to the output of Timer A1 Timer...

Page 140: ...r PFAHR and then enable it via PFFR Refer to the appropriate peripheral chapter for further use of that pin Once the port is set up data can be read or written by accessing PFDR Read PFDR to learn the...

Page 141: ...01 Parallel Port F bit 3 alternate output 1 I3 10 Parallel Port F bit 3 alternate output 2 TIMER C3 11 Parallel Port F bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port F bit 2 alternate output 0 FI...

Page 142: ...ernate output 3 RCLKE 1 0 00 Parallel Port F bit 4 alternate output 0 FIMA4 01 Parallel Port F bit 4 alternate output 1 I4 10 Parallel Port F bit 4 alternate output 2 PWM0 11 Parallel Port F bit 4 alt...

Page 143: ...e signal as an output See Table 13 1 Parallel Port F Drive Control Register PFDCR Address 0x003E Bit s Value Description 7 0 0 The corresponding port bit as an output is driven high and low 1 The corr...

Page 144: ...ddress 0x04BE PF7CR Address 0x04BF Bit s Value Description 7 5 These bits are reserved and should be written with zeros 4 0 Fast output slew rate 1 Slow output slew rate 3 2 00 4 mA output drive capab...

Page 145: ...or Timer B2 can be used for this function with each nibble of the port having a separate select field to control this timing Each bit can either be programmed as open drain or driven high and low The...

Page 146: ...1 Block Diagram Table 14 2 Parallel Port G Pin Alternate Input Functions Pin Name External Interrupts FIM PG7 INT2 7 FIMB7 PG6 INT2 7 FIMB6 PG5 INT2 7 FIMB5 PG4 INT2 7 FIMB4 PG3 INT2 7 FIMB3 PG2 INT2...

Page 147: ...14 2 2 Clocks All outputs on Parallel Port G are clocked by the peripheral clock unless changed in PGCR where the option of updating the Parallel Port G pins can be synchronized to the output of Time...

Page 148: ...r PGAHR and then enable it via PGFR Refer to the appropriate peripheral chapter for further use of that pin Once the port is set up data can be read or written by accessing PGDR Read PGDR to learn the...

Page 149: ...01 Parallel Port G bit 3 alternate output 1 I3 10 Parallel Port G bit 3 alternate output 2 TIMER C3 11 Parallel Port G bit 3 alternate output 3 SCLKD 5 4 00 Parallel Port G bit 2 alternate output 0 FI...

Page 150: ...e output 0 FIMB6 01 Parallel Port G bit 6 alternate output 1 I6 10 Parallel Port G bit 6 alternate output 2 PWM2 11 Parallel Port G bit 6 alternate output 3 TXE 3 2 00 Parallel Port G bit 5 alternate...

Page 151: ...al clock is the output of Timer A1 10 The lower nibble peripheral clock is the output of Timer B1 11 The lower nibble peripheral clock is the output of Timer B2 Parallel Port G Function Register PGFR...

Page 152: ...ddress 0x04CE PG7CR Address 0x04CF Bit s Value Description 7 5 These bits are reserved and should be written with zeros 4 0 Fast output slew rate 1 Slow output slew rate 3 2 00 4 mA output drive capab...

Page 153: ...Port H acts as the upper byte of the external I O bus when the 16 bit mode is enabled all other Parallel Port H functionality will be disabled automatically when that mode is in effect The drive stren...

Page 154: ...Rabbit 6000 User s Manual digi com 154 15 1 1 Block Diagram...

Page 155: ...00000000 Port H Alternate Low Register PHALR 0x0032 R W 00000000 Port H Alternate High Register PHAHR 0x0033 R W 00000000 Port H Function Register PHFR 0x0035 R W 00000000 Port H Drive Control Regist...

Page 156: ...acts as the upper byte of the data bus D 15 8 for external I O when 16 bit data is enabled All pins are set as inputs on startup The individual bits can be set to be open drain via PHDCR Drive strengt...

Page 157: ...ral chapter for further use of that pin 5 All these settings will be superseded if a 16 bit memory interface is selected since Parallel Port H is used for the upper half of the data bus in that mode O...

Page 158: ...3 alternate output 1 I3 10 Parallel Port H bit 3 alternate output 2 TIMER C3 11 Parallel Port H bit 3 alternate output 3 SCLKD 5 4 00 This value is reserved and must not be used 01 Parallel Port H bi...

Page 159: ...01 Parallel Port H bit 5 alternate output 1 I5 10 Parallel Port H bit 5 alternate output 2 PWM1 11 Parallel Port H bit 5 alternate output 3 RCLKE 1 0 00 This value is reserved and must not be used 01...

Page 160: ...Address 0x04DA PH3CR Address 0x04DB PH4CR Address 0x04DC PH5CR Address 0x04DD PH6CR Address 0x04DE PH7CR Address 0x04DF Bit s Value Description 7 5 These bits are reserved and should be written with...

Page 161: ...ocking of the timers takes place on the negative edge of these pulses When the counter reaches zero the reload register is loaded into the counter on the next input pulse instead of a count being perf...

Page 162: ...n and the corresponding interrupt is enabled an interrupt will occur when priorities allow However a separate interrupt is not guaranteed for each bit with an enabled interrupt If the bit is read in t...

Page 163: ...Rabbit 6000 User s Manual digi com 163 16 1 1 Block Diagram...

Page 164: ...0x00A5 R W xxxxxxxx Timer A Time Constant 8 Register TAT8R 0x00A6 R W xxxxxxxx Timer A Time Constant 3 Register TAT3R 0x00A7 R W xxxxxxxx Timer A Time Constant 9 Register TAT9R 0x00A8 R W xxxxxxxx Ti...

Page 165: ...mer A are clocked by the Timer A Prescaler TAPR In addition Timers A2 A7 can be clocked by the output of Timer A1 by selecting that option in TACSR and Timers A8 A11 can be clocked by the output of ti...

Page 166: ...1 Handling Interrupts The following steps explain how an interrupt is set up and used 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Configure TACSR to select w...

Page 167: ...d 1 The clock input for Timer A is enabled Timer A Prescale Register TAPR Address 0x00A1 Bit s Value Description 7 0 Time constant for the Timer A prescaler This time constant will take effect the nex...

Page 168: ...ked by the output of TAPR 1 Timer A2 clocked by the output of Timer A1 1 0 00 Timer A interrupts are disabled 01 Timer A interrupt use Interrupt Priority 1 10 Timer A interrupt use Interrupt Priority...

Page 169: ...s D G The compare value comes from either the match register or the value internally generated via the step reg ister When using the match register a new match value must be written to the match regis...

Page 170: ...Rabbit 6000 User s Manual digi com 170 17 1 1 Block Diagram...

Page 171: ...imer B Control Register TBCR 0x00B1 R W xx000000 Timer B MSB 1 Register TBM1R 0x00B2 R W xxxxxxxx Timer B LSB 1 Register TBL1R 0x00B3 R W xxxxxxxx Timer B MSB 2 Register TBM2R 0x00B4 R W xxxxxxxx Time...

Page 172: ...by writing a 1 to bit 0 of TBCSR 17 3 1 Handling Interrupts The following steps explain how an interrupt is set up and used 1 Write the vector to the interrupt service routine to the internal interru...

Page 173: ...Timer B is disabled 1 The clock input for Timer B is enabled Timer B Control Register TBCR Address 0x00B1 Bit s Value Description 7 6 These bits are reserved and should be written with zero 5 0 Normal...

Page 174: ...imer B comparator This compare value will be loaded into the actual comparator when the current compare detects a match Timer B Step LSB x Register TBSL1R Address 0x00BA TBSL2R Address 0x00BC Bit s Va...

Page 175: ...s Value Description 7 6 Read The current value of the two MSBs of the Timer B counter is reported 5 0 These bits are always read as zeros Timer B Count LSB Register TBCLR Address 0x00BF Bit s Value D...

Page 176: ...the counter rolls over allowing the control registers to be reloaded at any time during the count cycle Timer C can generate an interrupt when the count limit value is reached A separate Timer C Block...

Page 177: ...Rabbit 6000 User s Manual digi com 177 18 1 1 Block Diagram...

Page 178: ...w Register TCS1LR 0x050C R W xxxxxxxx Timer C Set 1 High Register TCS1HR 0x050D R W xxxxxxxx Timer C Reset 1 Low Register TCR1LR 0x050E R W xxxxxxxx Timer C Reset 1 High Register TCR1HR 0x050F R W xxx...

Page 179: ...ut of Timer A11 as selected in TCCR TA12 may be used as a prescaler for TA11 18 2 3 Other Registers 18 2 4 Interrupts A Timer C interrupt is enabled in TCCR and will occur whenever the count limit val...

Page 180: ...d to by TCBPR 5 Enable the desired output pins for Timer C by writing to the appropriate parallel port function and alternate output registers 6 Enable Timer C by writing a 1 to bit 0 of TCCSR 18 3 1...

Page 181: ...4 These bits are reserved and should be written with zero 3 2 00 Timer C clocked by main Timer C clock i e CLK 2 01 Timer C clocked by the output of Timer A1 10 Timer C clocked by main Timer C clock...

Page 182: ...ress 0x0519 TCS3HR Address 0x051D Bit s Value Description 7 0 Eight MSBs of the match value to set Timer C Output x Timer C Reset x Low Register TCR0LR Address 0x050A TCR1LR Address 0x050E TCR2LR Addr...

Page 183: ...ss the Timer C register pointed to by TCBPR TCBPR is automatically updated to the next Timer C register address in the sequence Timer C Block Pointer Register TCBPR Address 0x00F9 Bit s Value Descript...

Page 184: ...full duplex The transmit and receive buffers have 4 bytes each A serial port interrupt is generated whenever at least one byte is available in the receive buffer whenever a byte is shifted out of the...

Page 185: ...n Table 19 1 or from a dedicated 15 bit divider In either case the resulting bit data rate in the asynchronous mode is 1 8 or 1 16 the data clock rate selectable However the bit data rate in the clock...

Page 186: ...Rabbit 6000 User s Manual digi com 186 19 1 1 Block Diagram...

Page 187: ...er SBER 0x00D5 R W 00000000 Serial Port B Divider Low Register SBDLR 0x00D6 R W xxxxxxxx Serial Port B Divider High Register SBDHR 0x00D7 R W 0xxxxxxx Serial Port C Data Register SCDR 0x00E0 R W xxxxx...

Page 188: ...ve on pins PC3 PD3 or PE3 If the clocked serial mode is enabled the serial clock can be transmitted on PC7 PD7 PD2 or PE7 and can be received on PD2 or PE2 Serial Port D can transmit on parallel port...

Page 189: ...e located in the IIR as follows Serial Port A at offset 0x0C0 Serial Port B at offset 0x0D0 Serial Port C at offset 0x0E0 Serial Port D at offset 0x0F0 Each of them can be set as Priority 1 2 or 3 in...

Page 190: ...coding clock polarity and behavior during break 5 Write the desired divider value to TATxR for the appropriate serial port or else write a divider value to the dedicated 15 bit divider in SxDLR and Sx...

Page 191: ...and clock source if external 5 If your serial port will be the master write the desired divider value to TATxR for the appropriate serial port or else write a divider to the dedicated 15 bit divider...

Page 192: ...ead byte and clear interrupt do something with received byte here ld a 0x4D set bits 6 7 to 01 the other bits should represent the desired SBCR setup Parallel Port C internal clock Interrupt Priority...

Page 193: ...he clocked serial mode automatically causes the receiver to start a byte receive operation eliminating the need for software to issue the start receive command Write Loads the transmit buffer with an...

Page 194: ...eceive buffer was not overrun 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 4 0 The byte in the receive buffer has no parity error or was not checked for parity 1...

Page 195: ...receive buffer was overrun This bit is cleared by reading the receive buffer 4 0 This bit is always zero in clocked serial mode 3 0 The transmit buffer is empty 1 The transmit buffer is not empty The...

Page 196: ...ve operation simultaneously 5 4 00 Parallel Port C is used for input 01 Parallel Port D is used for input 10 Parallel Port E is used for input 11 Disable the receiver input 3 2 00 Asynchronous mode wi...

Page 197: ...checking with space always zero parity 111 Enable parity generation and checking with mark always one parity 4 0 Normal asynchronous data encoding 1 Enable RZI coding 3 16 bit cell IrDA compliant 3 0...

Page 198: ...rnal clock 11 Inverted clocked serial clock polarity inactive high Internal clock only 3 0 Normal bit order LSB first for transmit and receive 1 Reverse bit order MSB first for transmit and receive 2...

Page 199: ...0F7 Bit s Value Description 7 0 Disable the serial port divider and use the output of Timer A to clock the serial port 1 Enable the serial port divider and use its output to clock the serial port The...

Page 200: ...mit buffer is empty or busy sending a byte and the state of the ninth data bit whether it is an address bit or a stop bit Serial Ports E and F support the HDLC mode with either an internal or an exter...

Page 201: ...y 16 When using an external clock a 1 same speed as the data rate clock is supported In this case the maximum data rate is 1 6 of the peripheral clock rate The receive clock is generated from the tran...

Page 202: ...er SEER 0x00CD R W 00000000 Serial Port E Divider Low Register SEDLR 0x00CE R W xxxxxxxx Serial Port E Divider High Register SEDHR 0x00CF R W 0xxxxxxx Serial Port F Data Register SFDR 0x00D8 R W xxxxx...

Page 203: ...n PC1 PD1 or PE1 The transmit and receive clocks can also be transmitted on PH5 or PH1 if internal clock generation is enabled 20 2 2 Clocks The data clocks for Serial Ports E F are based on the perip...

Page 204: ...e occurrences correspond to bits 7 3 and 2 of the Serial Port Status Registers In the HDLC mode interrupts are also generated by the reception of an end of frame with abort valid CRC or CRC error at t...

Page 205: ...serial port or else write a divider to the dedicated 15 bit divider in SxDLR and SxDHR If the dedicated divider is to be used write a 1 to the most significant bit of SxDHR to enable it In either case...

Page 206: ...into SEAR or SELR instead ioi ld SEDR a load next byte into buffer and clear interrupt done pop af ipres ret 20 3 3 More on Clock Synchronization and Data Encoding The transmitter is not capable of se...

Page 207: ...ng of zeros for example but the other data encodings do NRZI guarantees transitions because of the inserted zeros and the biphase encodings all have at least one transition per bit cell The DPLL count...

Page 208: ...onto the required transitions Since the DPLL can adjust by one count every bit cell the maximum difference between the sending data rate and the DPLL output clock rate is 1 16 6 With biphase data enc...

Page 209: ...6 counter The regions that adjust the count by two allow the DPLL to synchronize faster to the data stream when starting up With biphase level encoding there is a guaranteed clock transition at the ce...

Page 210: ...SEDR Address 0x00C8 SFDR Address 0x00D8 Bit s Value Description 7 0 Read Returns the contents of the receive buffer Write Loads the transmit buffer with a data byte for transmission Serial Port x Addr...

Page 211: ...not overrun 1 The receive buffer was overrun This bit is cleared by reading the receive buffer 4 0 The byte in the receive buffer has no parity error or was not checked for parity 1 The byte in the re...

Page 212: ...t buffer is not empty The serial port will request an interrupt when the transmitter takes a byte from the transmit buffer unless the byte is marked as the last in the frame Transmit interrupts are cl...

Page 213: ...iver data input Clocks from Parallel Port E 3 2 00 Asynchronous mode with 8 bits per character 01 Asynchronous mode with 7 bits per character In this mode the most significant bit of a byte is ignored...

Page 214: ...always zero parity 111 Enable parity generation and checking with mark always one parity 4 0 Normal asynchronous data encoding 1 Enable RZI coding 3 16 bit cell IrDA compliant 3 0 Normal break operati...

Page 215: ...it flag on underrun 1 Transmit abort on underrun 1 0 Separate HDLC external receive and transmit clocks 1 Combined HDLC external and transmit clock from transmit clock pin 0 This bit is ignored in HDL...

Page 216: ...en written by the source side of the interface and are marked empty when read by the destination side of the interface The hardware interface to the external master consists of an 8 bit bidirectional...

Page 217: ...nemonic I O Address R W Reset Slave Port Data 0 Register SPD0R 0x0020 R W xxxxxxxx Slave Port Data 1 Register SPD1R 0x0021 R W xxxxxxxx Slave Port Data 2 Register SPD2R 0x0022 R W xxxxxxxx Slave Port...

Page 218: ...n the slave device whenever the mas ter writes to SPD0R The SLVATTN pin is asserted whenever the slave device writes to SPD0R Either of these conditions is cleared when either the master or slave read...

Page 219: ...abbit 6000 User s Manual digi com 219 21 3 Operation Figure 21 1 shows a typical slave port connection between a Rabbit processor as the master and two slaves Figure 21 1 Master Slave Port Connections...

Page 220: ...SLVATTN it reads the slave port data registers 21 3 1 Master Setup 1 Enable the I O strobes on PD6 and PD7 as chip selects by writing to the appropriate Parallel Port D pin and External I O registers...

Page 221: ...s writing multiple bytes SPD0R should be written last which enables the SLVATTN line 2 The master receives an external interrupt from the SLVATTN line and reads the data out of the slave port data reg...

Page 222: ...configuration is useful when fewer signals are desired or the master device has no external interrupts available If polling is to be used it is important to note that not all bits in the status regis...

Page 223: ...Setup Time 5 Th SCS SCS Hold Time 0 Tsu SA SA Setup Time 5 Th SA SA Hold Time 0 Tw SRD SRD Low Pulse Width 40 Ten SRD SRD to SD Enable Time 0 Ta SRD SRD to SD Access Time 30 Tdis SRD SRD to SD Disabl...

Page 224: ...Rabbit 6000 User s Manual digi com 224 Figure 21 2 shows the sequence of events when the master reads writes the slave port registers Figure 21 2 Slave Port R W Timing Diagram...

Page 225: ...s Value Description 7 0 Slave wrote to SPSR 1 Master wrote to Data Register 0 6 0 Slave port read byte 2 is empty 1 Slave port read byte 2 is full 5 0 Slave port read byte 1 is empty 1 Slave port rea...

Page 226: ...e the slave port with SCS from Parallel Port E bit 7 011 Enable the external I O bus Parallel Port A is used for the data bus and Parallel Port B 7 2 is used for the address bus 100 This bit combinati...

Page 227: ...nt can accept a clock from an external I O pin or divide the peripheral clock by a value between 2 and 256 The Rabbit 6000 also has a dedicated 1 megasamples s 12 bit A D converter with an 8 way multi...

Page 228: ...0 5 V from common mode Operating Current Active Standby Power down 40 mA 1 2 V 3 5 mA 1 2 V 10 A 1 2 V Nonlinearity Differential DNL Integral INL 0 7 LSB typ 1 2 LSB typ 1 Wi Fi fast D A converter Re...

Page 229: ...rate Clock 1 megasample sec 13MHz Input Range Single ended 0 1 x VCC33A to 0 9 x VCC33A Operating Current Active Standby 5 mA 3 3 V 10 A 3 3 V Nonlinearity Differential DNL Integral INL 0 8 LSB typ 2...

Page 230: ...Rabbit 6000 User s Manual digi com 230 22 2 Block Diagram...

Page 231: ...po nent 0 1 or 2 respectively 22 3 2 Clocks Each of the analog components can be clocked by the peripheral clock divided by 2 4 8 16 32 64 128 or 256 or by a clock input on PD4 PD5 or PD6 depending on...

Page 232: ...a to the A1IxR and A1QxR registers Writing the least significant bit registers first will hold the conversion output until the most significant bit register is written 3 For faster update an 8 bit val...

Page 233: ...be sure to allow enough filtering for each block as shown a range of ferrite beads may be used we obtained good results with ferrite beads rated at 120 at 100 MHz Also note that a common ground plane...

Page 234: ...Rabbit 6000 User s Manual digi com 234 Figure 22 3 Sample Slow A D Converter Circuit...

Page 235: ...Reading this register locks the value in the corresponding MSB register to guarantee that the full 10 bits are valid Write Writes to these bits are ignored 5 0 These bits are ignored and will always...

Page 236: ...uld be written with zeros 1 0 00 Fast A D converter powered down 01 Fast A D converter in sleep mode 10 This bit combination is reserved and should not be used 11 Fast A D converter active Analog Comp...

Page 237: ...lue Description 7 0 Use peripheral clock as fast D A converter clock source 1 Use Parallel Port PD5 as fast D A converter clock source 6 4 000 Clock divided by 2 001 Clock divided by 4 010 Clock divid...

Page 238: ...register locks the value in the corresponding MSB register to guarantee that the full 11 bits are valid Write Writes to this register are ignored 4 0 These bits are ignored and will always return zero...

Page 239: ...6 4 000 Clock divided by 2 001 Clock divided by 4 010 Clock divided by 8 011 Clock divided by 16 100 Clock divided by 32 101 Clock divided by 64 110 Clock divided by 128 111 Clock divided by 256 3 0 C...

Page 240: ...single channel A D converter a 10 bit two channel differential input A D converter and a 10 bit two channel differential output D A converter for 802 11 Wi Fi operation The Wi Fi analog features are a...

Page 241: ...ame Mnemonic I O Address R W Reset ADC LSB Register ADCLR 0x0540 R 00000000 ADC MSB Register ADCMR 0x0541 R 00000000 ADC Command Status Register ADCCSR 0x0543 R W 00000000 ADC Control Register ADCCR 0...

Page 242: ...VIN or they can simply be connected directly External voltage references can be used with the multiplexed A D converter if enabled they should be supplied on REF and REF The PD4 pin can be used as a...

Page 243: ...plexed A D converter in the continuous read mode 1 Select the clock source and enable the multiplexed A D converter by writing to ADCCR 2 Enable the continuous read mode by setting bit 7 of ADCCSR 3 T...

Page 244: ...sample circuit is shown below for the analog components For more information about possible post multiplexer pre A D converter filtering circuits please contact your sales representative at Digi Inter...

Page 245: ...guarantee that the full 12 bits are valid The channel is selected in ADCCSR 3 2 Read These bits always return zeros when read 1 0 No conversion is running 1 A conversion is in progress 0 0 Conversion...

Page 246: ...nversion 101 Select A D Converter Channel 5 for conversion 110 Select A D Converter Channel 6 for conversion 111 Select A D Converter Channel 7 for conversion 3 2 00 Floating reference 01 Internal ref...

Page 247: ...vided by 8 011 Clock divided by 16 100 Clock divided by 32 101 Clock divided by 64 110 Clock divided by 128 111 Clock divided by 256 3 This bit is reserved and should be written with zero 2 0 Multiple...

Page 248: ...to guarantee that the full 12 bits are valid 3 2 Read These bits always return zeros when read 1 0 No conversion is running 1 A conversion for this channel is in progress 0 0 Conversion is not comple...

Page 249: ...e is matched A mask is available for the byte match to allow termination only on particular bit settings in the data instead of an exact byte match There are two DMA transfer methods available in the...

Page 250: ...external request is ANDed with the automatically connected internal request To facilitate periodic DMA transfers there is also an internal timed request This request is generated from a programmable 1...

Page 251: ...r the byte pointed to by the initial address is reserved for status information when transferring data from an internal serial or network device This automatic status transfer means that the processor...

Page 252: ...peripheral from to a memory device The DMA automatically recognizes internal I O addresses that support fly by transfers Operating the DMA with the USB peripheral is complicated by the fact that the...

Page 253: ...RCR 0x0115 R W 00000000 DMA Timed Request Divider Low Register DTRDLR 0x0116 R W xxxxxxxx DMA Timed Request Divider High Register DTRDHR 0x0117 R W xxxxxxxx DMA Cycle Steal Timing Control Register DCS...

Page 254: ...7 DMA Channels 8 15 y 0 15 v y 8 z y 8 DMA y Buffer Complete Register 0x01y3 0x09z3 DMA y Termination Byte Register 0x01y8 0x09z8 DMA y Termination Mask Register 0x01y9 0x09z9 DMA y Buffer Unused 7 0...

Page 255: ...eral clock and will provide a DMA request each time it counts down to zero 24 2 3 Other Registers 24 2 4 Interrupts Each DMA channel has its own dedicated interrupt that can occur at the end of any DM...

Page 256: ...DxSA1R DxSA2R dma_addr_t destAddress DxDA0R DxDA1R DxDA2R dma_addr_t linkAddress DxLA0R DxLA1R DxLA2R DMABufDesc It is possible to abort a DMA transfer by writing the appropriate bit to the halt regi...

Page 257: ...ady Several automatic options auto increment auto decrement spe cial peripheral enables can be overridden by settings in DySCR 8 The initial address registers DyIAnR should be loaded with the physical...

Page 258: ...imit on interrupt latency arising from a DMA transfer Second the minimum number of clocks before the DMA can be active again can be set from 12 to 512 clocks guaranteeing processing time for the appli...

Page 259: ...e restarts at the top of the table One option is to rotate priority after every byte analogous to the fixed priority setting The priority list is updated after each byte transferred and if a higher pr...

Page 260: ...rs are certainly possible by different use of the available linking methods 24 3 5 1 Single Buffer In the simplest mode a single descriptor is set to halt and interrupt on completion 24 3 5 2 Buffer A...

Page 261: ...m 261 24 3 5 3 Linked List A linked list is similar to a buffer array except that 16 byte descriptors are used and the descriptors are not necessarily adjacent in memory The advantage of this mode is...

Page 262: ...ing pong buffer where there are only two buffers is the simplest version of a circular queue The application can operate on one buffer while the other buffer is being loaded 24 3 5 5 Linked Array The...

Page 263: ...nding by the DMA When the DMA destination is the network data register NBDR the final byte of the transfer will be written to the last data register NBLDR as required to complete an Ethernet packet an...

Page 264: ...l 15 8 using the contents of the DMA channel registers This command should only be issued after all the DMA channel registers source destination length and link if applicable have been loaded 7 0 0 Th...

Page 265: ...ptor rd only 1 The corresponding DMA channel 15 8 is enabled and active These bits are set by the Start command and remain set until the completion of the last buffer or receipt of a Halt command DMA...

Page 266: ...y rewound to the initial address Write Writing to this register loads the counter This feature is intended only for testing because the DMA automatically resets the counter to all ones when fetching f...

Page 267: ...number after the current channel request is serviced 5 3 000 Maximum one byte per burst 001 Maximum two bytes per burst 010 Maximum three bytes per burst 011 Maximum four bytes per burst 100 Maximum e...

Page 268: ...t 0 supplied to DMA Channel 0 0001 External DMA Request 0 supplied to DMA Channel 1 0010 External DMA Request 0 supplied to DMA Channel 2 0011 External DMA Request 0 supplied to DMA Channel 3 0100 Ext...

Page 269: ...t 1 supplied to DMA Channel 0 0001 External DMA Request 1 supplied to DMA Channel 1 0010 External DMA Request 1 supplied to DMA Channel 2 0011 External DMA Request 1 supplied to DMA Channel 3 0100 Ext...

Page 270: ...d DMA request supplied to DMA Channel 2 0011 Timed DMA request supplied to DMA Channel 3 0100 Timed DMA request supplied to DMA Channel 4 0101 Timed DMA request supplied to DMA Channel 5 0110 Timed DM...

Page 271: ...iority Priority rotates highest channel number to lowest channel number after every transfer 11 Rotating cycle steal DMA channel priority Priority rotates highest channel number to lowest channel numb...

Page 272: ...s 0x0138 D4TBR Address 0x0148 D5TBR Address 0x0158 D6TBR Address 0x0168 D7TBR Address 0x0178 D8TBR Address 0x0908 D9TBR Address 0x0918 D10TBR Address 0x0928 D11TBR Address 0x0938 D12TBR Address 0x0948...

Page 273: ...x0929 D11TMR Address 0x0939 D12TMR Address 0x0949 D13TMR Address 0x0959 D14TMR Address 0x0969 D15TMR Address 0x0979 Bit s Value Description 7 0 Mask for termination byte A one in a bit position enable...

Page 274: ...remaining length to this register at the completion of the transfer Normally the buffer remaining length is zero but if the transfer terminates early under source control or because of a termination...

Page 275: ...0x096C D15IA0R Address 0x097C Bit s Value Description 7 0 Bits 7 0 of the initial address are stored in this register DMA y Initial Addr 15 8 Register D0IA1R Address 0x010D D1IA1R Address 0x011D D2IA...

Page 276: ...D4IA2R Address 0x014E D5IA2R Address 0x015E D6IA2R Address 0x016E D7IA2R Address 0x017E D8IA2R Address 0x090E D9IA2R Address 0x091E D10IA2R Address 0x092E D11IA2R Address 0x093E D12IA2R Address 0x094...

Page 277: ...tion 10 Enable DMA for automatic Network Port D USB receive channel operation 11 Enable DMA for automatic Network Port D USB transmit channel operation 5 This bit is reserved and must always be read a...

Page 278: ...eld as a pointer to the next buffer descriptor This buffer descriptor is 16 bytes long 5 0 No special treatment for last byte 1 Internal Source status byte written to initial buffer descriptor before...

Page 279: ...09E2 D15L0R Address 0x09F2 Bit s Value Description 7 0 Bits 7 0 of the buffer length value are stored in this register DMA y Length 15 8 Register D0L1R Address 0x0183 D1L1R Address 0x0193 D2L1R Addres...

Page 280: ...s 0x09E4 D15SA0R Address 0x09F4 Bit s Value Description 7 0 Bits 7 0 of the source address are stored in this register DMA y Source Addr 15 8 Register D0SA1R Address 0x0185 D1SA1R Address 0x0195 D2SA1...

Page 281: ...09E6 D15SA2R Address 0x09F6 Bit s Value Description 7 0 Bits 23 16 of the source address are stored in this register DMA y Destination Addr 7 0 Register D0DA0R Address 0x0188 D1DA0R Address 0x0198 D2D...

Page 282: ...E9 D15DA1R Address 0x09F9 Bit s Value Description 7 0 Bits 15 8 of the destination address are stored in this register DMA y Destination Addr 23 16 Register D0DA2R Address 0x018A D1DA2R Address 0x019A...

Page 283: ...ess 0x09EC D15LA0R Address 0x09FC Bit s Value Description 7 0 Bits 7 0 of the link address are stored in this register DMA y Link Addr 15 8 Register D0LA1R Address 0x018D D1LA1R Address 0x019D D2LA1R...

Page 284: ...D4LA2R Address 0x01CE D5LA2R Address 0x01DE D6LA2R Address 0x01EE D7LA2R Address 0x01FE D8LA2R Address 0x098E D9LA2R Address 0x099E D10LA2R Address 0x09AE D11LA2R Address 0x09BE D12LA2R Address 0x09C...

Page 285: ...errupts because the DMA has no way of knowing when or if the frame has successfully been sent Both the receive and transmit FIFOs are capable of DMA fly by operation The network port requires an accur...

Page 286: ...etwork activity If the network receiver enters the NLP Link Test Fail state because of missing link test pulses this state machine requires seven successive properly timed link test pulses or an equal...

Page 287: ...Rabbit 6000 User s Manual digi com 287 25 1 1 Block Diagram...

Page 288: ...B Phys Addr 31 24 Register NBPA3R 0x0213 W xxxxxxxx Network Port B Phys Addr 39 32 Register NBPA4R 0x0214 W xxxxxxxx Network Port B Phys Addr 47 40 Register NBPA5R 0x0215 W xxxxxxxx Network Port B Mul...

Page 289: ...W 00000000 Network Port B MII Register Address Register NBMRAR 0x0254 R W 00000000 Network Port B MII PHY Address Register NBMPAR 0x0255 R W 00000000 Network Port B MII Write LSB Register NBMWLR 0x025...

Page 290: ...ied directly to XTL_25MO For optimal power reduction the XTL_25MO pin should be attached to the ETH_2 5V signal if the external 25 MHz clock interface is not used 25 2 3 Other Registers Table 25 1 Net...

Page 291: ...wn below Note that any status block marked with RxOV receive overflow is invalid as the FIFO could not hold the entire frame Only the marked frame is invalid so any previous frames read from the FIFO...

Page 292: ...ion 2 Enable the DMA transfer by auto loading the buffer 3 The packet transmission will proceed automatically If any interrupts were enabled for any transmitted packet events they will occur upon comp...

Page 293: ...read the interrupt status push af save status byte for later bit 4 a did transmit error occur jp nz handle_tx_err bit 4 a did transmit pause occur jp nz handle_pause_err done pop af ipres ret handle_t...

Page 294: ...program control A one in the corresponding table entry constitutes a multicast address match as far as the network port is concerned A table of one set of unique multicast addresses corresponding to e...

Page 295: ...of a frame to enable the subsequent transmission of the CRC The DMA automatically writes the last byte of the frame to this address Network Port B Transmit Status Register NBTSR Address 0x0202 Bit s...

Page 296: ...eared by a read of this register The individual interrupt enables are not affected 5 0 No transmit okay interrupt Read only 1 Transmit okay interrupt 4 0 No transmit error interrupt Read only 1 Transm...

Page 297: ...ex backpressure 4 0 No operation 1 Transmit FIFO purge command 3 1 These bits are ignored and should always be written as zeros 0 0 No operation 1 Receive FIFO purge command Network Port B Transmit Pa...

Page 298: ...is complete 10 DMA request when FIFO is half full or frame reception is complete 11 DMA request when FIFO is one fourth full or frame reception is complete 5 0 Normal receiver operation 1 Place recei...

Page 299: ...s x Register NBPA0R Address 0x0210 NBPA1R Address 0x0211 NBPA2R Address 0x0212 NBPA3R Address 0x0213 NBPA4R Address 0x0214 NBPA5R Address 0x0215 Bit s Value Description 7 0 Write Byte of physical addr...

Page 300: ...control frames 1 0 Pass normal receive frames only 1 Pass all receive frames normal or control 0 0 Disable receiver 1 Enable receiver Network Port B Configuration 1 Register NBCF1R Address 0x0241 Bit...

Page 301: ...s transmit and receive 1 0 Disable frame length checking 1 Enable frame length checking transmit and receive 0 0 Enable half duplex 1 Enable full duplex Network Port B Configuration 3 Register NBCF3R...

Page 302: ...C as specified by 802 3 Network Port B Gap 1 Register NBG1R Address 0x0247 Bit s Value Description 7 This bit is ignored and will always return zero when read 6 0 Non back to back interpacket gap Reco...

Page 303: ...ster NBMCFR Address 0x0250 Bit s Value Description 7 5 These bits are ignored and will always return zeros when read 4 2 000 MII Management Clock is system clock divided by 4 001 This value is reserve...

Page 304: ...0 No operation 1 Enable scan MII module performs continuous read cycles 0 0 No operation 1 Perform one MII read cycle Network Port B MII Register Address Register NBMRAR Address 0x0254 Bit s Value De...

Page 305: ...read data Network Port B MII Read MSB Register NBMRMR Address 0x0259 Bit s Value Description 7 0 MSB of MII read data Network Port B MII Status Register NBMSR Address 0x025A Bit s Value Description 7...

Page 306: ...Port B Station Address x Register NBSA0R Address 0x0260 NBSA1R Address 0x0261 NBSA2R Address 0x0262 NBSA3R Address 0x0263 NBSA4R Address 0x0264 NBSA5R Address 0x0265 Bit s Value Description 7 0 Byte o...

Page 307: ...internal 10 100 PHY Reads always return zero Write only 1 Reset the internal 10 100 PHY hardware This command must not be issued until at least 600 ms after the internal PHY has been enabled in ENPR T...

Page 308: ...B port 4 0 Internal 10 100 PHY This bit is ignored unless bit 6 of this register is also set at which point the internal PHY is powered up 1 External 10 100 PHY 3 2 00 Network Port D interrupts are di...

Page 309: ...handled automatically by the baseband These operations include time management and transmission interval spacing The MAC also performs the CRC check of all received frames and handles the virtual carr...

Page 310: ...Rabbit 6000 User s Manual digi com 310 26 1 1 Block Diagram...

Page 311: ...D R 00000000 Network Port C RSSI 2 Register NCRSSI2R 0x0A0E R 00000000 Network Port C RSSI 3 Register NCRSSI3R 0x0A0F R 00000000 Network Port C Interrupt Mask Register NCIMR 0x0A10 R W 00000000 Networ...

Page 312: ...k Port C Backoff 1 Register NCBO1R 0x0A57 R W xxxxxxxx Network Port C DTIM Period Register NCDTIMPR 0x0A58 R W xxxxxxxx Network Port C CFP Period Register NCCFPPR 0x0A59 R W xxxxxxxx Network Port C Li...

Page 313: ...differential voltage input VRXI Input Output ITXQ Output Q channel differential current output ITXQ Output ITXI Output I channel differential current output ITXI Output Clock XTL_20MI 20MHz crystal in...

Page 314: ...period of the main processor clock round up to the next integer and subtract two This is the required number of Wait states and guarantees that the Wi Fi cycle time of 65nS is always met Note that if...

Page 315: ...oes not affect overall Wi Fi throughput 26 3 1 Other Registers CPU DMA frequency DMA Waits CPU Waits unrestricted only byte access 50 0 MHz 2 2 0 61 5 MHz 3 3 0 76 9 MHz 4 4 4 92 3 MHz 5 5 4 107 6 MHz...

Page 316: ...a complete packet is received The events that generate an interrupt can be selected in NCISR The wireless network port interrupt vector is located in the IIR at offset 0x100 It can be set as Priority...

Page 317: ...Special Control Registers The network port requires an accurate 48 MHz clock to generate the proper USB serial rate An external crystal can be used to drive the internal oscillator or an external cloc...

Page 318: ...MHz clock can be applied directly to XTL_48MO The USB peripheral has a fixed 250ns access time so wait states are usually necessary when accessing it from the Rabbit 6000 The required number of wait...

Page 319: ...t offset 0x110 It can be set as Priority 1 2 or 3 by writing to ENPR Details about what events cause interrupts are available in the OHCI specification Register Function PEDDR PEFR PEALR Selection of...

Page 320: ...e for all four bytes Those values will remain until the next read of the lowest byte so to avoid stale data all four bytes should be read whenever a 32 bit register is accessed 27 3 2 Setup The follow...

Page 321: ...k pulldown resistor on D 0 0 Disable the USB overcurrent detection input on PE3 1 Enable the USB overcurrent detection input on PE3 Network Port D Wait Register NDWR Address 0x0433 Bit s Value Descri...

Page 322: ...s driven by Timer A12 and the Timer A prescaler If the counter rolls over to zero a register bit is set and an interrupt can be generated Two events are recognized a start condition and a stop conditi...

Page 323: ...Rabbit 6000 User s Manual digi com 323 28 1 1 Block Diagram...

Page 324: ...rigger 1 Register ICT1R 0x0058 R W 00000000 Input Capture Source 1 Register ICS1R 0x0059 R W xxxxxxxx Input Capture LSB 1 Register ICL1R 0x005A R xxxxxxxx Input Capture MSB 1 Register ICM1R 0x005B R x...

Page 325: ...egisters 28 2 4 Interrupts Each input capture channel can generate an interrupt whenever a start stop condition occurs or when the counter rolls over to zero The interrupt request is cleared when ICCS...

Page 326: ...ts that will generate an interrupt 3 Configure the Input Capture Control Register ICCR to select the interrupt priority note that inter rupts will be enabled once this value is set this step should be...

Page 327: ...nd or stop condition 3 In the interrupt handler read out the counter as an event timestamp Measure Time Interval from a Software Start to an External Event The following steps explain how to measure t...

Page 328: ...Input Capture 1 counter has not rolled over to all zeros Read 1 The Input Capture 1 counter has rolled over to all zeros 7 2 Read These status bits but not the interrupt enable bits are cleared by th...

Page 329: ...ration for Input Capture 2 6 0 Input Capture operation for Input Capture 1 1 Input Count operation for Input Capture 1 5 2 These bits are reserved and should be written with zero 1 0 00 Input Capture...

Page 330: ...R return the programmed match value 01 Latch the count on the Stop condition only 10 Latch the count on the Start condition only 11 Latch the count on either the Start or Stop condition 3 2 00 Ignore...

Page 331: ...ondition input 10 Parallel Port E used for Stop condition input 11 This bit combination is reserved and should not be used 1 0 00 Use port bit 1 for Stop condition input 01 Use port bit 3 for Stop con...

Page 332: ...ress 0x005F Bit s Value Description 7 0 Read The most significant eight bits of the latched Input capture count are returned In Counter operation if no latching condition is specified the value writte...

Page 333: ...can occur each time the count overflows or underflows The Quadrature Decoder con tains digital filters on the inputs to prevent false counts The external signals are synchronized with an internal cloc...

Page 334: ...ansitions on the I and Q inputs are sampled in different clock cycles Input capture may be used to measure the pulse width on the I inputs because they come from the odd numbered port bits The operati...

Page 335: ...code Ctrl Status Register QDCSR 0x0090 R W xxxxxxxx Quad Decode Control Register QDCR 0x0091 R W 00000000 Quad Decode Count 1 Register QDC1R 0x0094 R xxxxxxxx Quad Decode Count 1 High Register QDC1HR...

Page 336: ...can be used as a predivider for Timer A10 Both the I and Q inputs go through a digital filter that rejects pulses shorter than two clock periods wide 29 2 3 Other Registers 29 2 4 Interrupts Each Quad...

Page 337: ...interrupt priority note that interrupts will be enabled once this value is set The following actions occur within the interrupt service routine Determine exactly why the interrupt occurred by reading...

Page 338: ...of this register 5 This bit always reads as zero 4 0 No effect on the Quadrature Decoder 2 Write only 1 Reset Quadrature Decoder 2 to all zeros without causing an interrupt 3 0 Quadrature Decoder 1 d...

Page 339: ...ause Quadrature Decoder 1 to increment or decrement 01 Quadrature Decoder 1 inputs from Parallel Port D bits 1 and 0 10 Quadrature Decoder 1 inputs from Parallel Port E bits 1 and 0 11 Quadrature Deco...

Page 340: ...e further prescaled by cascading it off of Timer A12 Each PWM output high time can optionally be spread throughout the cycle to reduce ripple on the exter nally filtered PWM output The PWM outputs can...

Page 341: ...is the equivalent to dividing the contents of the pulse width register by four and using this value in each quadrant To get the exact high time the Pulse Width Modulator uses the two LSBs of the pulse...

Page 342: ...be accessed via the access register Each read or write of the access register automatically increments the pointer register through the sequence shown below Note that only the lower three bits of the...

Page 343: ...0x0089 R W xxxxxxxx PWM LSB 1 Register PWL1R 0x008A R W xxxxx00x PWM MSB 1 Register PWM1R 0x008B R W xxxxxxxx PWM LSB 2 Register PWL2R 0x008C R W xxxxx00x PWM MSB 2 Register PWM2R 0x008D R W xxxxxxxx...

Page 344: ...over every second rollover every fourth rollover or every eighth rollover This option is selected in PWL1R The interrupt request is cleared by a write to any PWM register The PWM interrupt vector is i...

Page 345: ...The following steps explain how an interrupt is set up and used 1 Write the vector to the interrupt service routine to the internal interrupt table 2 Configure PWL0R to select the PWM interrupt prior...

Page 346: ...th Modulator interrupts use Interrupt Priority 3 0 0 PWM output High for single block 1 Spread PWM output throughout the cycle PWM LSB 1 Register PWL1R Address 0x008A Bit s Value Description 7 6 Least...

Page 347: ...ad PWM output throughout the cycle PWM MSB x Register PWM0R Address 0x0089 PWM1R Address 0x008B PWM2R Address 0x008D PWM3R Address 0x008F Bit s Value Description 7 0 Most significant eight bits for th...

Page 348: ...sistor can be enabled for the pins 31 1 1 External I O Bus The Rabbit 6000 can enable a separate external I O bus for external devices to keep bus loading on the memory bus at an acceptable level This...

Page 349: ...interface The I O strobes can be used for devices on the memory bus or the external I O bus It is also possible to shorten the read strobe by one clock cycle and the write strobe by one half a clock...

Page 350: ...llel Port E pins for any combination of the I O banks The external device holds this signal active high or low when it is busy and cannot accept a transaction The Rabbit 6000 will then hold midway thr...

Page 351: ...Rabbit 6000 User s Manual digi com 351 31 1 4 Block Diagram...

Page 352: ...egister IB3ER 0x0457 R W 00000000 I O Bank 4 Control Register IB4CR 0x0084 or 0x0458 W R W 00000000 I O Bank 4 Extended Register IB4ER 0x0459 R W 00000000 I O Bank 5 Control Register IB5CR 0x0085 or 0...

Page 353: ...PE0 bank one on PC1 PD1 or PE1 etc The settings for each strobe will be reflected on IOWR IORD and BUFEN as well whenever that bank is accessed The I O handshake can be input on any one of the Parall...

Page 354: ...er 31 3 2 I O Strobes The following steps must be taken before using an I O strobe 1 Set the strobe type and timing for a particular device by writing to the appropriate IBxCR and IBxER registers for...

Page 355: ...101 Use Parallel Port E bit 5 for I O handshake 110 Use Parallel Port E bit 6 for I O handshake 111 Use Parallel Port E bit 7 for I O handshake I O Handshake Select Register IHSR Address 0x0029 Bit s...

Page 356: ...meout has occurred since the last read of this register This bit is cleared by a read of this register 6 This bit is reserved and should be written with zero 5 0 Time constant for the I O handshake ti...

Page 357: ...accesses in this bank 5 4 00 The I signal is an I O chip select 01 The I signal is an I O read strobe 10 The I signal is an I O write strobe 11 The I signal is an I O data read or write strobe 3 0 Wr...

Page 358: ...e upper byte 3 This bit is reserved and should be written with zero 2 0 000 I O transactions run at CPU clock speed Note that I O transactions are always run at the CPU clock speed when running the CP...

Page 359: ...ignored and should be written with zero 4 2 000 Disable the slave port Parallel Port A is a byte wide input port 001 Disable the slave port Parallel Port A is a byte wide output port 010 Enable the sl...

Page 360: ...the match occurred However because of the time required to perform a 24 bit address match in the processor a code execution breakpoint that is set on a single byte 2 clock instruction will not be ena...

Page 361: ...Rabbit 6000 User s Manual digi com 361 32 1 1 Block Diagram...

Page 362: ...rol Register B3CR 0x033B R W 00000000 Breakpoint 4 Control Register B4CR 0x034B R W 00000000 Breakpoint 5 Control Register B5CR 0x035B R W 00000000 Breakpoint 6 Control Register B6CR 0x036B R W 000000...

Page 363: ...int interrupt will always be handled first 32 3 Operation The following steps must be taken to enable breakpoints 1 Write the vector to the interrupt service routine to the external interrupt table 2...

Page 364: ...ioi ld a BDCR determine which interrupts are pending and clear the interrupt request handle all breakpoints here reenable any breakpoints by writing to BDCR pop af ipres you should exit the handler wi...

Page 365: ...ess 0x033B B4CR Address 0x034B B5CR Address 0x036B B6CR Address 0x037B Bit s Value Description 7 6 00 No Breakpoint x on execute address match 01 Breakpoint x on User Mode execute address match 10 Bre...

Page 366: ...0 Breakpoint x Address 1 Register B0A1R Address 0x030D B1A1R Address 0x031D B2A1R Address 0x032D B3A1R Address 0x033D B4A1R Address 0x034D B5A1R Address 0x036D B6A1R Address 0x037D Bit s Value Descrip...

Page 367: ...1R Address 0x0309 B1M1R Address 0x0319 B2M1R Address 0x0329 B3M1R Address 0x0339 B4M1R Address 0x0349 B5M1R Address 0x0369 B6M1R Address 0x0379 Bit s Value Description 7 0 Breakpoint x Mask 15 8 A one...

Page 368: ...he FIM Communication between the Rabbit 6000 and the Flexible Interface Modules is realized in several ways 16 byte TX FIFO from the Rabbit to the Flexible Interface Module 16 byte RX FIFO from the Fl...

Page 369: ...Rabbit 6000 User s Manual digi com 369 33 2 Block Diagram...

Page 370: ...0 15 FACBxR 0x6007 x R W 00000000 FIMA Port Expansion Bytes 0 15 FAPEBxR 0x6017 x R 00000000 FIMA Code LSB Register FACLR 0x6800 0x6BFF R W xxxxxxxx FIMA Code MSB Register FACMR 0x6C00 0x6FFF R W xxx...

Page 371: ...override mode are not covered in this document 33 3 2 Clocks The Flexible Interface Modules have two clocking options selectable in the Master System Configuration Register One option is to use the ma...

Page 372: ...o bit 7 of FxICR to enable the Flexible Interface Module If interrupts from the module are to be used set the priority level in bits 0 1 of FxICR as well 6 The Flexible Interface Module is now running...

Page 373: ...d a 0x80 ioi ld FAIIR a set acknowledge bit for FIMA ld b 255 timeout counter for FIM ack waitForFIM dec b decrement timeout counter jp z timeout exit to timeout handling routine ioi ld a FAIOR bit 7...

Page 374: ...R Address 0x6001 Bit s Value Description 7 This bit is reserved and always returns zero 6 0 read Returns the contents of the receive status FIFO buffer FIMA FIFO Status Register FAFSR Address 0x6002 B...

Page 375: ...e interrupt request This bit must remain set until the interrupt code from the Flexible Interface Module processor has been cleared 6 0 write Interrupt value to the Flexible Interface Module processor...

Page 376: ...resses 0x10 0x17 and bytes 8 15 are mapped to data memory addresses 0x90 0x97 These registers are read write for the Rabbit but read only for the FIM FIMA Port Expansion x Register FAPE0R Address 0x60...

Page 377: ...Bit s Value Description 7 6 These bits are unused 5 0 FIMA code bits 13 8 FIMB Data FIFO Register FBDFR Address 0x7000 Bit s Value Description 7 0 write Loads the transmit FIFO buffer read Returns the...

Page 378: ...Register FBOIR Address 0x7003 Bit s Value Description 7 0 The Interrupt code to the Flexible Interface Module processor has been cleared by the FIM Read only 1 Flexible Interface Module processor int...

Page 379: ...e Outbound Interrupt Register is set by the Flexible Interface Module processor The code values are user defined FIMB Master Mode Register FBMMR Address 0x7005 Bit s Value Description 7 0 These bits a...

Page 380: ...emory addresses 0x10 0x17 and bytes 8 15 are mapped to data memory addresses 0x90 0x97 These registers are read write for the main processor FIMB Port Expansion x Register FBPE0R Address 0x7017 FBPE1R...

Page 381: ...Master System Reset Register MSRR Address 0x0436 Bit s Value Description 7 3 These bits are reserved and should be written with zeros 2 wr only 0 No reset of Flexible Interface Module B Reads always...

Page 382: ...t F 1 Override Port F operation FIM A or FIM B controls the port 4 0 Normal operation for Port E 1 Override Port E operation FIM A or FIM B controls the port 3 0 Normal operation for Port D 1 Override...

Page 383: ...d the resulting counter value can be read out at any point Both the line and column parity values are available for ECC allowing for 1 bit error correction and 2 bit error detection Data can be read i...

Page 384: ...a 3 Register ECD3R 0x05C3 R W 00000000 ECC Control Register ECCR 0x05C4 R W 00000000 ECC CP Read Register ECPR 0x05C4 R W 00000000 ECC CP Read Shifted Register ECPSR 0x05C6 R W 00000000 ECC Write 0 Re...

Page 385: ...o ECCR Select the initial value and read data direction if desired 2 If desired the initial state of the line parity bits can be set by writing to ECWxR and the column parity bits by writing to ECPR o...

Page 386: ...ECC Data 1 Register ECD1R Address 0x05C1 Bit s Value Description 7 0 Read LP CRC bits 15 8 Write Data byte for ECC CRC calculation ECC Data 2 Register ECD2R Address 0x05C2 Bit s Value Description 7 0...

Page 387: ...to 64 KB blocks 001 CRC 32 IEEE 802 010 CRC 16 IBM USB 011 CRC 16 CCITT 100 CRC 15 CAN 101 This bit combination is reserved and should not be used 110 This bit combination is reserved and should not b...

Page 388: ...ess 0x05C9 Bit s Value Description 7 0 Read LP CRC bits 8 15 used for reverse bit order cases Write Set the state of LP CRC bits 23 16 ECC Write 3 Register ECW3R Address 0x05CA Bit s Value Description...

Page 389: ...Master transmit master receive slave transmit and slave receive modes Multi master mode General call address detection in slave mode The I2 C peripheral does not support the high speed 3 4 Mbit s mod...

Page 390: ...Rabbit 6000 User s Manual digi com 390 35 1 1 Block Diagram...

Page 391: ...SGCD2R SGCD3R 0x0588 0x0589 0x058A 0x058B R W 00000000 00000000 00000000 00000000 Serial Port G Data Register SGDR 0x058C R W 00000000 Serial Port G Slave Address Registers SGSA0R SGSA1R SGSA2R SGSA3R...

Page 392: ...Clocks In the master mode the data clock for the I2 C peripheral is based on the peripheral clock and is divided by the 16 bit divider in SGCDxR In the slave mode the external master provides the cloc...

Page 393: ...o the interrupt service routine to the internal interrupt table 2 Configure SGMCR to select the I2 C interrupt priority and SGC1R to select which interrupts will occur In the interrupt service routine...

Page 394: ...2 Set slave mode by clearing bit 2 and enable the controller by setting bit 1 of SGC0R 3 Monitor bits 5 and 8 of SGSxR to determine when byte has been received for the correct slave address Bits 1 and...

Page 395: ...slave receive mode 5 0 No effect 1 Initiate a stop condition after transferring the next data byte on the I2 C bus master mode only 4 0 No effect 1 Initiate a start condition when the I2C bus is idle...

Page 396: ...hen a stop condition is detected 1 Enable interrupt when a stop condition is detected 2 0 No interrupt on non ACK response 1 Enable interrupt on non ACK response from slave after transmit byte complet...

Page 397: ...d only 1 Byte has been received This bit is cleared by the read of this register 4 0 No byte transmitted Read only 1 Byte has been transmitted This bit is cleared by the read of this register 3 0 The...

Page 398: ...ll address match Read only 1 General call address match slave mode While the underlying status bit is cleared by the read of SGS0R the bit latched in the interface remains set until the next read of S...

Page 399: ...and should always be written with zeros Serial Port G Data Register SGDR Address 0x058C Bit s Value Description 7 0 Read Returns the byte received from the I2C bus Write Data byte for transmission on...

Page 400: ...Timing Control 0 Register SGTC0R Address 0x0594 Bit s Value Description 7 0 Bits 7 0 of the data acknowledgement delay Serial Port G Timing Control 1 Register SGTC1R Address 0x0595 Bit s Value Descrip...

Page 401: ...y 1 SDA is high Serial Port G Bus Monitor 1 Register SGBM1R Address 0x0599 Bit s Value Description 7 0 These bits are reserved and should be written as zeros Serial Port G Bus Monitor 2 Register SGBM2...

Page 402: ...itten with zeros Reads return zeros 3 0 Parallel Port PE1 is used for SCL 1 Parallel Port PE5 is used for SCL 2 0 Parallel Port PE0 is used for SDA 1 Parallel Port PE4 is used for SDA 1 0 00 The seria...

Page 403: ...trobes are available to reduce current draw by the attached memory devices Figure 36 1 shows a typical current draw as a function of the main clock frequency when all of the network ports and analog f...

Page 404: ...04 36 1 1 Registers Register Name Mnemonic I O Address R W Reset Global Control Status Register GCSR 0x0000 R W 11000000 Global Power Save Control Register GPSCR 0x000D R W 00000000 Global Clock Doubl...

Page 405: ...isabling any peripherals not being used will help reduce power The A D converter and D A converter peripherals have sleep modes that can be enabled when they should remain active but are not being dir...

Page 406: ...It is recommended that in that situation the Rabbit 6000 be performing a tight polling loop in another memory device either SRAM or external parallel flash waiting for a wake up event Table 36 2 Cloc...

Page 407: ...lf For reduced processor speeds based on the main oscillator a short chip select can be enabled in GPSCR this feature is not available when the processor is running at full speed This feature can be e...

Page 408: ...Rabbit 6000 User s Manual digi com 408...

Page 409: ...g off the 32 kHz clock the short chip select option will produce chip select signal that is the width of a single 32 kHz clock 30 5 s otherwise the timing is identical to the short chip select options...

Page 410: ...Rabbit 6000 User s Manual digi com 410...

Page 411: ...Rabbit 6000 User s Manual digi com 411...

Page 412: ...educe power consumption even more when running off the 32 kHz oscillator When self timed chip selects are enabled the chip select is only active for a short selectable period of time ranging from 165...

Page 413: ...ck from the fats clock 010 Processor clock from the fast clock Peripheral clock from the fast clock 011 Processor clock from the fast clock divided by 2 Peripheral clock from the fast clock divided by...

Page 414: ...165nS self timed chip selects for read only 4 0 Normal Chip Select timing for read cycles 1 Short Chip Select timing for read cycles not available in full speed 3 0 Normal Chip Select timing for write...

Page 415: ...cuit is disabled 00001 9 nS nominal Low time 00010 10 5 nS nominal Low time 00011 12 nS nominal Low time 00100 13 5 nS nominal Low time 00101 15 nS nominal Low time 00110 16 5 nS nominal Low time 0011...

Page 416: ...mA Core Current 32 768 kHz 25 C 5 mA I O Ring I O Ring Supply Voltage 3 3 V VDDIO 3 0 V 3 3 V 3 6 V I O Current 200 MHz 25 C Additional current for WiFi 25 C Additional current for Ethernet 25 C IIO 2...

Page 417: ...Typ Max VBAT VBAT Supply Voltage VBAT 1 08 V 1 2 V 1 32 V VBAT Current rest of device powered rest of device powered down IVBAT to be determined VBATIO VBATIO Supply Voltage rest of device powered re...

Page 418: ...yp Max Main Clock Frequency on CLKI direct clock fmain 20 MHz 200 MHz Main Clock Frequency on CLKI internal oscillator 24 MHz 42 MHz Main Clock Frequency on CLKI PLL input 20 MHz 25 MHz 42 MHz Real Ti...

Page 419: ...s 8 ns Clock to Memory Chip Select Delay TCSx 3 ns 6 ns Clock to Memory Read Strobe Delay TOEx 3 ns 6 ns Data Setup Time Tsetup 1 ns Data Hold Time Thold 0 ns Table 37 5 Memory Write Time Delays VDDCO...

Page 420: ...Rabbit 6000 User s Manual digi com 420 Figure 37 1 Memory Read and Write Cycles...

Page 421: ...Rabbit 6000 User s Manual digi com 421 Figure 37 2 Memory Read and Write Cycles Early Output Enable and Write Enable Timing...

Page 422: ...RD 3 ns 7 ns Clock to I O Buffer Enable Delay TBUFEN 3 ns 6 ns Data Setup Time Tsetup 1 ns Data Hold Time Thold 1 ns Table 37 7 External I O Write Time Delays VDDCORE 1 2 V 10 VDDIO 3 3 V 10 TA 40 C t...

Page 423: ...Rabbit 6000 User s Manual digi com 423 Figure 37 3 I O Read Cycles No Extra Wait States NOTE IOCSx can be programmed to be active low default or active high...

Page 424: ...Rabbit 6000 User s Manual digi com 424 Figure 37 4 I O Write Cycles No Extra Wait States NOTE IOCSx can be programmed to be active low default or active high...

Page 425: ...timal Use 25 200 0000 PLL 10 ns 2 wait states 12 ns 3 wait states 15 ns 3 wait state 45 ns 9 wait states 55 ns 11 wait states 70 ns 14 wait states 10 ns or faster devices 25 150 0000 PLL 10 ns 1 wait...

Page 426: ...digi com 426 14 7456 29 4912 doubler 55 ns 0 wait states 70 ns 1 wait state 55 ns devices Table 37 8 Some Recommended Clock Memory Configurations Input Frequency MHz Internal Frequency MHz Recommended...

Page 427: ...r See Table 36 2 for more details The Ethernet and Wi Fi peripherals in particular can draw a significant amount of current when powered as shown in Table 37 5 Exercise care that they are only enabled...

Page 428: ...werdown even if the processor is running at 3 3 V normally A circuit to switch between a 1 2 2 0 V battery and the main power can use the RESOUT pin to switch the power source for the VBATIO pin R is...

Page 429: ...Rabbit 6000 User s Manual digi com 429 38 PACKAGE SPECIFICATIONS AND PINOUT 38 1 Ball Grid Array Packages 38 1 1 Pinout 17mm 17mm BGA 292 Figure 38 1 BGA 292 Pinout Looking Through the Top of Package...

Page 430: ...Rabbit 6000 User s Manual digi com 430 38 1 2 Pinout 15mm 15mm BGA 233 Figure 38 2 BGA 233 Pinout Looking Through the Top of Package...

Page 431: ...Rabbit 6000 User s Manual digi com 431 38 1 3 Mechanical Dimensions and Land Pattern Figure 38 3 a BGA 292 Package Outline...

Page 432: ...and assume a single conductor between solder lands Table 38 1 Ball and Land Size Dimensions Nominal Ball Diameter mm Tolerance Variation mm Ball Pitch mm Nominal Land Diameter mm Land Variation mm 0...

Page 433: ...406 0 016 C Land to Mask Clearance min 0 076 0 003 D Conductor Width max 0 127 0 005 E Conductor Spacing typ 0 127 0 005 F Via Capture Pad max 0 406 0 016 G Via Drill Size max 0 203 0 008 Table 38 2...

Page 434: ...Direction Function BGA 292 Ball BGA 233 Ball Hardware CLK Output Internal Clock Output M19 G17 CLK_RTC Input 32KHz Clock R1 M1 CLK_HSI Input Main Clock Crystal In P20 K16 CLK_HSO Bidirectional Main Cl...

Page 435: ...L3 K3 D1 E4 A18 A19 F17 D20 E18 E19 G17 A13 N A A0 Output Address Bus 0 Bar C11 N A D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Bidirectional Data Bus D3 G4 C3 G3 D2 E2 C1 H3 D17 B20 C18 D1...

Page 436: ...ip Select F20 N A CS1 Output Memory Chip Select T3 K3 CS2 Output Memory Chip Select G1 N A Output Enables OE0 Output Memory Output Enable C16 N A OE1 Output Memory Output Enable F3 N A Write Enables W...

Page 437: ...C E17 D19 C19 B18 D14 A17 A16 A15 A16 D14 B15 C14 D13 A15 B14 C13 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Input Output Parallel Port D H18 G20 G19 H17 G18 F19 F18 C20 C17 E15 B17 C16 F14 D15 A17 C15 PE7 PE6...

Page 438: ...H1 PH0 Input Output Parallel Port H E3 C2 H2 J2 K2 L2 G2 F1 E4 C3 A2 E3 G4 C2 F4 D3 Ethernet TX TX Output Transmit A6 A5 A5 A6 RX RX Input Receive A4 A3 A3 A4 SPEED_LED TX_LED LINK_LED RX_LED Output L...

Page 439: ...ble Y3 P3 RXHP Output Receiver High Power V4 N4 SCLK Output Serial Bus Clock U5 R3 SDATA Output Serial Bus Data V5 U2 SEN Output Serial Bus Enable W5 T3 TX_ON Output Transmitter Enable W4 P4 VGA4 VGA3...

Page 440: ...DA_RSET Bidirectional D A resistor U12 P9 S_VIN Input RSSI A D Input Y20 U15 S_AD_REF Input RSSI A D Top Ref W20 P14 S_AD_REF Input RSSI A D Bottom Ref W19 R14 IN7 IN6 IN5 IN4 IN3 IN2 IN1 IN0 Input A...

Page 441: ...NS A 1 Alternate Parallel Port Pin Outputs Table A 1 Alternate Parallel Port A and B Pin Outputs Pin Alternate Output Options Serial Clock External I O Bus Slave Port PA 7 0 ID 7 0 SD 7 0 PB7 IA5 SLVA...

Page 442: ...ER C2 TXF PC1 TXD I1 TIMER C1 RCLKF PC0 TXD I0 TIMER C0 TCLKF PD7 IA7 I7 PWM3 SCLKC PD6 TXA I6 PWM2 TXE PD5 IA6 I5 PWM1 RCLKE PD4 TXB I4 PWM0 TCLKE PD3 IA7 I3 TIMER C3 SCLKD PD2 SCLKC I2 TIMER C2 TXF...

Page 443: ...PWM1 RCLKE PG4 FIMB4 I4 PWM0 TCLKE PG3 FIMB3 I3 TIMER C3 SCLKD PG2 FIMB2 I2 TIMER C2 TXF PG1 FIMB1 I1 TIMER C1 RCLKF PG0 FIMB0 I0 TIMER C0 TCLKF PH7 I7 PWM3 SCLKC D15 PH6 I6 PWM2 TXE D14 PH5 I5 PWM1...

Page 444: ...lave Port Serial Ports A D Serial Ports E F PA 7 0 SD 7 0 PB7 PB6 SCS PB5 SA1 PB4 SA0 PB3 SRD PB2 SWR PB1 SCLKA PB0 SCLKB PC7 yes RXA RXE PC6 PC5 yes RXB RCLKE PC4 TCLKE PC3 yes RXC RXF PC2 PC1 yes RX...

Page 445: ...upt FIM Slave Port Serial Ports A D Serial Ports E F PF7 INT2 7 FIMA7 PF6 INT2 7 FIMA6 PF5 INT2 7 FIMA5 PF4 INT2 7 FIMA4 PF3 INT2 7 FIMA3 PF2 INT2 7 FIMA2 PF1 INT2 7 FIMA1 PF0 INT2 7 FIMA0 PG7 INT2 7...

Page 446: ...cifications 228 240 fast A D converter 228 fast D A converter 228 slow A D converter 229 B block diagram analog components 230 241 bootstrap 36 breakpoints 361 clocks 17 DMA channels 252 Error Check a...

Page 447: ...erview 249 priorities 258 register descriptions 264 registers 253 setup 256 timed requests 250 transfer priorities 258 transfer priority 258 transfer rates 259 transfers 251 use with peripherals 263 E...

Page 448: ...ISR 326 internal interrupt vector table 84 interrupt priorities 86 memory management 60 Network Port B 291 293 Network Port C 316 operation 84 Parallel Port D 117 Parallel Port E 129 Parallel Port F 1...

Page 449: ...external I O bus 100 operation 103 overview 100 register descriptions 104 registers 102 slave port enabled 100 SPCR setup 100 Parallel Port C 106 alternate input functions 107 alternate output functio...

Page 450: ...odulator See PWM PWM 340 block diagram 343 channels 344 clocks 344 dependencies 344 DMA channels 342 interrupts 340 344 345 example ISR 345 operation 345 outputs 340 342 overview 340 register descript...

Page 451: ...284 DyLnR 279 DySA0R 280 DySA1R 280 DySA2R 281 DySCR 277 DyTBR 272 DyTMR 273 ECC0R 388 ECC1R 388 ECCR 387 ECD0R 386 ECD1R 386 ECD2R 386 ECD3R 386 ECPR 387 ECPSR 387 ECW0R 388 ECW1R 388 ECW2R 388 ECW3...

Page 452: ...R 321 PADR 98 PAxCR 98 PBDDR 104 PBDR 104 PBxCR 104 PCAHR 111 PCALR 110 PCDCR 111 PCDDR 110 PCDR 110 PCFR 111 PCxCR 112 PDAHR 120 PDALR 119 PDB0R 121 PDB1R 121 PDB2R 122 PDB3R 122 PDB4R 122 PDB5R 122...

Page 453: ...3 210 SxSR asynch mode 194 211 SxSR clocked serial mode 195 SxSR HDLC mode 212 TACR 168 TACSR 167 TAECR 167 TAPR 167 TATxR 168 TBCLR 175 TBCMR 175 TBCR 173 TBCSR 173 TBLxR 174 TBMxR 174 TBSLxR 174 TBS...

Page 454: ...andshake Control Register 355 I O Handshake Select Register 355 I O Handshake Timeout Register 356 Slave Port Control Register 359 external interrupts 89 Interrupt x Control Register 92 93 Flexible In...

Page 455: ...B MII PHY Address Register 304 Network Port B MII Read LSB Register 305 Network Port B MII Read MSB Register 305 Network Port B MII Register Address Register 304 Network Port B MII Reset Register 304...

Page 456: ...347 PWM Block Pointer Register 347 PWM LSB 0 Register 346 PWM LSB 1 Register 346 PWM LSB x Register 347 PWM MSB x Register 347 Quadrature Decoder 335 Quad Decode Control Register 339 Quad Decode Contr...

Page 457: ...ation and data encoding 206 Serial Ports A D 184 block diagram 186 clocks 188 data clocks 185 dependencies 188 interrupts 189 operation 190 asynchronous mode 190 clocked serial mode 184 191 overview 1...

Page 458: ...am 163 capabilities 162 clocks 165 dependencies 165 interrupts 162 165 166 example ISR 166 operation 166 overview 161 register descriptions 167 registers 164 reload register operation 161 Timer B 169...

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