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Rabbit 6000 User’s Manual
454
DMA channels ..................................................253
DMA Master Auto-Load LSB Register .......264
DMA Master Auto-Load MSB Register ......265
DMA Master Control Register .....................266
DMA Master Control/Status LSB Register ..264
DMA Master Control/Status MSB Register .264
DMA Master Halt LSB Register ..................265
DMA Master Halt MSB Register .................265
DMA Master Request 0 Control Register ....268
DMA Master Request 1 Control Register ....269
DMA Master Timing Control Register ........267
DMA Timed Request Control Register ........270
DMA Timed Request Divider High Register .....
DMA Timed Request Divider Low Register 270
DMA y Buffer Complete Register ...............266
DMA y Buffer Unused[15:8] Register .........274
DMA y Buffer Unused[7:0] Register ...........274
DMA y Control Register ..............................278
DMA y Destination Addr[15:8] Register .....282
DMA y Destination Addr[23:16] Register ...282
DMA y Destination Addr[7:0] Register .......281
DMA y Initial Addr[15:8] Register ..............275
DMA y Initial Addr[23:16] Register ............276
DMA y Initial Addr[7:0] Register ................275
DMA y Length[15:8] Register .....................279
DMA y Length[7:0] Register .......................279
DMA y Link Addr[15:8] Register ................283
DMA y Link Addr[23:16] Register ..............284
DMA y Link Addr[7:0] Register ..................283
DMA y Source Addr[15:8] Register ............280
DMA y Source Addr[23:16] Register ..........281
DMA y Source Addr[7:0] Register ..............280
DMA y Special Control Register .................277
DMA y Termination Byte Register ..............272
DMA y Termination Mask Register .............273
Error Check and Correction ..............................384
ECC Control Register ...................................387
ECC Count 0 Register ..................................388
ECC Count 1 Register ..................................388
ECC CP Read Register .................................387
ECC CP Read Shifted Register ....................387
ECC Data 0 Register ....................................386
ECC Data 1 Register ....................................386
ECC Data 2 Register ....................................386
ECC Data 3 Register ....................................386
ECC Write 0 Register ...................................388
ECC Write 1 Register ...................................388
ECC Write 2 Register ...................................388
ECC Write 3 Register ...................................388
external I/O control ...........................................352
I/O Bank x Control Register .........................357
I/O Bank x Extended Register ......................358
I/O Handshake Control Register ..................355
I/O Handshake Select Register .....................355
I/O Handshake Timeout Register .................356
Slave Port Control Register ..........................359
external interrupts ................................................89
Interrupt x Control Register ......................92, 93
Flexible Interface Modules ................................370
FIMA Code LSB Register ............................377
FIMA Code MSB Register ...........................377
FIMA Control Byte x Register .....................376
FIMA Data FIFO Register ............................374
FIMA FIFO Status Register .........................374
FIMA Inbound Interrupt Register ................375
FIMA Interrupt Control Register ..................375
FIMA Outbound Interrupt Register ..............375
FIMA Port Expansion x Register .................376
FIMA Rx Status FIFO Register ....................374
FIMB Code LSB Register ............................381
FIMB Code MSB Register ...................381, 382
FIMB Control Byte n Register .....................380
FIMB Data FIFO Register ............................377
FIMB FIFO Status Register ..........................378
FIMB Inbound Interrupt Register .................379
FIMB Interrupt Control Register ..................379
FIMB Master Mode Register ........................379
FIMB Outbound Interrupt Register ..............378
FIMB Port Expansion n Register .................380
FIMB Rx Status FIFO Register ....................377
I
C peripheral ....................................................391
Serial Port G Bus Monitor 0 Register ...........401
Serial Port G Bus Monitor 1 Register ...........401
Serial Port G Bus Monitor 2 Register ...........401
Serial Port G Bus Monitor 3 Register ...........401
Serial Port G Clock Division 0 Register .......398
Serial Port G Clock Division 1 Register .......399
Serial Port G Clock Division 2 Register .......399
Serial Port G Clock Division 3 Register .......399
Serial Port G Control 0 Register ...................395
Serial Port G Control 1 Register ...................396
Serial Port G Control 2 Register ...................396
Serial Port G Control 3 Register ...................396
Serial Port G Data Register ..........................399
Serial Port G Main Control Register ............402
Serial Port G Slave Address 0 Register ........399
Serial Port G Slave Address 1 Register ........399
Serial Port G Slave Address 2 Register ........400
Serial Port G Slave Address 3 Register ........400
Serial Port G Status 0 Register .....................397
Serial Port G Status 1 Register .....................398
Serial Port G Status 2 Register .....................398
Serial Port G Status 3 Register .....................398
Serial Port G Timing Control 0 Register ......400
Serial Port G Timing Control 1 Register ......400
Serial Port G Timing Control 2 Register ......400
Serial Port G Timing Control 3 Register ......400
Summary of Contents for 6000
Page 1: ...Rabbit 6000 Microprocessor User s Manual 90001108_J...
Page 11: ...Rabbit 6000 User s Manual digi com 11 1 3 Block Diagram Figure 1 1 Rabbit 6000 Block Diagram...
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Page 234: ...Rabbit 6000 User s Manual digi com 234 Figure 22 3 Sample Slow A D Converter Circuit...
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Page 420: ...Rabbit 6000 User s Manual digi com 420 Figure 37 1 Memory Read and Write Cycles...