Rabbit 6000, User Manual

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Rabbit 6000 User’s Manual
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307
Master System Configuration Register (MSCR) (Address = 0x0434)
Bit(s) Value Description
7 0 CPU clock direct from oscillator.
1
CPU clock from system PLL output (divided by two). Response to this
setting may be delayed until the PLL output is stable (roughly 200 µs
after enabling the system PLL, uses 32 kHz clock to generate delay).
6 This bit is reserved and should be written as zero.
5 0 Clock on-chip 10/100 PHY from system oscillator.
1
Enable embedded oscillator in the internal 10-100 PHY. If using this
option, the oscillator must be enabled at least 500 ns before the PHY is
enabled in ENPR. This delay must be created in software.
4 0 No reset of the internal 10/100 PHY. Reads always return zero.
(Write-
only)
1
Reset the internal 10/100 PHY hardware. This command must not be
issued until at least 600 ms after the internal PHY has been enabled in
ENPR. This delay must be created in software.
3:2 00 FIMB clock is disabled.
01 FIMB clock is identical to the CPU clock.
10 This bit combination is reserved and should not be used.
11
FIMB clock from system PLL output. Response to this setting may be
delayed until the PLL output is stable (roughly 200 us after enabling the
system PLL, uses 32 kHz clock to generate delay).
1:0 00 FIMA clock is disabled.
01 FIMA clock is identical to the CPU clock.
10 This bit combination is reserved and should not be used.
11
FIMA clock from system PLL output. Response to this setting may be
delayed until the PLL output is stable (roughly 200 µs after enabling the
system PLL, uses 32 kHz clock to generate delay).