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Rabbit 6000 User’s Manual
digi.com
348
31. E
XTERNAL
I/O C
ONTROL
31.1 Overview
The Rabbit 6000’s external I/O space consists of 64KB that is accessed by prefixing a read or write instruc-
tion with the
IOE
instruction. These accesses can go onto the memory bus or onto the external I/O bus
(described below). There are three dedicated signal pins (/IORD, /IOWR, /BUFEN) that toggle for all
external I/O accesses, and eight I/O strobes that can be associated with this external I/O space and directed
out on Parallel Ports C–H.
In addition, a handshaking signal input can be enabled on any Parallel Port E pin, and can be used to pause
an external I/O transaction until the external device is ready to complete the transaction. A timeout period
can be defined to ensure that the processor is not held indefinitely by a misbehaving external device.
The drive strength and slew rate can be controlled for the /IORD, /IOWR, and /BUFEN pins. In addition, a
75 k
pullup or pulldown resistor can be enabled for the pins.
31.1.1 External I/O Bus
The Rabbit 6000 can enable a separate external I/O bus for external devices to keep bus loading on the
memory bus at an acceptable level. This bus consists of eight data lines on Parallel Port A and up to eight
address lines on Parallel Port B; two of the address lines are also available on Parallel Port D. If desired,
Parallel Port H can be used for an additional eight data lines for 16-bit accesses.
Note that if the 16-bit mode is enabled (using parallel port H as the upper byte), it does not behave the
same as 16-bit accesses on the memory bus. The external I/O bus in 16-bit mode is word-addressable,
while the memory bus is byte-addressable. Each 16-bit external I/O write goes to a single address, while
16-bit memory bus writes span two bytes.
This functionality is mutually exclusive with the slave port and regular parallel I/O on Parallel Ports A and
B.
When enabled, the address lines of the external I/O bus hold their value until a new value is written to
them. The data lines return to a tristate mode after each transaction.
See Section 31.1.2 for memory timing for external I/O accesses.
Summary of Contents for 6000
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