Phytec phyCORE-PXA255, Hardware Manual

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Development Board for phyCORE-PXA255
38 
PHYTEC Meßtechnik GmbH 2004 L-657e_0
CF control register 1 is used to set the memory interface. The CF card
interface can operate in TruIDE mode if the register bit is set to 0. The
PXA255 controller’s PCMCIA interface does not support TruIDE
mode. Therefore the /CF_PCE1 signal is linked with A11=’0’ and the
/CF_PCE2 signal is linked with A11=’1’. Both signals are active
during 8-bit as well as 16-bit accesses. If register bit 0 is set to ’0’ then
the memory mode of the CF card is configured. This memory
interface is supported directly by the PXA255.
REG ADDR D7 D3 D2 D1 D0
CF1 0x3001002 Res Res Res Res IDE/MEM
RW R/W=0 R/W=0 R/W=0 R/W=0 R=1/W=1
Table 28: CF Card Control Register 1
IDE/MEM Setting this bit to "1" turns on the TrueIDE mode,
writing a "0" selects the memory mode.
The CF card settings for Reset and RDY are made in CF control
register 2. With RES_POL the polarity of the reset signal can be set
and with RESENA the Reset can be activated. RDYENA connects the
RDY signal of the CF card to the controller signal PWAIT. The RDY
signal can be read on the RDY bit.
REG ADDR D7 D3 D2 D1 D0
CF2 0x3001004 Res RDY RDYENA RES_POL RESENA
RW R/W=0 R/W R/W R/W R=1/W=1
Table 29: CF Card Control Register 2
RESENA Activates the CF card reset.
RESPOL Indicates the polarity for the CF card reset.
RDYEN Connects the RDY input with PWAIT.
RDY Returns the state of the RDY signal.