Phytec phyCORE-PXA255, Hardware Manual

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Development Board for phyCORE-PXA255
74 
PHYTEC Meßtechnik GmbH 2004 L-657e_0
Pin Number Signal I/O Comments
Pin row X17C
14C NSSP_CLK I/O Network SPI Clock signal, use for CAN
Controller
Alternative: GPIO 81
15C NSSP_TxD I/O Network SPI TxD signal, use for CAN
Controller
Alternative: GPIO 83
16C NSSP_RxD I/O Network SPI RxD signal, use for CAN
Controller
Alternative: GPIO 84
18C IR_TXD O IrDA TxD
Alternative: GPIO 47
19C IR_RXD I IrDA RxD
Alternative: GPIO 46
20C FF_RI_DETECT O RI-Detect FF-UART (for interrupt)
21C FF_/INVALID O Invalid level FF_UART
23C /ACRESET O /RESET AC97
24C SYNC I/O SYNC AC97
Alternative: GPIO 31
25C BITCLK I/O BITCLK
Alternative: GPIO 28
26C SDATA_IN_1 I/O SDATA_IN 1 AC97 Interface
Alternative: GPIO 32
28C SDATA_IN_0 I/O SDATA_IN0 AC97 Interface
Alternative: GPIO 29
29C SDATA_OUT I/O SDATAOUT AC97 Interface
Alternative: GPIO 30
30C SDA I/O I
2
C data from processor
31C SCL I I
2
C clock from processor
33C /LAN_LED_A- O Not connected
34C /LAN_LED_B O Not connected
35C LAN_TPI- O Not connected
36C LAN_TPO- O Not connected
38C OTG_ID I OTD ID Input USB Controller
39C PWM0 O PWM output #0
Alternative: GPIO 16
40C PWM1 O PWM output #1
Alternative: GPIO 17
41C /TRST O JTAG reset
43C H_DP2 IO USB H_DP2
44C H_DM2 IO USB H_DM2
45C MMC_CS_1 O MMC_C1 for external MMC card
Alternative: GPIO 8