Phytec phyCORE-PXA255, Hardware Manual

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Development Board for phyCORE-PXA255
72 
PHYTEC Meßtechnik GmbH 2004 L-657e_0
Pin Number Signal I/O Comments
Pin row X17B
1B DEV_RES I Reset for USB, CAN and Ethernet Device
only
2B GPIO_3 I/O Processor I/O port,
alternative: interrupt
3B GPIO_1 I/O Processor I/O port,
alternative: interrupt
4B, 9B, 14B,
19B, 24B, 29B,
34B, 39B, 44B,
49B, 54B, 59B,
64B, 69B, 74B,
79B
GND - Ground 0 V
5B /CS_3 I/O Freely available /CS signal of the processor,
alternative: GPIO79
6B /CS_5 I/O Chip Select signal of the processor, can be
used to access the LAN controller,
alternative: GPIO33
7B /OE O Output-enable signal of the processor
8B, 10B, 11B,
12B, 13B, 15B,
16B, 17B, 23B,
25B, 26B, 27B
36B
A0, A3, A5,
A6, A8, A11,
A13, A14, A16,
A19, A21, A22,
A25
I/O Address lines
18B, 20B, 21B,
22B, 28B, 30B,
31B, 32B, 37B,
38B, 40B, 41B,
42B, 43B, 45B,
46B
D0, D3, D5,
D6, D8, D11,
D13, D14, D16,
D17, D21, D23,
D24, D26, D29,
D31
I/O Data lines
33B,
35B
DQM_0,
DQM_3
o Byte enable signals
47B
/CS_0
O Chip Select for on-board Flash
48B /CS_1 I/O /CS-Signal for second on-board
16-bit Flash,
alternative: GPIO15
50B
51B
52B
53B
/SDCS_0
/SDCS_1
/SDCS_2,
/SDCS_3
O /CS SDRAM bank #0
/CS SDRAM bank #1
/CS SDRAM bank #2
/CS SDRAM bank #3
55B
/SDCLK_2
O Clock signal for synchronous memory
56B /SDRAS O /SDRAS control signal for SDRAM
57B
/SDCAS
O /SDCAS control signal for SDRAM