Phytec phyCORE-PXA255, Hardware Manual

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GPIO Expansion

PHYTEC Meßtechnik GmbH 2004 L-657e_0
73
Pin Number Signal I/O Comments
Pin row X17B
58B /PKSEL I/O Card0/1 select
alternative: GPIO 54
60B /PWE I/O PCMCIA memory write signal and I/O
write signal
alternative: GPIO 49
61B /POE I/O PCMCIA memory read signal
alternative: GPIO 48
62B /PIOR I/O PCMCIA I/O write signal
alternative: GPIO 50
63B /PIOW I/O PCMCIA I/O read signal
alternative: GPIO 51
65B /LAN_IRQ I/O Interrupt LAN controller
66B /OTG_CS I /CS signal for USB controller (PXA /CS_2
or /CS_4)
67B /OTG_INT1 I Interrupt /INT1 signal USB controller
68B /OTG_INT2 I Interrupt /INT2 signal USB controller
70B, 71B,
72B, 73B,
75B, 76B
77B,
78B
80B
L_DD0, L_DD1,
L_DD2, L_DD4,
L_DD7, L_DD9,
L_DD10,
L_DD12,
L_DD15
I/O LCD data bus
alternative: GPIO 58, GPIO 59, GPIO 62,
GPIO 65, GPIO 67, GPIO 68, GPIO 70,
GPIO 73
Pin row X17C
1C, 2C +3V3 P Supply v3.3 VDC
3C, 7C, 12C,
17C, 22C, 27C,
32C, 37C, 42C,
47C, 52C, 57C,
62C, 67C 72C,
77C
GND P Ground 0 V
4C VMMC P Optional supply voltage for internal MMC
card
5C VBAT P Input for external battery
6C OTG_5V I USB Controller VDD_5V Pin
8C, 9C /H_OC1,
/H_OC2
I USB Controller Over Current Inputs Cannel
1 /2
10C /RESIN I/O /Reset input for reset controller at U9
11C /RESET_OUT I/O /Reset output of the PXA255 processor
13C NSSP_FRM I/O Network SPI Frame signal, use for CAN
Controller
alternative: GPIO 82