Phytec phyCORE-PXA255, Hardware Manual

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Development Board for phyCORE-PXA255
70 
PHYTEC Meßtechnik GmbH 2004 L-657e_0
Pin Number Signal I/O Comments
Pin Row X17A
1A CLKIN I Optional external clock input of the
processor
2A, 7A, 12A,
17A, 22A, 27A,
32A, 37A, 42A,
47A, 52A, 57A,
62A, 67A, 72A,
77A
GND - Ground 0 V
3A GPIO2 I/O Processor I/O port,
alternative: interrupt
4A GPIO0 I/O Processor I/O port,
alternative: interrupt
5A /CS_2 I/O Freely available /CS signal of the processor,
alternative: GPIO78
6A /CS_4 I/O Chip Select signal of the processor, can be
used to access the USB controller,
alternative: GPIO80
8A
/WE
O Write-enable signal for SDRAM, SRAM
and Flash devices. Please note that the
/PWE signal must be used for I/O
components.
9A, 10A, 11A,
13A, 14A, 15A,
16A, 18A, 24A,
25A, 26A, 28A,
36A
A1, A2, A4, A7,
A9, A10, A12,
A15, A17, A18,
A20, A23, A24
I/O Address lines
19A, 20A, 21A,
23A, 29A, 30A,
31A, 33A, 38A,
39A, 40A, 41A,
43A, 44A, 45A,
46A
D1, D2, D4, D7,
D9, D10, D12,
D15, D18, D19,
D20, D22, D25,
D27, D28, D30
I/O Data lines
34A, 35A
DQM_1,
DQM_2
O Byte enable signals
48A RDY I/O Ready signal of the processor,
alternative: GPIO 18
49A RDnWR O Bus control signal of the processor