Omega CL3001, User Manual, Page: 58 / 104

4) Programming the STB and SRE
By resetting (to 0) the bits in the SRE, you can mask (disable)
associated bits in the serial poll status byte. Bits set to 1 enable
the associated bit in the serial poll status byte.
5) Event Status Register (ESR)
The Event Status Register is a two-byte register in which the
higher eight bits are always 0, and the lower eight bits represent
various conditions of the CL3001. The ESR is cleared (set to 0)
when the power is turned on, and every time it is read.
Many of the remote commands require parameters. Improper
use of parameters causes command errors to occur. When a
command error occurs, bit CME (5) in the Event Status Register
(ESR) goes to 1 (if enabled in ESE register), and the error is
logged in the error queue.
6) Event Status Enable (ESE) Register
A mask register called the Event Status Enable register (ESE)
allows the controller to enable or mask (disable) each bit in the
ESR. When a bit in the ESE is 1, the corresponding bit in the
ESR is enabled. When any enabled bit in the ESR is 1, the ESB
bit in the Serial Poll Status Byte also goes to 1. The ESR bit
stays 1 until the controller reads the ESR, does a device clear, a
selected device clear, or sends the reset or *CLS command to
the CL3001. The ESE is cleared (set to 0) when the power is
turned on.
7) Bit Assignments for the ESR and ESE
The bits in the Event Status Register (ESR) and Event Status
Enable register (ESE) are assigned as shown in Figure 35.
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