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NXP Semiconductors i.MX RT500, Hardware Design Manual

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NXP Semiconductors

IMXRT500HDG

i.MX RT500 Hardware Design Guide

VDD_AO1V8

1

2

3

4

5

PMIC_MODE0/1

VDD1V8, VVD1V8_1

VDDIO_0, 1, 2, 3, 4

VDDA_BIAS

VDDIO_3(3.3V)

VDDCORE

RESETN

VDDA_ADC1V8, VREFP

ERR050716: VDDIO_x should be

powered at same time as VDD1V8

Figure 2. Power-on sequence

The power-on sequences are shown in the 

Figure 2

 are as follows:

1.

VDD_AO1V8

, 

VDD1V8

, and 

VDD1V8_1

 should be powered first. If using PMIC, mode

pins are pulled-up to always-on supply until mode pins are active.

2.

VDDA_ADC1V8

 and 

VREFP

 can be powered concurrently with 

VDD_AO1V8

 and

VDD1V8

 or later.

3.

VDDIO_x

 and 

VDDA_BIAS

 can be powered concurrently with 

VDD1V8

 range or later.

The delta voltage between 

VDDIO_3

 and 

VDD1V8

 must be 1.89 V or less when

VDDIO_3

 is 3.3 V.

4. Power-up 

VDDCORE

 should not be ramped-up until after all the other supplies have

completed the rampup.

5. Hold 

RESETN

 low until 

VDDCORE

 is valid when PMIC is used. The only difference

when using internal 

VDDCORE LDO

 (

LDO_ENABLE

 = 1) is that internal PMC releases

internal 

RESETN

 when 

VDDCORE

 is stable.

3.6 NXP PCA9420 PMIC

The NXP PCA9420 PMIC designed to be used with the i.MX RT500 and i.MX RT600

microcontrollers. This PMIC has two LDO regulators and two switch-mode regulators.
This PMIC is available in two small packages:

IMXRT500HDG

All information provided in this document is subject to legal disclaimers.

© 2022 NXP B.V. All rights reserved.

User guide

Rev. 0 — 15 November 2022

9 / 48

Summary of Contents for i.MX RT500

Page 1: ...15 November 2022 User guide Document information Information Content Keywords IMXRT500HDG i MX RT500 MIMXRT595 EVK Abstract This user guide provides details about the system hardware design to help t...

Page 2: ...T FC8_I2C MIPI BUS PDM SWD JTAG UART I2C RST USER KEY x2 FlexSPI1 FlexSPI0 SD0 HS SPI GPIO FLEX IO ADCs I3C0 FC1_I2S RT595 AB M 2 Mini connector QSPI NOR FLASH IS25WP064AIBLE QSPI NOR FLASH MX25UM5134...

Page 3: ...ming ITM Instrumentation Trace Macrocell LDO Low Dropout Regulator MCU Microcontroller Unit MLCCs Multi layer Ceramic Capacitors OTP One Time Programmable PCB Printed Circuit board PFM Pulse Frequency...

Page 4: ...ip analog functions Power rail MIN V TYP V MAX V Decoupling and bulk capacitors min qty Description VDD_ AO1V8 1 71 1 8 1 89 1 0 22 F 1 1 F 1 8 V supply for always on features It includes the RTC modu...

Page 5: ...performing any OTP read write function the VDDCORE voltage must be set to 1 0 V or higher when LDO_ENABLE is externally tied high or low 3 For the ADC analog reference VREFP is a 1 8 V reference that...

Page 6: ...sented for the three main capacitors used in the decoupling networks see Table 4 Capacitor information is presented in the Section 7 Signal Description LDO_ENABLE This input enables the on chip regula...

Page 7: ...ins continued VDDIO_0 VDDIO_1 VDDIO_2 and VDDIO_4 supplies can be powered between 1 71 V to 1 89 V VDDIO_3 can be powered between 1 71 V and 3 6 V 3 5 Power on sequence using PMIC internal LDO disable...

Page 8: ...low the user must boot at VDDCORE 1 0 V or higher Low power Normal clock mode OTP setting BOOT_CLK_SPEED or VDDCORE 1 13 V High Speed clock OTP setting BOOT_CLK_SPEED Thereafter the VDDCORE can be ad...

Page 9: ...currently with VDD1V8 range or later The delta voltage between VDDIO_3 and VDD1V8 must be 1 89 V or less when VDDIO_3 is 3 3 V 4 Power up VDDCORE should not be ramped up until after all the other supp...

Page 10: ...pin open MODESEL1 MODESEL0 EN_MODE_SEL_BY_PIN_x 1 x can be 0 1 2 or 3 LOW 0 HIGH 1 LOW 0 LOW 0 HIGH 1 LOW 0 HIGH 1 HIGH 1 Output voltage setting Mode setting 0 Mode setting 1 Mode setting 2 Mode setti...

Page 11: ...red as the main 3 3 V supply for the USB module and the VDDIO_3 domains SW1_OUT is configured to provide the 1 0 V CORE supply which is also used by the MIPI_DSI module SW2_OUT is the high current 1 8...

Page 12: ...Addendum document IMXRT500EC Power rail MIN V TYP V MAX V Decoupling and bulk capacitors min qty Description USB1_VDD3V3 3 0 3 3 3 6 1 0 22 F USB1 analog 3 3 V supply USB1_VBUS 3 0 5 0 5 5 1 0 22 F U...

Page 13: ...8 There is a limitation for the PLL crystal oscillator as it has a range from 5 MHz to 26 MHz crystal with a PLL multiplier range of 16 through 22 yielding a VCO frequency range of 80 MHz to 572 MHz...

Page 14: ...400 420 440 24 384 408 432 456 480 504 528 26 416 442 468 494 520 546 572 32 512 544 576 608 640 672 704 VCO range is from 80 MHz to 572 MHz Table 8 PLL frequency 5 3 Main crystal oscillator XTALIN X...

Page 15: ...bit in SYSOSCCTL0 Low Power mode saves energy by reducing the drive current after initial oscillation Oscillation levels are around 0 8 V peak to peak Do not attempt to measure the oscillation levels...

Page 16: ...the bypass mode when the low power oscillator is enabled 1 Connect the TCXO output 800mVp p minimum to the XTALIN input and float XTALOUT 2 Enable the low power oscillator by setting the LP_ENABLE bi...

Page 17: ...gister Select CLKIN by setting the SEL field to 0b001 in SYSOSCBYPASS The CLKIN function is configured in the GPIO pad control register and selected as the osc_clk with the system oscillator bypass bi...

Page 18: ...load capacitor values placed on the crystal pins also called Cx and Cy The crystal load capacitance is a crystal parameter used by the vendor to manufacture and test each crystal Crystal vendors gene...

Page 19: ...Cx Cy 2 12 5 pF 0 pF 3 pF 22 pF Example 2 Small 32 768 kHz crystal CL 9 pF CPin 3 pF CStray 0 ignore for first pass calculation Cx Cy 2 9 pF 0 pF 3 pF 15 pF Here are the definitions of the symbols use...

Page 20: ...alculating load capacitor values with absolute accuracy is futile NXP recommendation to approximate the initial load capacitor values and measure the resulting frequency eliminates many guesswork and...

Page 21: ...l Wire Output SWO provides data from the Instrumentation Trace Macrocell to improve debugging support The MIMXRT595 EVK board has an LPC4322 based Link2 debugger to save costs for users It provides a...

Page 22: ...his pin is used for JTAG boundary scan when the JTAG mode is active This pin has an internal pull up and input buffer enabled in boundary scan mode TDI In PIO0_10 JTAG Test Data In It is the serial da...

Page 23: ...exSPI_REC_ BOOT b 1100 Boot from Octal Quad SPI flash device on FlexSPI0 If an image is not found check recovery boot using SPI flash device through FlexComm The FlexComm instance used is chosen by fu...

Page 24: ...low The Serial Interface UART I2C SPI is used to program OTP external FLASH or eMMC devices Serial Download high high high Serial Master boot is used to download a boot image over the serial interface...

Page 25: ...able 14 When used with a PMIC tie this pin to the SYSRSTb pin or POWER_OK pin with a 100 Kohm external pull up to VDD_AO1V8 When used with the internal VDDCORE LDO enabled this pin should have a 100 K...

Page 26: ...see i MX RT500 Low Power Crossover Processor Data Sheet with Addendum document IMXRT500EC High Density Interconnect HDI design methods are expected to be used with the 249 FOWLP and 141 WLCSP package...

Page 27: ...il dielectric L4 is tightly coupled to L5 with a 4 mil dielectric L6 is tightly coupled to L5 with a 2 7 mil dielectric The tight coupling of signals to planes with thin dielectrics is the basis of im...

Page 28: ...oupled to the ground plane on L5 L4 Contains the main power domains and ground L5 It is a solid ground plane that is a reference that provides the return paths for L6 signals The thin dielectric betwe...

Page 29: ...diameter of 8mils with 18 mils pad Layers Trace width Mils Single ended L1_TOP L3 and L4 L6_BOTTOM 4 5 4 5 4 5 50 50 50 4 5 4 5 4 5 5 5 5 90 90 90 3 5 3 5 3 5 7 7 7 100 100 100 Impedance Ohms Trace w...

Page 30: ...hicknesses between layers 1 and 2 and layers 2 and 3 in the stack up above This HDI technique uses the via in pad process to enable efficient routing of BGA packages that have small ball pitches 7 8 H...

Page 31: ...dimensions under the package The outside ring of balls is routed on the top layer These signals may later connect to other layers but the escape route is the top layer The inside ring of balls is rout...

Page 32: ...uld generally be 1 per via decoupling capacitors plus one or two additional bulk capacitors It reduces the number of capacitors from 1 per pin to 1 per 2 or more pins on some supply domains However wh...

Page 33: ...edge of the BGA via array Placing the decoupling capacitors close to the power balls is critical to minimize inductance and ensure high speed transient current demand by the processor The following l...

Page 34: ...ble It means to keep the traces as short as possible and on the same layer The loop area is all the space between the 2 crystal traces For more details see Figure 23 MIMXRT595 EVK L1 Signals and compo...

Page 35: ...esign practices are described as follows R435 R451 51 k R450 51 k MEM_1V8 FLEXSPI0_SS0_B Frequency max 166 MHz Data DDR feature FLEXSPI0_SS0_B 0 A G F C2 15 RESET_OSPI_MEM CS ECS R443 0 B A4 RESET 7 8...

Page 36: ...ed on L1 and L3 It is poor since all HS signals between MCU and memory should be on the same layer Shorting resistors for shared components and signals It is poor because these options create stubs an...

Page 37: ...n L6 It is poor since all HS signals between MCU and memory should be on the same layer The resistors create stubs that degrade signal integrity Shorting resistors for shared components and signals It...

Page 38: ...is footprint supports 1 S26KS256SDPBHV02 2 S27KS0641DPBHI023 pin2pin with 3 3 APS6408L OBM BA pin2pin with 2 4 MX25UM51345GXDI00 Clock CE and DQS on L1 But not shared but Addr Data across L1 L3 L6 Sho...

Page 39: ...n the top layer Addr Data lines are routed across several layers It is poor since all HS signals between MCU and memory should be on the same layer and have matched lengths for signal integrity IMXRT5...

Page 40: ...annot work at the same time Populated R691 R697 R611 R620 R660 R661 R698 DNP R611 R620 R660 R661 R698 R691 R697 7 8 SD0_D0 0 A3 7 8 SD0_D1 DAT0 VCC4 K9 VDDI R612 0 A4 DAT1 RST 7 8 SD0_D2 R613 0 A5 DAT...

Page 41: ...ard schematic Figure 32 EVK external eMMC and SD card layout The eMMC and SD Card interface has many signals on multiple layers It is poor since all HS signals between MCU and memory should be on the...

Page 42: ...caps are located close to the MCU R165 0 R166 0 R182 0 R480 0 D4 VDD_AO1V8_1 _MCU_AO1V8 B2 VDD_AO1V8_2 J14 LDO LDO_ENABLE VDD1V8_A H6 VDD1V8_B H7 VDD1V8_C J7 VDD1V8_D G6 VDD1V8_E M6 E6 VDD1V8_F VDD1V...

Page 43: ...1 2 MCU_1V8 1 2 HDR 1x2 JS24 E12 VDDA_BIAS K5 USB1_VDD3V3 C160 0 22 F 10 V C186 0 22 F 10 V M8 VDDIO_3_1 _MCU_VDDIO_3 M 2 SD1 _MCU_VDDIO_4 N9 VDDIO_3_2 C199 0 22 F 10 V C314 1 0 F 10 V JUMPER DEFAULT...

Page 44: ...tance vs DC bias curves 7 21 MLCC capacitor DC bias effect recommendations The following are the recommendation for MLCC capacitor DC bias effect The recommended 10 F capacitor is the 0603 package 16...

Page 45: ...Capacitance F GRM188R61C106MA73 10 F 20 0603 16 V X5R 8 30 F 1 8 V 6 06 F 3 3 V 4 03 F 5 0 V DC Bias V 0 10 6 4 8 2 0 1 0 3 0 2 0 4 0 GRM033R61A224ME90 C DC bias capacitance 25 0degC AC0 5Vrms Capaci...

Page 46: ...ramming connections were reviewed Layout requirements and recommendations were presented with examples from the i MX RT500 EVK General high speed design and specific HDI design recommendations were di...

Page 47: ...ility in this respect Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profi...

Page 48: ...OOT_ SRC 3 0 bits 22 6 5 Boot source from ISP_Pin 2 0 23 6 6 Physical ISP pins configuration on EVK board 24 6 7 Reset pin 25 7 Layout recommendations 26 7 1 Basic PCB design recommendations 26 7 2 St...

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