NXP Semiconductors
IMXRT500HDG
i.MX RT500 Hardware Design Guide
C
x
= C
y
≈ 2(18 pF – 0 pF) – 3 pF = 33 pF
Example 4:
Small 24 MHz crystal:
C
L
= 10 pF
C
Pin
= 3 pF
C
Stray
= 0 (ignore for first pass calculation)
C
x
= C
y
≈ 2(10 pF – 0 pF) – 3 pF = 17 pF
6 DEBUG, TRACE, JTAG SCAN, and PROGRAMMING
This section provides information about the debugging and programming features of the
i.MX RT500.
6.1 Serial Wire Debug (SWD) mode
The i.MX RT500 uses SWD mode to support debugging of the Arm Cortex-M33
processor and Fusion DSP. The i.MX RT500 SWD signals are multiplexed on several
GPIO pins. The clock and data signals are initialized as SWD functions by default on
reset.
The clock signal is enabled as an input reset.
CAUTION:
Use at least 10 Kohm as an external register, but 100 Kohm pull-xxxx is
recommended for the safety of the board.
For more details, see
.
The optional Serial Wire Output (SWO) provides data from the Instrumentation Trace
Macrocell to improve debugging support.
The MIMXRT595-EVK board has an LPC4322-based Link2 debugger to save costs for
users. It provides a USB debug connection to the MCU’s SWD interface.
GPIO / Signal
Description
Recommendation
PIO2_25 / SWCLK
Serial Wire Clock (SWC) input
from the debugger. Internal
weak pull-down at reset.
Add an external 100 Kohm pull-
down.
PIO2_26 / SWDIO
Bidirectional SWD Data I/O.
Internal weak pull-up at reset.
Add an external 100 Kohm pull-
up.
PIO2_24 or PIO2_31 / SWO
Serial Wire Output (SWO)
optionally provides data from
the ITM for an external debug
tool to evaluate.
Must be selected as a function
before use.
Table 9. SWD debug
6.2 Trace signals
Trace Port Interface Unit (PIU) connections are available on the i.MX RT500, see
. The high-speed TRACE clock and data pins are multiplexed with GPIO pins.
IMXRT500HDG
All information provided in this document is subject to legal disclaimers.
© 2022 NXP B.V. All rights reserved.
User guide
Rev. 0 — 15 November 2022
21 / 48
