NXP Semiconductors
IMXRT500HDG
i.MX RT500 Hardware Design Guide
PCA9420
LX1
SW1_OUT
PSYS2
PGND2
LX2
2.2 µH
SW2_OUT
VDDCORE
LDO1_OUT
LDO2_OUT
Always-on
1.8 V
Default
3.3 V
ASYS
Default: 1.0 V
Default: 1.8 V VDDIO_1,2,3
and/or 4
VDD1V8 and
other 1.8 V power
VDD_AO1V8
VDDIO_1,2,3,
and/or 4
USB1_VDD3V3
and other
3V.3V power
E1
D1
B4
B5
A5
C5
B2
A3
i.MXRT
RT5xx
RT6xx
1 µF
6.3 V
2.2 µF
6.3 V
10 µF
6.3 V
2.2 µF
10 V
2.2 µH
10 µF
6.3 V
Figure 4. PMIC supply
PMIC Supply
Description
Power rail
LDO1_OUT
Low power always-on 1.8 V
supply
VDD_AO1V8
LDO2_OUT
3.3 V supply
USB1_VDD3V3, VDDA_BIAS,
VDDIO_3
SW1_OUT
1.0 V core supply
VDDCORE, MIPI_DSI_VDD11
SW2_OUT
High current 1.8 V supply
VDD1V8, VDD1V8_1, VDDIO_
0, VDDIO_1, VDDIO_2,
VDDIO_3, VDDIO_4, VDDA_
ADC1V8, VREFP
Table 6. PMIC supply
•
LDO1_OUT
is configured as the low power always-on supply, which also biases the
RESETN and PMIC control signal pull-up resistors.
•
LDO2_OUT
is configured as the main 3.3 V supply for the USB module, and the
VDDIO_3
domains.
•
SW1_OUT
is configured to provide the 1.0 V CORE supply, which is also used by the
MIPI_DSI
module.
•
SW2_OUT
is the high current 1.8 V supply that powers the remaining 1.8 V domains and
loads.
Note:
The
SW2 _OUT
operates in Pulse-Frequency Mode (PFM) under low load
conditions (less than 50 mA) for power efficiency and 1 MHz Pulse Width Modulation
(PWM) mode for higher loads. In the low load condition, PFM operation generates more
than 20 mV of ripple on this supply, which can propagate to the main oscillator and cause
a jitter. If the MCU operates under low load conditions and clock jitter is not acceptable,
an external 1.8 V LDO regulator must be used for the
VDD1V8
supply.
Note:
You can request specific default power supply voltages and sequences for the
PMIC and the PMIC team generates a new part number for you.
4 i.MX RT500 power domains, other power rails
Other power rails include:
IMXRT500HDG
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© 2022 NXP B.V. All rights reserved.
User guide
Rev. 0 — 15 November 2022
11 / 48
