Nuvoton NuMicro MS51 32K Series, Technical Reference Manual

Page: 404 / 491

MS51
Nov. 28, 2019 Page 404 of 491 Rev 1.00
MS51
32K
SE
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TE
CHNICAL RE
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CE MA
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UAL
SCnTSR
– SC Transfer Status Register
Register SFR Address Reset Value
SC0TSR DFH, Page 2 0000_1010 b
SC1TSR E7H, Page 2 0000_1010 b
SC2TSR EFH, Page 2 0000_1010 b
7 6 5 4 3 2 1 0
ACT BEF FEF PEF TXEMPTY TXOV RXEMPTY RXOV
R R/W R/W R/W R R/W R R/W
Bit Name Description
7 ACT Transmit /Receive in Active Status Flag (Read Only)
0 = This bit is cleared automatically when TX/RX transfer is finished
1 = This bit is set by hardware when TX/RX transfer is in active.
6 BEF Receiver Break Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received data input (RX) held in the “spacing state” (logic 0)
is longer than a full word transmiss
ion time (that is, the total time of “start bit” + data bits +
stop bits). .
Note: This bit is read only, but it can be cleared by writing 0 to it.
5 FET Receiver Frame Error Status Flag (Read Only)
This bit is set to logic 1 whenever the receive
d character does not have a valid “stop bit” (that is,
the stop bit following the last data bit or parity bit is detected as logic 0).
Note: This bit is read only, but it can be cleared by writing 0 to it.
4 PEF Receiver Parity Error Status Flag (Read Only)
This bit is set to logic 1 whenever the received character does not have a valid
“parity bit”.
Note: This bit is read only, but it can be cleared by writing 0 to it.
3 TXEMPTY Transmit Buffer Empty Status Flag (Read Only)
This bit indicates TX buffer empty or not.
Note: When TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit
high. It will be cleared when writing data into DAT(SCnDR[7:0]) (TX buffer not empty).
2 TXOVF TX Overflow Error Interrupt Status Flag (Read Only)
If TX buffer is full, an additional write to DAT(SCnDR[7:0]) will cause this bit be set to “1” by
hardware.
Note: This bit is read only, but it can be cleared by writing 0 to it.
1 RXEMPTY Receiver Buffer Empty Status Flag(Read Only)
This bit indicates RX buffer empty or not.
Note: When Rx buffer has been read by CPU, hardware sets this bit high. It will be cleared when
SC receives any new data.