MS51
Nov. 28, 2019
Page
333
of 491
Rev 1.00
MS51
32K
SE
RIES
TE
CHNICAL RE
F
EREN
CE MA
N
UAL
PWMnCON1
– PWM Control 1
Register
SFR Address
Reset Value
PWM0CON1
DFH, page 0
0000_0000 b
PWM1CON1
B5H, page 2
0000_0000 b
PWM2CON1
C5H, page 2
0000_0000 b
PWM3CON1
D5H, page 2
0000_0000 b
7
6
5
4
3
2
1
0
PWMMOD[1:0]
GP
PWMTYP
FBINEN
PWMDIV[2:0]
R/W
R/W
R/W
R/W
R/W
Bit
Name
Description
7:6
PWMMOD[1:0]
PWM mode select
00 = Independent mode.
01 = Complementary mode.
10 = Synchronized mode.
11 = Reserved.
5
GP
Group mode enable
This bit enables the group mode. If enabled, the duty of first three pairs of PWM are decided
by PWM01H and PWM01L rather than their original duty control registers.
0 = Group mode Disabled.
1 = Group mode Enabled.
Note: This bit is only valid in PWM0
4
PWMTYP
PWM type select
0 = Edge-aligned PWM.
1 = Center-aligned PWM.
3
FBINEN
FB pin input enable
0 = PWM0 output Fault Braked by FB pin input Disabled.
1 = PWM0 output Fault Braked by FB pin input Enabled. Once an edge, which matches
FBINLS (PWM0FBD.6) selection, occurs on FB pin, PWM0 channel 0~5 output Fault
Brake data in PWM0FBD register. PWM0RUN (PWM0CON0.7) will also be
automatically cleared by hardware. The PWM0 output resumes when PWM0RUN is set
again.
Note: This bit is only valid in PWM0
.
