MS51
Nov. 28, 2019
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325
of 491
Rev 1.00
MS51
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CHNICAL RE
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EREN
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N
UAL
The output frequency and duty cycle for center-aligned PWM are given by following equations:
PWM frequency =
}
,
{
2
PWMnPL
PWMnPH
F
PWM
(F
PWM
is the PWM clock source frequency divided by
PWMDIV).
PWM high level duty =
}
,
{
}
,
{
PWMnPL
PWMnPH
PWMnCHxL
PWMnCHxH
.
Operation Modes
6.6.2.5
After PnGx signals pass through the first stage of the PWM. The PWM mode selection circuit
generates different kind of PWM output modes. It supports independent mode, complementary mode,
and synchronous mode.
Independent Mode
6.6.2.6
Independent mode is enabled when PWMMOD[1:0] (PWMnCON1[7:6]) is [0:0]. It is the default mode
of PWM. PnGx output PWM signals independently.
Complementary Mode with Dead-Time Insertion
6.6.2.7
Complementary mode is enabled when PWMMOD[1:0] = [0:1]. In this mode, PnG0/2/4 output PWM
signals the same as the independent mode. However, PnG1/3/5 output the out-phase PWM signals of
PnG0/2/4 correspondingly, and ignore PnG1/3/5 Duty register {PWMnH, PWMnL} (n:1/3/5). This
mode makes PnG0/PnG1 a PWM complementary pair and so on P0G2/P0G3 and P0G4/P0G5.
In a real motor application, a complementary PWM0
output always has a need of “dead-time” insertion
to prevent damage of the power switching device like GPIBs due to being active on simultaneously of
the upper and lower
switches of the half bridge, even in a “
μs” duration. For a power switch device
physically cannot switch on/off instantly. For the MS51 PWM0, each PWM0 pair share a 9-bit dead-time down-
counter PWM0DTCNT used to produce the off time between two PWM0 signals in the same pair. On
implementation, a 0-to-1 signal edge delays after PWM0DTCNT timer underflows. The timing diagram illustrates
the complementary mode with dead-time insertion of P0G0/P0G1 pair. Pairs of P0G2/P0G3 and P0G4/P0G5
have the same dead-time circuit. Each pair has its own dead-time enabling bit in the field of PWM0DTEN [3:0].
Note
that the PWM0DTCNT and PWM0DTEN registers are all TA write protection. The dead-time control are
also valid only when the PWM0 is configured in its complementary mode. Dead-Time Insertion is
only valid in
PWM0.
P0G0
P0G1
P0G0_DT
P0G1_DT
Figure 6.6-7 PWM0 Complementary Mode with Dead-time Insertion
Synchronous Mode
6.6.2.8
Synchronous mode is enabled when PWMMOD[1:0] = [1:0]. In this mode, PnG0/2/4 output PWM
signals the same as the independent mode. PnG1/3/5 output just the same in-phase PWM signals of
