Nuvoton NuMicro MS51 32K Series, Technical Reference Manual, Page: 432 / 491

MS51
Nov. 28, 2019 Page 432 of 491 Rev 1.00
MS51
32K
SE
RIES
TE
CHNICAL RE
F
EREN
CE MA
N
UAL
CPHA = 0 CPHA = 1
sample
C
P
O
L
=
0
C
P
O
L
=
1
Clock Phase (CPHA)
C
lo
ck
P
ol
ar
ity
(
C
P
O
H
)
sample
sample sample
Figure 6.12-4 SPI Clock Formats
In SPI, a Master device always initiates the transfer. If SPI is selected as Master mode (MSTR = 1)
and enabled (SPIEN = 1), writing to the SPI data register (SPInDR) by the Master device starts the
SPI clock and data transfer. After shifting one byte out and receiving one byte in, the SPI clock stops
and SPIF (SPInSR.7) is set in both Master and Slave. If SPI interrupt enable bit is set 1 and global
interrupt is enabled (EA = 1), the interrupt service routine (ISR) of SPI will be executed.
Concerning the Slave mode, the
SS
̅̅̅̅̅
signal needs to be taken care. As shown in Figure 6.12-4 SPI
Clock Formats, when CPHA = 0, the first SPCLK edge is the sampling strobe of MSB (for an example
of LSBFE = 0, MSB first). Therefore, the Slave should shift its MSB data before the first SPCLK edge.
The falling edge of
SS
̅̅̅̅̅
is used for preparing the MSB on MISO line. The
SS
̅̅̅̅̅
pin therefore should
toggle high and then low between each successive serial byte. Furthermore, if the slave writes data to
the SPI data register (SPInDR) while
SS
̅̅̅̅̅
is low, a write collision error occurs.
When CPHA = 1, the sampling edge thus locates on the second edge of SPCLK clock. The Slave
uses the first SPCLK clock to shift MSB out rather than the
SS
̅̅̅̅̅
falling edge. Therefore, the
SS
̅̅̅̅̅
line can
remain low between successive transfers. This format may be preferred in systems having single fixed
Master and single fixed Slave. The
SS
̅̅̅̅̅
line of the unique Slave device can be tied to VSS as long as
only CPHA = 1 clock mode is used.
Note: The SPI should be configured before it is enabled (SPIEN = 1), or a change of LSBFE, MSTR,
CPOL, CPHA and SPR[1:0] will abort a transmission in progress and force the SPI system into idle
state. Prior to any configuration bit changed, SPIEN must be disabled first.