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. It also summarizes the interrupt sources, flag bits, vector addresses, enable bits, priority bits, natural
priority and the permission to wake up the CPU from Power-down mode. For details of waking CPU up
from Power-down mode, please see Section 6.2.2.3
Interrupt Priority Control Bits
Interrupt Priority Level
IPH / EIPH / EIPH1
IP / EIP / EIP2
0
0
Level 0 (lowest)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest)
Table 6.2-4 Interrupt Priority Level Setting
